imx6: pcie driver fixups

Add upstream patches needed for PCIe through a switch.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

SVN-Revision: 38511

1 files changed, 106 insertions, 0 deletions

diff --git a/target/linux/imx6/patches-3.10/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch b/target/linux/imx6/patches-3.10/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch
new file mode 100644
index 0000000000..bc9ad3c7a7
--- /dev/null
+++ b/target/linux/imx6/patches-3.10/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch
@@ -0,0 +1,106 @@
+From 93d2b52fe73294d59bbce3a6d4da031647b1f3b2 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Tue, 22 Oct 2013 15:56:40 -0700
+Subject: [PATCH] PCI: imx6: remove outbound io/mem ATU region mapping
+
+The IMX6 iATU is used for address translation between the AXI bus
+address space and PCI address space.  This is used for type0 and type1
+config cycles but is not necessary for outbound io/mem regions.
+
+This patch removes the calls that inappropriately re-configures the ATU
+viewport for outbound memory and IO after config cycles and removes them
+altogether as they are not necessary.
+
+This resolves issues with PCI devices behind switches and has been tested with
+a Gige device behind a PLX PEX860x switch.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+---
+ drivers/pci/host/pcie-designware.c |   41 +++---------------------------------
+ 1 file changed, 3 insertions(+), 38 deletions(-)
+
+--- a/drivers/pci/host/pcie-designware.c
++++ b/drivers/pci/host/pcie-designware.c
+@@ -43,7 +43,6 @@
+ #define PCIE_ATU_VIEWPORT		0x900
+ #define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
+ #define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
+-#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
+ #define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
+ #define PCIE_ATU_CR1			0x904
+ #define PCIE_ATU_TYPE_MEM		(0x0 << 0)
+@@ -264,8 +263,8 @@ static void dw_pcie_prog_viewport_cfg0(s
+ 
+ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
+ {
+-	/* Program viewport 1 : OUTBOUND : CFG1 */
+-	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
++	/* Program viewport 0 : OUTBOUND : CFG1 */
++	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+ 			  PCIE_ATU_VIEWPORT);
+ 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
+ 	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+@@ -275,38 +274,8 @@ static void dw_pcie_prog_viewport_cfg1(s
+ 			  PCIE_ATU_LIMIT);
+ 	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
+ 	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
+-}
+-
+-static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
+-{
+-	/* Program viewport 0 : OUTBOUND : MEM */
+-	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+-			  PCIE_ATU_VIEWPORT);
+-	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
+-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+-	dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
+-	dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
+-	dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
+-			  PCIE_ATU_LIMIT);
+-	dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
+-	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
+-			  PCIE_ATU_UPPER_TARGET);
+-}
+-
+-static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
+-{
+-	/* Program viewport 1 : OUTBOUND : IO */
+-	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+-			  PCIE_ATU_VIEWPORT);
+-	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
++	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
+ 	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+-	dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
+-	dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
+-	dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
+-			  PCIE_ATU_LIMIT);
+-	dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
+-	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
+-			  PCIE_ATU_UPPER_TARGET);
+ }
+ 
+ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
+@@ -322,11 +291,9 @@ static int dw_pcie_rd_other_conf(struct
+ 	if (bus->parent->number == pp->root_bus_nr) {
+ 		dw_pcie_prog_viewport_cfg0(pp, busdev);
+ 		ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
+-		dw_pcie_prog_viewport_mem_outbound(pp);
+ 	} else {
+ 		dw_pcie_prog_viewport_cfg1(pp, busdev);
+ 		ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
+-		dw_pcie_prog_viewport_io_outbound(pp);
+ 	}
+ 
+ 	return ret;
+@@ -345,11 +312,9 @@ static int dw_pcie_wr_other_conf(struct
+ 	if (bus->parent->number == pp->root_bus_nr) {
+ 		dw_pcie_prog_viewport_cfg0(pp, busdev);
+ 		ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
+-		dw_pcie_prog_viewport_mem_outbound(pp);
+ 	} else {
+ 		dw_pcie_prog_viewport_cfg1(pp, busdev);
+ 		ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
+-		dw_pcie_prog_viewport_io_outbound(pp);
+ 	}
+ 
+ 	return ret;