generic: mtk_eth_soc: switch to external PCS driver

Backport patch to make use of the new PCS driver in mtk_eth_soc.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

6 files changed, 532 insertions, 20 deletions

diff --git a/target/linux/generic/backport-5.15/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch b/target/linux/generic/backport-5.15/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
new file mode 100644
index 0000000000..1eca7dfeaf
--- /dev/null
+++ b/target/linux/generic/backport-5.15/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
@@ -0,0 +1,512 @@
+From 2a3ec7ae313310c1092e4256208cc04d1958e469 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 19 Mar 2023 12:58:02 +0000
+Subject: [PATCH] net: ethernet: mtk_eth_soc: switch to external PCS driver
+
+Now that we got a PCS driver, use it and remove the now redundant
+PCS code and it's header macros from the Ethernet driver.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/Kconfig       |   2 +
+ drivers/net/ethernet/mediatek/Makefile      |   2 +-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |  61 +++++-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  93 +--------
+ drivers/net/ethernet/mediatek/mtk_sgmii.c   | 217 --------------------
+ 5 files changed, 56 insertions(+), 319 deletions(-)
+ delete mode 100644 drivers/net/ethernet/mediatek/mtk_sgmii.c
+
+--- a/drivers/net/ethernet/mediatek/Kconfig
++++ b/drivers/net/ethernet/mediatek/Kconfig
+@@ -18,6 +18,8 @@ config NET_MEDIATEK_SOC
+ 	select DIMLIB
+ 	select PAGE_POOL
+ 	select PAGE_POOL_STATS
++	select PCS_MTK_LYNXI
++	select REGMAP_MMIO
+ 	help
+ 	  This driver supports the gigabit ethernet MACs in the
+ 	  MediaTek SoC family.
+--- a/drivers/net/ethernet/mediatek/Makefile
++++ b/drivers/net/ethernet/mediatek/Makefile
+@@ -4,7 +4,7 @@
+ #
+ 
+ obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
+-mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
++mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
+ mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
+ ifdef CONFIG_DEBUG_FS
+ mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -20,6 +20,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/pinctrl/devinfo.h>
+ #include <linux/phylink.h>
++#include <linux/pcs/pcs-mtk-lynxi.h>
+ #include <linux/jhash.h>
+ #include <linux/bitfield.h>
+ #include <net/dsa.h>
+@@ -357,7 +358,7 @@ static struct phylink_pcs *mtk_mac_selec
+ 		sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
+ 		       0 : mac->id;
+ 
+-		return mtk_sgmii_select_pcs(eth->sgmii, sid);
++		return eth->sgmii_pcs[sid];
+ 	}
+ 
+ 	return NULL;
+@@ -3979,8 +3980,17 @@ static int mtk_unreg_dev(struct mtk_eth
+ 	return 0;
+ }
+ 
++static void mtk_sgmii_destroy(struct mtk_eth *eth)
++{
++	int i;
++
++	for (i = 0; i < MTK_MAX_DEVS; i++)
++		mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]);
++}
++
+ static int mtk_cleanup(struct mtk_eth *eth)
+ {
++	mtk_sgmii_destroy(eth);
+ 	mtk_unreg_dev(eth);
+ 	mtk_free_dev(eth);
+ 	cancel_work_sync(&eth->pending_work);
+@@ -4410,6 +4420,36 @@ void mtk_eth_set_dma_device(struct mtk_e
+ 	rtnl_unlock();
+ }
+ 
++static int mtk_sgmii_init(struct mtk_eth *eth)
++{
++	struct device_node *np;
++	struct regmap *regmap;
++	u32 flags;
++	int i;
++
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i);
++		if (!np)
++			break;
++
++		regmap = syscon_node_to_regmap(np);
++		flags = 0;
++		if (of_property_read_bool(np, "mediatek,pnswap"))
++			flags |= MTK_SGMII_FLAG_PN_SWAP;
++
++		of_node_put(np);
++
++		if (IS_ERR(regmap))
++			return PTR_ERR(regmap);
++
++		eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap,
++							 eth->soc->ana_rgc3,
++							 flags);
++	}
++
++	return 0;
++}
++
+ static int mtk_probe(struct platform_device *pdev)
+ {
+ 	struct resource *res = NULL;
+@@ -4473,13 +4513,7 @@ static int mtk_probe(struct platform_dev
+ 	}
+ 
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
+-		eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
+-					  GFP_KERNEL);
+-		if (!eth->sgmii)
+-			return -ENOMEM;
+-
+-		err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
+-				     eth->soc->ana_rgc3);
++		err = mtk_sgmii_init(eth);
+ 
+ 		if (err)
+ 			return err;
+@@ -4490,14 +4524,17 @@ static int mtk_probe(struct platform_dev
+ 							    "mediatek,pctl");
+ 		if (IS_ERR(eth->pctl)) {
+ 			dev_err(&pdev->dev, "no pctl regmap found\n");
+-			return PTR_ERR(eth->pctl);
++			err = PTR_ERR(eth->pctl);
++			goto err_destroy_sgmii;
+ 		}
+ 	}
+ 
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
+ 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-		if (!res)
+-			return -EINVAL;
++		if (!res) {
++			err = -EINVAL;
++			goto err_destroy_sgmii;
++		}
+ 	}
+ 
+ 	if (eth->soc->offload_version) {
+@@ -4657,6 +4694,8 @@ err_deinit_hw:
+ 	mtk_hw_deinit(eth);
+ err_wed_exit:
+ 	mtk_wed_exit();
++err_destroy_sgmii:
++	mtk_sgmii_destroy(eth);
+ 
+ 	return err;
+ }
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -507,65 +507,6 @@
+ #define ETHSYS_DMA_AG_MAP_QDMA	BIT(1)
+ #define ETHSYS_DMA_AG_MAP_PPE	BIT(2)
+ 
+-/* SGMII subsystem config registers */
+-/* BMCR (low 16) BMSR (high 16) */
+-#define SGMSYS_PCS_CONTROL_1	0x0
+-#define SGMII_BMCR		GENMASK(15, 0)
+-#define SGMII_BMSR		GENMASK(31, 16)
+-#define SGMII_AN_RESTART	BIT(9)
+-#define SGMII_ISOLATE		BIT(10)
+-#define SGMII_AN_ENABLE		BIT(12)
+-#define SGMII_LINK_STATYS	BIT(18)
+-#define SGMII_AN_ABILITY	BIT(19)
+-#define SGMII_AN_COMPLETE	BIT(21)
+-#define SGMII_PCS_FAULT		BIT(23)
+-#define SGMII_AN_EXPANSION_CLR	BIT(30)
+-
+-#define SGMSYS_PCS_ADVERTISE	0x8
+-#define SGMII_ADVERTISE		GENMASK(15, 0)
+-#define SGMII_LPA		GENMASK(31, 16)
+-
+-/* Register to programmable link timer, the unit in 2 * 8ns */
+-#define SGMSYS_PCS_LINK_TIMER	0x18
+-#define SGMII_LINK_TIMER_MASK	GENMASK(19, 0)
+-#define SGMII_LINK_TIMER_DEFAULT	(0x186a0 & SGMII_LINK_TIMER_MASK)
+-
+-/* Register to control remote fault */
+-#define SGMSYS_SGMII_MODE		0x20
+-#define SGMII_IF_MODE_SGMII		BIT(0)
+-#define SGMII_SPEED_DUPLEX_AN		BIT(1)
+-#define SGMII_SPEED_MASK		GENMASK(3, 2)
+-#define SGMII_SPEED_10			FIELD_PREP(SGMII_SPEED_MASK, 0)
+-#define SGMII_SPEED_100			FIELD_PREP(SGMII_SPEED_MASK, 1)
+-#define SGMII_SPEED_1000		FIELD_PREP(SGMII_SPEED_MASK, 2)
+-#define SGMII_DUPLEX_HALF		BIT(4)
+-#define SGMII_IF_MODE_BIT5		BIT(5)
+-#define SGMII_REMOTE_FAULT_DIS		BIT(8)
+-#define SGMII_CODE_SYNC_SET_VAL		BIT(9)
+-#define SGMII_CODE_SYNC_SET_EN		BIT(10)
+-#define SGMII_SEND_AN_ERROR_EN		BIT(11)
+-#define SGMII_IF_MODE_MASK		GENMASK(5, 1)
+-
+-/* Register to reset SGMII design */
+-#define SGMII_RESERVED_0	0x34
+-#define SGMII_SW_RESET		BIT(0)
+-
+-/* Register to set SGMII speed, ANA RG_ Control Signals III*/
+-#define SGMSYS_ANA_RG_CS3	0x2028
+-#define RG_PHY_SPEED_MASK	(BIT(2) | BIT(3))
+-#define RG_PHY_SPEED_1_25G	0x0
+-#define RG_PHY_SPEED_3_125G	BIT(2)
+-
+-/* Register to power up QPHY */
+-#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
+-#define	SGMII_PHYA_PWD		BIT(4)
+-
+-/* Register to QPHY wrapper control */
+-#define SGMSYS_QPHY_WRAP_CTRL	0xec
+-#define SGMII_PN_SWAP_MASK	GENMASK(1, 0)
+-#define SGMII_PN_SWAP_TX_RX	(BIT(0) | BIT(1))
+-#define MTK_SGMII_FLAG_PN_SWAP	BIT(0)
+-
+ /* Infrasys subsystem config registers */
+ #define INFRA_MISC2            0x70c
+ #define CO_QPHY_SEL            BIT(0)
+@@ -1105,31 +1046,6 @@ struct mtk_soc_data {
+ /* currently no SoC has more than 2 macs */
+ #define MTK_MAX_DEVS			2
+ 
+-/* struct mtk_pcs -    This structure holds each sgmii regmap and associated
+- *                     data
+- * @regmap:            The register map pointing at the range used to setup
+- *                     SGMII modes
+- * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
+- * @interface:         Currently configured interface mode
+- * @pcs:               Phylink PCS structure
+- * @flags:             Flags indicating hardware properties
+- */
+-struct mtk_pcs {
+-	struct regmap	*regmap;
+-	u32             ana_rgc3;
+-	phy_interface_t	interface;
+-	struct phylink_pcs pcs;
+-	u32		flags;
+-};
+-
+-/* struct mtk_sgmii -  This is the structure holding sgmii regmap and its
+- *                     characteristics
+- * @pcs                Array of individual PCS structures
+- */
+-struct mtk_sgmii {
+-	struct mtk_pcs	pcs[MTK_MAX_DEVS];
+-};
+-
+ /* struct mtk_eth -	This is the main datasructure for holding the state
+  *			of the driver
+  * @dev:		The device pointer
+@@ -1149,6 +1065,7 @@ struct mtk_sgmii {
+  *			MII modes
+  * @infra:              The register map pointing at the range used to setup
+  *                      SGMII and GePHY path
++ * @sgmii_pcs:		Pointers to mtk-pcs-lynxi phylink_pcs instances
+  * @pctl:		The register map pointing at the range used to setup
+  *			GMAC port drive/slew values
+  * @dma_refcnt:		track how many netdevs are using the DMA engine
+@@ -1189,8 +1106,8 @@ struct mtk_eth {
+ 	u32				msg_enable;
+ 	unsigned long			sysclk;
+ 	struct regmap			*ethsys;
+-	struct regmap                   *infra;
+-	struct mtk_sgmii                *sgmii;
++	struct regmap			*infra;
++	struct phylink_pcs		*sgmii_pcs[MTK_MAX_DEVS];
+ 	struct regmap			*pctl;
+ 	bool				hwlro;
+ 	refcount_t			dma_refcnt;
+@@ -1352,10 +1269,6 @@ void mtk_stats_update_mac(struct mtk_mac
+ void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
+ u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
+ 
+-struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id);
+-int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
+-		   u32 ana_rgc3);
+-
+ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
+ int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
+ int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
+--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
++++ /dev/null
+@@ -1,217 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0
+-// Copyright (c) 2018-2019 MediaTek Inc.
+-
+-/* A library for MediaTek SGMII circuit
+- *
+- * Author: Sean Wang <sean.wang@mediatek.com>
+- *
+- */
+-
+-#include <linux/mfd/syscon.h>
+-#include <linux/of.h>
+-#include <linux/phylink.h>
+-#include <linux/regmap.h>
+-
+-#include "mtk_eth_soc.h"
+-
+-static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs)
+-{
+-	return container_of(pcs, struct mtk_pcs, pcs);
+-}
+-
+-static void mtk_pcs_get_state(struct phylink_pcs *pcs,
+-			      struct phylink_link_state *state)
+-{
+-	struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
+-	unsigned int bm, adv;
+-
+-	/* Read the BMSR and LPA */
+-	regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm);
+-	regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
+-
+-	phylink_mii_c22_pcs_decode_state(state, FIELD_GET(SGMII_BMSR, bm),
+-					 FIELD_GET(SGMII_LPA, adv));
+-}
+-
+-static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
+-			  phy_interface_t interface,
+-			  const unsigned long *advertising,
+-			  bool permit_pause_to_mac)
+-{
+-	bool mode_changed = false, changed, use_an;
+-	struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
+-	unsigned int rgc3, sgm_mode, bmcr;
+-	int advertise, link_timer;
+-
+-	advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+-							     advertising);
+-	if (advertise < 0)
+-		return advertise;
+-
+-	/* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and
+-	 * we assume that fixes it's speed at bitrate = line rate (in
+-	 * other words, 1000Mbps or 2500Mbps).
+-	 */
+-	if (interface == PHY_INTERFACE_MODE_SGMII) {
+-		sgm_mode = SGMII_IF_MODE_SGMII;
+-		if (phylink_autoneg_inband(mode)) {
+-			sgm_mode |= SGMII_REMOTE_FAULT_DIS |
+-				    SGMII_SPEED_DUPLEX_AN;
+-			use_an = true;
+-		} else {
+-			use_an = false;
+-		}
+-	} else if (phylink_autoneg_inband(mode)) {
+-		/* 1000base-X or 2500base-X autoneg */
+-		sgm_mode = SGMII_REMOTE_FAULT_DIS;
+-		use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+-					   advertising);
+-	} else {
+-		/* 1000base-X or 2500base-X without autoneg */
+-		sgm_mode = 0;
+-		use_an = false;
+-	}
+-
+-	if (use_an) {
+-		bmcr = SGMII_AN_ENABLE;
+-	} else {
+-		bmcr = 0;
+-	}
+-
+-	if (mpcs->interface != interface) {
+-		link_timer = phylink_get_link_timer_ns(interface);
+-		if (link_timer < 0)
+-			return link_timer;
+-
+-		/* PHYA power down */
+-		regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
+-				   SGMII_PHYA_PWD, SGMII_PHYA_PWD);
+-
+-		if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
+-			regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
+-					   SGMII_PN_SWAP_MASK,
+-					   SGMII_PN_SWAP_TX_RX);
+-
+-		/* Reset SGMII PCS state */
+-		regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
+-				   SGMII_SW_RESET, SGMII_SW_RESET);
+-
+-		if (interface == PHY_INTERFACE_MODE_2500BASEX)
+-			rgc3 = RG_PHY_SPEED_3_125G;
+-		else
+-			rgc3 = 0;
+-
+-		/* Configure the underlying interface speed */
+-		regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
+-				   RG_PHY_SPEED_3_125G, rgc3);
+-
+-		/* Setup the link timer */
+-		regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8);
+-
+-		mpcs->interface = interface;
+-		mode_changed = true;
+-	}
+-
+-	/* Update the advertisement, noting whether it has changed */
+-	regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
+-				 SGMII_ADVERTISE, advertise, &changed);
+-
+-	/* Update the sgmsys mode register */
+-	regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
+-			   SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN |
+-			   SGMII_IF_MODE_SGMII, sgm_mode);
+-
+-	/* Update the BMCR */
+-	regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
+-			   SGMII_AN_ENABLE, bmcr);
+-
+-	/* Release PHYA power down state
+-	 * Only removing bit SGMII_PHYA_PWD isn't enough.
+-	 * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
+-	 * prevents SGMII from working. The SGMII still shows link but no traffic
+-	 * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
+-	 * taken from a good working state of the SGMII interface.
+-	 * Unknown how much the QPHY needs but it is racy without a sleep.
+-	 * Tested on mt7622 & mt7986.
+-	 */
+-	usleep_range(50, 100);
+-	regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
+-
+-	return changed || mode_changed;
+-}
+-
+-static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
+-{
+-	struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
+-
+-	regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
+-			   SGMII_AN_RESTART, SGMII_AN_RESTART);
+-}
+-
+-static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
+-			    phy_interface_t interface, int speed, int duplex)
+-{
+-	struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
+-	unsigned int sgm_mode;
+-
+-	if (!phylink_autoneg_inband(mode)) {
+-		/* Force the speed and duplex setting */
+-		if (speed == SPEED_10)
+-			sgm_mode = SGMII_SPEED_10;
+-		else if (speed == SPEED_100)
+-			sgm_mode = SGMII_SPEED_100;
+-		else
+-			sgm_mode = SGMII_SPEED_1000;
+-
+-		if (duplex != DUPLEX_FULL)
+-			sgm_mode |= SGMII_DUPLEX_HALF;
+-
+-		regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
+-				   SGMII_DUPLEX_HALF | SGMII_SPEED_MASK,
+-				   sgm_mode);
+-	}
+-}
+-
+-static const struct phylink_pcs_ops mtk_pcs_ops = {
+-	.pcs_get_state = mtk_pcs_get_state,
+-	.pcs_config = mtk_pcs_config,
+-	.pcs_an_restart = mtk_pcs_restart_an,
+-	.pcs_link_up = mtk_pcs_link_up,
+-};
+-
+-int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
+-{
+-	struct device_node *np;
+-	int i;
+-
+-	for (i = 0; i < MTK_MAX_DEVS; i++) {
+-		np = of_parse_phandle(r, "mediatek,sgmiisys", i);
+-		if (!np)
+-			break;
+-
+-		ss->pcs[i].ana_rgc3 = ana_rgc3;
+-		ss->pcs[i].regmap = syscon_node_to_regmap(np);
+-
+-		ss->pcs[i].flags = 0;
+-		if (of_property_read_bool(np, "mediatek,pnswap"))
+-			ss->pcs[i].flags |= MTK_SGMII_FLAG_PN_SWAP;
+-
+-		of_node_put(np);
+-		if (IS_ERR(ss->pcs[i].regmap))
+-			return PTR_ERR(ss->pcs[i].regmap);
+-
+-		ss->pcs[i].pcs.ops = &mtk_pcs_ops;
+-		ss->pcs[i].pcs.poll = true;
+-		ss->pcs[i].interface = PHY_INTERFACE_MODE_NA;
+-	}
+-
+-	return 0;
+-}
+-
+-struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id)
+-{
+-	if (!ss->pcs[id].regmap)
+-		return NULL;
+-
+-	return &ss->pcs[id].pcs;
+-}
diff --git a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
index 75393bcce7..5dcbc6c46a 100644
--- a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
+++ b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
@@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2993,8 +2993,8 @@ static irqreturn_t mtk_handle_irq_rx(int
+@@ -2994,8 +2994,8 @@ static irqreturn_t mtk_handle_irq_rx(int
  
  	eth->rx_events++;
  	if (likely(napi_schedule_prep(&eth->rx_napi))) {
@@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}
  
  	return IRQ_HANDLED;
-@@ -3006,8 +3006,8 @@ static irqreturn_t mtk_handle_irq_tx(int
+@@ -3007,8 +3007,8 @@ static irqreturn_t mtk_handle_irq_tx(int
  
  	eth->tx_events++;
  	if (likely(napi_schedule_prep(&eth->tx_napi))) {
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}
  
  	return IRQ_HANDLED;
-@@ -4638,6 +4638,8 @@ static int mtk_probe(struct platform_dev
+@@ -4675,6 +4675,8 @@ static int mtk_probe(struct platform_dev
  	 * for NAPI to work
  	 */
  	init_dummy_netdev(&eth->dummy_dev);
diff --git a/target/linux/generic/pending-5.15/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch b/target/linux/generic/pending-5.15/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch
index c6572214fb..c7e1d3f6f0 100644
--- a/target/linux/generic/pending-5.15/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch
+++ b/target/linux/generic/pending-5.15/731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch
@@ -53,7 +53,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4607,8 +4607,8 @@ static int mtk_probe(struct platform_dev
+@@ -4644,8 +4644,8 @@ static int mtk_probe(struct platform_dev
  		for (i = 0; i < num_ppe; i++) {
  			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
  
@@ -64,7 +64,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  			if (!eth->ppe[i]) {
  				err = -ENOMEM;
  				goto err_free_dev;
-@@ -4733,6 +4733,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4772,6 +4772,7 @@ static const struct mtk_soc_data mt7622_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 2,
@@ -72,7 +72,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
-@@ -4770,6 +4771,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4809,6 +4810,7 @@ static const struct mtk_soc_data mt7629_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7629_CLKS_BITMAP,
  	.required_pctl = false,
@@ -80,7 +80,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4790,6 +4792,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4829,6 +4831,7 @@ static const struct mtk_soc_data mt7981_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
@@ -90,7 +90,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1044,6 +1044,8 @@ struct mtk_reg_map {
+@@ -1014,6 +1014,8 @@ struct mtk_reg_map {
   *				the extra setup for those pins used by GMAC.
   * @hash_offset			Flow table hash offset.
   * @foe_entry_size		Foe table entry size.
@@ -99,7 +99,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
   * @txd_size			Tx DMA descriptor size.
   * @rxd_size			Rx DMA descriptor size.
   * @rx_irq_done_mask		Rx irq done register mask.
-@@ -1061,6 +1063,7 @@ struct mtk_soc_data {
+@@ -1031,6 +1033,7 @@ struct mtk_soc_data {
  	u8		hash_offset;
  	u16		foe_entry_size;
  	netdev_features_t hw_features;
diff --git a/target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch b/target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
index 84afb3f46a..b5e118f9fa 100644
--- a/target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
+++ b/target/linux/generic/pending-5.15/732-00-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
@@ -17,7 +17,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1851,9 +1851,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1852,9 +1852,7 @@ static int mtk_poll_rx(struct napi_struc
  
  	while (done < budget) {
  		unsigned int pktlen, *rxdcsum;
@@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		dma_addr_t dma_addr;
  		u32 hash, reason;
  		int mac = 0;
-@@ -1988,36 +1986,21 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1989,36 +1987,21 @@ static int mtk_poll_rx(struct napi_struc
  			skb_checksum_none_assert(skb);
  		skb->protocol = eth_type_trans(skb, netdev);
  
@@ -70,7 +70,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		skb_record_rx_queue(skb, 0);
  		napi_gro_receive(napi, skb);
  
-@@ -2832,29 +2815,11 @@ static netdev_features_t mtk_fix_feature
+@@ -2833,29 +2816,11 @@ static netdev_features_t mtk_fix_feature
  
  static int mtk_set_features(struct net_device *dev, netdev_features_t features)
  {
@@ -100,7 +100,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3168,30 +3133,6 @@ static int mtk_open(struct net_device *d
+@@ -3169,30 +3134,6 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -131,7 +131,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
  	if (err) {
  		netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
-@@ -3232,6 +3173,35 @@ static int mtk_open(struct net_device *d
+@@ -3233,6 +3174,35 @@ static int mtk_open(struct net_device *d
  	phylink_start(mac->phylink);
  	netif_tx_start_all_queues(dev);
  
@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3716,10 +3686,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3717,10 +3687,9 @@ static int mtk_hw_init(struct mtk_eth *e
  	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
  		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
@@ -180,7 +180,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/* set interrupt delays based on current Net DIM sample */
  	mtk_dim_rx(&eth->rx_dim.work);
-@@ -4357,7 +4326,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4367,7 +4336,7 @@ static int mtk_add_mac(struct mtk_eth *e
  		eth->netdev[id]->hw_features |= NETIF_F_LRO;
  
  	eth->netdev[id]->vlan_features = eth->soc->hw_features &
diff --git a/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
index 0ed8c695e9..72bad79c13 100644
--- a/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
+++ b/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
@@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1424,12 +1424,28 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1425,12 +1425,28 @@ static void mtk_wake_queue(struct mtk_et
  	}
  }
  
@@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	bool gso = false;
  	int tx_num;
  
-@@ -1451,6 +1467,18 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1452,6 +1468,18 @@ static netdev_tx_t mtk_start_xmit(struct
  		return NETDEV_TX_BUSY;
  	}
  
@@ -64,7 +64,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* TSO: fill MSS info in tcp checksum field */
  	if (skb_is_gso(skb)) {
  		if (skb_cow_head(skb, 0)) {
-@@ -1466,8 +1494,14 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1467,8 +1495,14 @@ static netdev_tx_t mtk_start_xmit(struct
  		}
  	}
  
diff --git a/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch b/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch
index f6919dc19e..4f765c5c14 100644
--- a/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch
+++ b/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch
@@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1364,6 +1364,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk
+@@ -1277,6 +1277,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk
  int mtk_eth_offload_init(struct mtk_eth *eth);
  int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
  		     void *type_data);