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authorRafał Miłecki <zajec5@gmail.com>2015-02-11 09:14:48 +0000
committerRafał Miłecki <zajec5@gmail.com>2015-02-11 09:14:48 +0000
commitd417d58ff7d9f129dc0b258ccf70c62d4a6214bf (patch)
tree18d2b2c239189f7624ddd6d7d4db6f2c0ec1182e /target/linux/generic
parent3ae30df7db14be3b76f05058683c1093f2ddcaa3 (diff)
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kernel: 3.18: complete backport of some bcma patch
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> SVN-Revision: 44384
Diffstat (limited to 'target/linux/generic')
-rw-r--r--target/linux/generic/patches-3.18/025-bcma_backport.patch37
1 files changed, 37 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.18/025-bcma_backport.patch b/target/linux/generic/patches-3.18/025-bcma_backport.patch
index 07ceb037b7..ca24e86133 100644
--- a/target/linux/generic/patches-3.18/025-bcma_backport.patch
+++ b/target/linux/generic/patches-3.18/025-bcma_backport.patch
@@ -247,3 +247,40 @@
{
return 0;
}
+--- a/Documentation/devicetree/bindings/bus/bcma.txt
++++ b/Documentation/devicetree/bindings/bus/bcma.txt
+@@ -8,6 +8,11 @@ Required properties:
+
+ The cores on the AXI bus are automatically detected by bcma with the
+ memory ranges they are using and they get registered afterwards.
++Automatic detection of the IRQ number is not working on
++BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
++them manually through device tree. Use an interrupt-map to specify the
++IRQ used by the devices on the bus. The first address is just an index,
++because we do not have any special register.
+
+ The top-level axi bus may contain children representing attached cores
+ (devices). This is needed since some hardware details can't be auto
+@@ -22,6 +27,22 @@ Example:
+ ranges = <0x00000000 0x18000000 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0x000fffff 0xffff>;
++ interrupt-map =
++ /* Ethernet Controller 0 */
++ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
++
++ /* Ethernet Controller 1 */
++ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++
++ /* PCIe Controller 0 */
++ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
++ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+
+ chipcommon {
+ reg = <0x00000000 0x1000>;