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| author | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2019-09-11 12:22:42 +0200 |
|---|---|---|
| committer | Koen Vandeputte <koen.vandeputte@ncentric.com> | 2019-09-13 16:40:29 +0200 |
| commit | 00d48bcac08afc5a586c074894f96d9237fbe823 (patch) | |
| tree | 6ab7a0b48a9ae16234d544ac31c42f1c33c8b01d /target/linux/generic/pending-4.14/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch | |
| parent | 78c3a18a1e7c57fbc529f0feab60167d53edec31 (diff) | |
| download | upstream-00d48bcac08afc5a586c074894f96d9237fbe823.tar.gz upstream-00d48bcac08afc5a586c074894f96d9237fbe823.tar.bz2 upstream-00d48bcac08afc5a586c074894f96d9237fbe823.zip | |
ar71xx: Fix potentially missed IRQ handling during dispatch
If both interrupts are set in the current implementation
only the 1st will be handled and the 2nd will be skipped
due to the "if else" condition.
Fix this by using the same approach as done for QCA955x
just below it.
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Diffstat (limited to 'target/linux/generic/pending-4.14/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch')
0 files changed, 0 insertions, 0 deletions