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| author | Felix Fietkau <nbd@nbd.name> | 2017-01-27 14:32:10 +0100 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2017-02-04 20:28:14 +0100 |
| commit | f791fb4af45032a653ba7c850f4564923871cb16 (patch) | |
| tree | c1fc4e564c8e27faad582e5b55a9ce91816a241c /target/linux/generic/patches-4.9/162-mtd-spi-nor-add-support-for-ESMT_f25l32qa-and-ESMT_f.patch | |
| parent | 7d00cfe9bb693e376ac9d035e13f8ce8a5ff572c (diff) | |
| download | upstream-f791fb4af45032a653ba7c850f4564923871cb16.tar.gz upstream-f791fb4af45032a653ba7c850f4564923871cb16.tar.bz2 upstream-f791fb4af45032a653ba7c850f4564923871cb16.zip | |
kernel: add linux 4.9 support
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Tim Harvey <tharvey@gateworks.com> [fixes]
Diffstat (limited to 'target/linux/generic/patches-4.9/162-mtd-spi-nor-add-support-for-ESMT_f25l32qa-and-ESMT_f.patch')
| -rw-r--r-- | target/linux/generic/patches-4.9/162-mtd-spi-nor-add-support-for-ESMT_f25l32qa-and-ESMT_f.patch | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/generic/patches-4.9/162-mtd-spi-nor-add-support-for-ESMT_f25l32qa-and-ESMT_f.patch b/target/linux/generic/patches-4.9/162-mtd-spi-nor-add-support-for-ESMT_f25l32qa-and-ESMT_f.patch new file mode 100644 index 0000000000..8f48ab1370 --- /dev/null +++ b/target/linux/generic/patches-4.9/162-mtd-spi-nor-add-support-for-ESMT_f25l32qa-and-ESMT_f.patch @@ -0,0 +1,21 @@ +From: "L. D. Pinney" <ldpinney@gmail.com> +Date: Thu, 25 Aug 2016 13:07:56 -0500 +Subject: [PATCH] mtd: spi-nor: add support for ESMT_f25l32qa and ESMT_f25l64qa + +Add Support for the ESMT_F25L32QA and ESMT_F25L64QA +These are 4MB and 8MB SPI NOR Chips from Elite Semiconductor Memory Technology + +Signed-off-by: L. D. Pinney <ldpinney@gmail.com> +--- + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -821,6 +821,8 @@ static const struct flash_info spi_nor_i + + /* ESMT */ + { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) }, ++ { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K) }, ++ { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K) }, + + /* Everspin */ + { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |