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authorRafał Miłecki <rafal@milecki.pl>2017-01-28 17:33:56 +0100
committerRafał Miłecki <rafal@milecki.pl>2017-01-28 17:34:17 +0100
commit2ee7bc0a5e14981a7f753bce1d5ea61e2c223799 (patch)
tree4edb9c02a25ed65da0c67dbd3f6a437b57bbabfb /target/linux/generic/patches-4.4/078-0003-net-phy-cherry-pick-Broadcom-drivers-updates-from-v4.patch
parentf5ab082243f9822544204fc713c6bd4dab14a3a8 (diff)
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kernel: backport support for BCM54612E PHY
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Diffstat (limited to 'target/linux/generic/patches-4.4/078-0003-net-phy-cherry-pick-Broadcom-drivers-updates-from-v4.patch')
-rw-r--r--target/linux/generic/patches-4.4/078-0003-net-phy-cherry-pick-Broadcom-drivers-updates-from-v4.patch103
1 files changed, 103 insertions, 0 deletions
diff --git a/target/linux/generic/patches-4.4/078-0003-net-phy-cherry-pick-Broadcom-drivers-updates-from-v4.patch b/target/linux/generic/patches-4.4/078-0003-net-phy-cherry-pick-Broadcom-drivers-updates-from-v4.patch
new file mode 100644
index 0000000000..6f6536bb1f
--- /dev/null
+++ b/target/linux/generic/patches-4.4/078-0003-net-phy-cherry-pick-Broadcom-drivers-updates-from-v4.patch
@@ -0,0 +1,103 @@
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Subject: [PATCH 1/2] net: phy: cherry-pick Broadcom drivers updates from
+ v4.10-rc1
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+
+--- a/drivers/net/phy/broadcom.c
++++ b/drivers/net/phy/broadcom.c
+@@ -337,6 +337,41 @@ static int bcm5481_config_aneg(struct ph
+ return ret;
+ }
+
++static int bcm54612e_config_aneg(struct phy_device *phydev)
++{
++ int ret;
++
++ /* First, auto-negotiate. */
++ ret = genphy_config_aneg(phydev);
++
++ /* Clear TX internal delay unless requested. */
++ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
++ (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
++ /* Disable TXD to GTXCLK clock delay (default set) */
++ /* Bit 9 is the only field in shadow register 00011 */
++ bcm_phy_write_shadow(phydev, 0x03, 0);
++ }
++
++ /* Clear RX internal delay unless requested. */
++ if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
++ (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
++ u16 reg;
++
++ /* Errata: reads require filling in the write selector field */
++ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
++ MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
++ reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
++ /* Disable RXD to RXC delay (default set) */
++ reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
++ /* Clear shadow selector field */
++ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
++ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
++ MII_BCM54XX_AUXCTL_MISC_WREN | reg);
++ }
++
++ return ret;
++}
++
+ static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
+ {
+ int val;
+@@ -488,6 +523,19 @@ static struct phy_driver broadcom_driver
+ .config_intr = bcm_phy_config_intr,
+ .driver = { .owner = THIS_MODULE },
+ }, {
++ .phy_id = PHY_ID_BCM54612E,
++ .phy_id_mask = 0xfffffff0,
++ .name = "Broadcom BCM54612E",
++ .features = PHY_GBIT_FEATURES |
++ SUPPORTED_Pause | SUPPORTED_Asym_Pause,
++ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
++ .config_init = bcm54xx_config_init,
++ .config_aneg = bcm54612e_config_aneg,
++ .read_status = genphy_read_status,
++ .ack_interrupt = bcm_phy_ack_intr,
++ .config_intr = bcm_phy_config_intr,
++ .driver = { .owner = THIS_MODULE },
++}, {
+ .phy_id = PHY_ID_BCM54616S,
+ .phy_id_mask = 0xfffffff0,
+ .name = "Broadcom BCM54616S",
+@@ -612,6 +660,7 @@ static struct mdio_device_id __maybe_unu
+ { PHY_ID_BCM5411, 0xfffffff0 },
+ { PHY_ID_BCM5421, 0xfffffff0 },
+ { PHY_ID_BCM5461, 0xfffffff0 },
++ { PHY_ID_BCM54612E, 0xfffffff0 },
+ { PHY_ID_BCM54616S, 0xfffffff0 },
+ { PHY_ID_BCM5464, 0xfffffff0 },
+ { PHY_ID_BCM5481, 0xfffffff0 },
+--- a/include/linux/brcmphy.h
++++ b/include/linux/brcmphy.h
+@@ -18,6 +18,7 @@
+ #define PHY_ID_BCM5421 0x002060e0
+ #define PHY_ID_BCM5464 0x002060b0
+ #define PHY_ID_BCM5461 0x002060c0
++#define PHY_ID_BCM54612E 0x03625e60
+ #define PHY_ID_BCM54616S 0x03625d10
+ #define PHY_ID_BCM57780 0x03625d90
+
+@@ -102,11 +103,12 @@
+ #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
+
+ #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
++#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
+ #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
+ #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
+ #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
+
+-#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
++#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
+
+ /*
+ * Broadcom LED source encodings. These are used in BCM5461, BCM5481,