kernel: update bcma and ssb to version from wireless-testing/master tag master-2013-07-18

This should fix some build problems in b43 with kernel 3.3.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

SVN-Revision: 37432

1 files changed, 1384 insertions, 91 deletions

diff --git a/target/linux/generic/patches-3.6/020-ssb_update.patch b/target/linux/generic/patches-3.6/020-ssb_update.patch
index 6f9c8342d0..2d134583cf 100644
--- a/target/linux/generic/patches-3.6/020-ssb_update.patch
+++ b/target/linux/generic/patches-3.6/020-ssb_update.patch
@@ -30,7 +30,7 @@
  					    ARRAY_SIZE(wgt634u_devices));
 --- a/drivers/ssb/Kconfig
 +++ b/drivers/ssb/Kconfig
-@@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS
+@@ -136,10 +136,15 @@ config SSB_DRIVER_MIPS
  
  	  If unsure, say N
  
@@ -42,6 +42,11 @@
  # Assumption: We are on embedded, if we compile the MIPS core.
  config SSB_EMBEDDED
  	bool
+-	depends on SSB_DRIVER_MIPS
++	depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
+ 	default y
+ 
+ config SSB_DRIVER_EXTIF
 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
  
  	  If unsure, say N
@@ -98,7 +103,7 @@
  
  #include "ssb_private.h"
  
-@@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru
+@@ -280,13 +282,79 @@ static void calc_fast_powerup_delay(stru
  	cc->fast_pwrup_delay = tmp;
  }
  
@@ -174,7 +179,11 @@
 +
  	if (cc->dev->id.revision >= 11)
  		cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
- 	ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
+-	ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
++	ssb_dbg("chipcommon status is 0x%x\n", cc->status);
+ 
+ 	if (cc->dev->id.revision >= 20) {
+ 		chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
  	chipco_powercontrol_init(cc);
  	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
@@ -333,16 +342,62 @@
  				/* Turn off UART clock before switching clocksource. */
 --- a/drivers/ssb/driver_chipcommon_pmu.c
 +++ b/drivers/ssb/driver_chipcommon_pmu.c
-@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
+@@ -110,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s
+ 		return;
+ 	}
+ 
+-	ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
+-		   (crystalfreq / 1000), (crystalfreq % 1000));
++	ssb_info("Programming PLL to %u.%03u MHz\n",
++		 crystalfreq / 1000, crystalfreq % 1000);
+ 
+ 	/* First turn the PLL off. */
+ 	switch (bus->chip_id) {
+@@ -138,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s
+ 	}
+ 	tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
+ 	if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
+-		ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
++		ssb_emerg("Failed to turn the PLL off!\n");
+ 
+ 	/* Set PDIV in PLL control 0. */
+ 	pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
+@@ -249,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s
+ 		return;
+ 	}
+ 
+-	ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
+-		   (crystalfreq / 1000), (crystalfreq % 1000));
++	ssb_info("Programming PLL to %u.%03u MHz\n",
++		 crystalfreq / 1000, crystalfreq % 1000);
+ 
+ 	/* First turn the PLL off. */
+ 	switch (bus->chip_id) {
+@@ -275,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s
+ 	}
+ 	tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
+ 	if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
+-		ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
++		ssb_emerg("Failed to turn the PLL off!\n");
+ 
+ 	/* Set p1div and p2div. */
+ 	pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
+@@ -346,10 +346,11 @@ static void ssb_pmu_pll_init(struct ssb_
  			chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
  		}
  		break;
 +	case 43222:
 +		break;
  	default:
- 		ssb_printk(KERN_ERR PFX
- 			   "ERROR: PLL init unknown for device %04X\n",
-@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
+-		ssb_printk(KERN_ERR PFX
+-			   "ERROR: PLL init unknown for device %04X\n",
+-			   bus->chip_id);
++		ssb_err("ERROR: PLL init unknown for device %04X\n",
++			bus->chip_id);
+ 	}
+ }
+ 
+@@ -434,6 +435,7 @@ static void ssb_pmu_resources_init(struc
  		 min_msk = 0xCBB;
  		 break;
  	case 0x4322:
@@ -350,7 +405,30 @@
  		/* We keep the default settings:
  		 * min_msk = 0xCBB
  		 * max_msk = 0x7FFFF
-@@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
+@@ -469,9 +471,8 @@ static void ssb_pmu_resources_init(struc
+ 		max_msk = 0xFFFFF;
+ 		break;
+ 	default:
+-		ssb_printk(KERN_ERR PFX
+-			   "ERROR: PMU resource config unknown for device %04X\n",
+-			   bus->chip_id);
++		ssb_err("ERROR: PMU resource config unknown for device %04X\n",
++			bus->chip_id);
+ 	}
+ 
+ 	if (updown_tab) {
+@@ -523,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
+ 	pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
+ 	cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
+ 
+-	ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
+-		    cc->pmu.rev, pmucap);
++	ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n",
++		cc->pmu.rev, pmucap);
+ 
+ 	if (cc->pmu.rev == 1)
+ 		chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
+@@ -615,6 +616,32 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
  EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
  EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
  
@@ -374,9 +452,8 @@
 +	case 0x5354:
 +		ssb_pmu_get_alp_clock_clk0(cc);
 +	default:
-+		ssb_printk(KERN_ERR PFX
-+			   "ERROR: PMU alp clock unknown for device %04X\n",
-+			   bus->chip_id);
++		ssb_err("ERROR: PMU alp clock unknown for device %04X\n",
++			bus->chip_id);
 +		return 0;
 +	}
 +}
@@ -384,7 +461,27 @@
  u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
  {
  	struct ssb_bus *bus = cc->dev->bus;
-@@ -645,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_
+@@ -624,9 +651,8 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chi
+ 		/* 5354 chip uses a non programmable PLL of frequency 240MHz */
+ 		return 240000000;
+ 	default:
+-		ssb_printk(KERN_ERR PFX
+-			   "ERROR: PMU cpu clock unknown for device %04X\n",
+-			   bus->chip_id);
++		ssb_err("ERROR: PMU cpu clock unknown for device %04X\n",
++			bus->chip_id);
+ 		return 0;
+ 	}
+ }
+@@ -639,9 +665,52 @@ u32 ssb_pmu_get_controlclock(struct ssb_
+ 	case 0x5354:
+ 		return 120000000;
+ 	default:
+-		ssb_printk(KERN_ERR PFX
+-			   "ERROR: PMU controlclock unknown for device %04X\n",
+-			   bus->chip_id);
++		ssb_err("ERROR: PMU controlclock unknown for device %04X\n",
++			bus->chip_id);
  		return 0;
  	}
  }
@@ -405,8 +502,23 @@
 +		pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
 +		break;
 +	case 43222:
-+		/* TODO: BCM43222 requires updating PLLs too */
-+		return;
++		if (spuravoid == 1) {
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
++		} else {
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
++			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
++		}
++		pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
++		break;
 +	default:
 +		ssb_printk(KERN_ERR PFX
 +			   "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
@@ -419,7 +531,7 @@
 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
 --- /dev/null
 +++ b/drivers/ssb/driver_chipcommon_sflash.c
-@@ -0,0 +1,18 @@
+@@ -0,0 +1,166 @@
 +/*
 + * Sonics Silicon Backplane
 + * ChipCommon serial flash interface
@@ -431,9 +543,157 @@
 +
 +#include "ssb_private.h"
 +
++static struct resource ssb_sflash_resource = {
++	.name	= "ssb_sflash",
++	.start	= SSB_FLASH2,
++	.end	= 0,
++	.flags  = IORESOURCE_MEM | IORESOURCE_READONLY,
++};
++
++struct platform_device ssb_sflash_dev = {
++	.name		= "ssb_sflash",
++	.resource	= &ssb_sflash_resource,
++	.num_resources	= 1,
++};
++
++struct ssb_sflash_tbl_e {
++	char *name;
++	u32 id;
++	u32 blocksize;
++	u16 numblocks;
++};
++
++static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
++	{ "M25P20", 0x11, 0x10000, 4, },
++	{ "M25P40", 0x12, 0x10000, 8, },
++
++	{ "M25P16", 0x14, 0x10000, 32, },
++	{ "M25P32", 0x15, 0x10000, 64, },
++	{ "M25P64", 0x16, 0x10000, 128, },
++	{ "M25FL128", 0x17, 0x10000, 256, },
++	{ 0 },
++};
++
++static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
++	{ "SST25WF512", 1, 0x1000, 16, },
++	{ "SST25VF512", 0x48, 0x1000, 16, },
++	{ "SST25WF010", 2, 0x1000, 32, },
++	{ "SST25VF010", 0x49, 0x1000, 32, },
++	{ "SST25WF020", 3, 0x1000, 64, },
++	{ "SST25VF020", 0x43, 0x1000, 64, },
++	{ "SST25WF040", 4, 0x1000, 128, },
++	{ "SST25VF040", 0x44, 0x1000, 128, },
++	{ "SST25VF040B", 0x8d, 0x1000, 128, },
++	{ "SST25WF080", 5, 0x1000, 256, },
++	{ "SST25VF080B", 0x8e, 0x1000, 256, },
++	{ "SST25VF016", 0x41, 0x1000, 512, },
++	{ "SST25VF032", 0x4a, 0x1000, 1024, },
++	{ "SST25VF064", 0x4b, 0x1000, 2048, },
++	{ 0 },
++};
++
++static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
++	{ "AT45DB011", 0xc, 256, 512, },
++	{ "AT45DB021", 0x14, 256, 1024, },
++	{ "AT45DB041", 0x1c, 256, 2048, },
++	{ "AT45DB081", 0x24, 256, 4096, },
++	{ "AT45DB161", 0x2c, 512, 4096, },
++	{ "AT45DB321", 0x34, 512, 8192, },
++	{ "AT45DB642", 0x3c, 1024, 8192, },
++	{ 0 },
++};
++
++static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
++{
++	int i;
++	chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
++		       SSB_CHIPCO_FLASHCTL_START | opcode);
++	for (i = 0; i < 1000; i++) {
++		if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
++		      SSB_CHIPCO_FLASHCTL_BUSY))
++			return;
++		cpu_relax();
++	}
++	pr_err("SFLASH control command failed (timeout)!\n");
++}
++
 +/* Initialize serial flash access */
 +int ssb_sflash_init(struct ssb_chipcommon *cc)
 +{
++	struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
++	const struct ssb_sflash_tbl_e *e;
++	u32 id, id2;
++
++	switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
++	case SSB_CHIPCO_FLASHT_STSER:
++		ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
++
++		chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
++		ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
++		id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
++
++		chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
++		ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
++		id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
++
++		switch (id) {
++		case 0xbf:
++			for (e = ssb_sflash_sst_tbl; e->name; e++) {
++				if (e->id == id2)
++					break;
++			}
++			break;
++		case 0x13:
++			return -ENOTSUPP;
++		default:
++			for (e = ssb_sflash_st_tbl; e->name; e++) {
++				if (e->id == id)
++					break;
++			}
++			break;
++		}
++		if (!e->name) {
++			pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
++			       id, id2);
++			return -ENOTSUPP;
++		}
++
++		break;
++	case SSB_CHIPCO_FLASHT_ATSER:
++		ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
++		id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
++
++		for (e = ssb_sflash_at_tbl; e->name; e++) {
++			if (e->id == id)
++				break;
++		}
++		if (!e->name) {
++			pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
++			       id);
++			return -ENOTSUPP;
++		}
++
++		break;
++	default:
++		pr_err("Unsupported flash type\n");
++		return -ENOTSUPP;
++	}
++
++	sflash->window = SSB_FLASH2;
++	sflash->blocksize = e->blocksize;
++	sflash->numblocks = e->numblocks;
++	sflash->size = sflash->blocksize * sflash->numblocks;
++	sflash->present = true;
++
++	pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
++		e->name, e->blocksize, e->numblocks);
++
++	/* Prepare platform device, but don't register it yet. It's too early,
++	 * malloc (required by device_private_init) is not available yet. */
++	ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
++					 sflash->size;
++	ssb_sflash_dev.dev.platform_data = sflash;
++
 +	pr_err("Serial flash support is not implemented yet!\n");
 +
 +	return -ENOTSUPP;
@@ -537,7 +797,7 @@
  }
 --- /dev/null
 +++ b/drivers/ssb/driver_gpio.c
-@@ -0,0 +1,176 @@
+@@ -0,0 +1,210 @@
 +/*
 + * Sonics Silicon Backplane
 + * GPIO driver
@@ -614,6 +874,16 @@
 +	ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
 +}
 +
++static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
++{
++	struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++	if (bus->bustype == SSB_BUSTYPE_SSB)
++		return ssb_mips_irq(bus->chipco.dev) + 2;
++	else
++		return -EINVAL;
++}
++
 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
 +{
 +	struct gpio_chip *chip = &bus->gpio;
@@ -626,6 +896,7 @@
 +	chip->set		= ssb_gpio_chipco_set_value;
 +	chip->direction_input	= ssb_gpio_chipco_direction_input;
 +	chip->direction_output	= ssb_gpio_chipco_direction_output;
++	chip->to_irq		= ssb_gpio_chipco_to_irq;
 +	chip->ngpio		= 16;
 +	/* There is just one SoC in one device and its GPIO addresses should be
 +	 * deterministic to address them more easily. The other buses could get
@@ -674,6 +945,16 @@
 +	return 0;
 +}
 +
++static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
++{
++	struct ssb_bus *bus = ssb_gpio_get_bus(chip);
++
++	if (bus->bustype == SSB_BUSTYPE_SSB)
++		return ssb_mips_irq(bus->extif.dev) + 2;
++	else
++		return -EINVAL;
++}
++
 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
 +{
 +	struct gpio_chip *chip = &bus->gpio;
@@ -684,6 +965,7 @@
 +	chip->set		= ssb_gpio_extif_set_value;
 +	chip->direction_input	= ssb_gpio_extif_direction_input;
 +	chip->direction_output	= ssb_gpio_extif_direction_output;
++	chip->to_irq		= ssb_gpio_extif_to_irq;
 +	chip->ngpio		= 5;
 +	/* There is just one SoC in one device and its GPIO addresses should be
 +	 * deterministic to address them more easily. The other buses could get
@@ -714,9 +996,88 @@
 +
 +	return -1;
 +}
++
++int ssb_gpio_unregister(struct ssb_bus *bus)
++{
++	if (ssb_chipco_available(&bus->chipco) ||
++	    ssb_extif_available(&bus->extif)) {
++		return gpiochip_remove(&bus->gpio);
++	} else {
++		SSB_WARN_ON(1);
++	}
++
++	return -1;
++}
 --- a/drivers/ssb/driver_mipscore.c
 +++ b/drivers/ssb/driver_mipscore.c
-@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
+@@ -10,6 +10,7 @@
+ 
+ #include <linux/ssb/ssb.h>
+ 
++#include <linux/mtd/physmap.h>
+ #include <linux/serial.h>
+ #include <linux/serial_core.h>
+ #include <linux/serial_reg.h>
+@@ -17,6 +18,25 @@
+ 
+ #include "ssb_private.h"
+ 
++static const char * const part_probes[] = { "bcm47xxpart", NULL };
++
++static struct physmap_flash_data ssb_pflash_data = {
++	.part_probe_types	= part_probes,
++};
++
++static struct resource ssb_pflash_resource = {
++	.name	= "ssb_pflash",
++	.flags  = IORESOURCE_MEM,
++};
++
++struct platform_device ssb_pflash_dev = {
++	.name		= "physmap-flash",
++	.dev		= {
++		.platform_data  = &ssb_pflash_data,
++	},
++	.resource	= &ssb_pflash_resource,
++	.num_resources	= 1,
++};
+ 
+ static inline u32 mips_read32(struct ssb_mipscore *mcore,
+ 			      u16 offset)
+@@ -147,21 +167,22 @@ static void set_irq(struct ssb_device *d
+ 		irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
+ 		ssb_write32(mdev, SSB_IPSFLAG, irqflag);
+ 	}
+-	ssb_dprintk(KERN_INFO PFX
+-		    "set_irq: core 0x%04x, irq %d => %d\n",
+-		    dev->id.coreid, oldirq+2, irq+2);
++	ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
++		dev->id.coreid, oldirq+2, irq+2);
+ }
+ 
+ static void print_irq(struct ssb_device *dev, unsigned int irq)
+ {
+-	int i;
+ 	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
+-	ssb_dprintk(KERN_INFO PFX
+-		"core 0x%04x, irq :", dev->id.coreid);
+-	for (i = 0; i <= 6; i++) {
+-		ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
+-	}
+-	ssb_dprintk("\n");
++	ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
++		dev->id.coreid,
++		irq_name[0], irq == 0 ? "*" : " ",
++		irq_name[1], irq == 1 ? "*" : " ",
++		irq_name[2], irq == 2 ? "*" : " ",
++		irq_name[3], irq == 3 ? "*" : " ",
++		irq_name[4], irq == 4 ? "*" : " ",
++		irq_name[5], irq == 5 ? "*" : " ",
++		irq_name[6], irq == 6 ? "*" : " ");
+ }
+ 
+ static void dump_irq(struct ssb_bus *bus)
+@@ -178,9 +199,9 @@ static void ssb_mips_serial_init(struct
  {
  	struct ssb_bus *bus = mcore->dev->bus;
  
@@ -728,9 +1089,11 @@
  		mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
  	else
  		mcore->nr_serial_ports = 0;
-@@ -190,16 +190,33 @@ static void ssb_mips_flash_detect(struct
+@@ -189,17 +210,42 @@ static void ssb_mips_serial_init(struct
+ static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
  {
  	struct ssb_bus *bus = mcore->dev->bus;
++	struct ssb_pflash *pflash = &mcore->pflash;
  
 -	mcore->flash_buswidth = 2;
 -	if (bus->chipco.dev) {
@@ -738,11 +1101,11 @@
 -		mcore->flash_window_size = 0x02000000;
 +	/* When there is no chipcommon on the bus there is 4MB flash */
 +	if (!ssb_chipco_available(&bus->chipco)) {
-+		mcore->pflash.present = true;
-+		mcore->pflash.buswidth = 2;
-+		mcore->pflash.window = SSB_FLASH1;
-+		mcore->pflash.window_size = SSB_FLASH1_SZ;
-+		return;
++		pflash->present = true;
++		pflash->buswidth = 2;
++		pflash->window = SSB_FLASH1;
++		pflash->window_size = SSB_FLASH1_SZ;
++		goto ssb_pflash;
 +	}
 +
 +	/* There is ChipCommon, so use it to read info about flash */
@@ -754,23 +1117,30 @@
 +		break;
 +	case SSB_CHIPCO_FLASHT_PARA:
 +		pr_debug("Found parallel flash\n");
-+		mcore->pflash.present = true;
-+		mcore->pflash.window = SSB_FLASH2;
-+		mcore->pflash.window_size = SSB_FLASH2_SZ;
++		pflash->present = true;
++		pflash->window = SSB_FLASH2;
++		pflash->window_size = SSB_FLASH2_SZ;
  		if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
  		               & SSB_CHIPCO_CFG_DS16) == 0)
 -			mcore->flash_buswidth = 1;
 -	} else {
 -		mcore->flash_window = 0x1fc00000;
 -		mcore->flash_window_size = 0x00400000;
-+			mcore->pflash.buswidth = 1;
++			pflash->buswidth = 1;
 +		else
-+			mcore->pflash.buswidth = 2;
++			pflash->buswidth = 2;
 +		break;
++	}
++
++ssb_pflash:
++	if (pflash->present) {
++		ssb_pflash_data.width = pflash->buswidth;
++		ssb_pflash_resource.start = pflash->window;
++		ssb_pflash_resource.end = pflash->window + pflash->window_size;
  	}
  }
  
-@@ -211,9 +228,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
+@@ -211,9 +257,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
  	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
  		return ssb_pmu_get_cpu_clock(&bus->chipco);
  
@@ -782,7 +1152,16 @@
  		ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
  	} else
  		return 0;
-@@ -249,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco
+@@ -241,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipsco
+ 	if (!mcore->dev)
+ 		return; /* We don't have a MIPS core */
+ 
+-	ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
++	ssb_dbg("Initializing MIPS core...\n");
+ 
+ 	bus = mcore->dev->bus;
+ 	hz = ssb_clockspeed(bus);
+@@ -249,9 +295,9 @@ void ssb_mipscore_init(struct ssb_mipsco
  		hz = 100000000;
  	ns = 1000000000 / hz;
  
@@ -794,6 +1173,71 @@
  		ssb_chipco_timing_init(&bus->chipco, ns);
  
  	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+@@ -289,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipsco
+ 			break;
+ 		}
+ 	}
+-	ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
++	ssb_dbg("after irq reconfiguration\n");
+ 	dump_irq(bus);
+ 
+ 	ssb_mips_serial_init(mcore);
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci
+ 		return -ENODEV;
+ 	}
+ 
+-	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
+-		   pci_name(d));
++	ssb_info("PCI: Fixing up device %s\n", pci_name(d));
+ 
+ 	/* Fix up interrupt lines */
+ 	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
+@@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(
+ 	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
+ 		return;
+ 
+-	ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
++	ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev));
+ 
+ 	/* Enable PCI bridge bus mastering and memory space */
+ 	pci_set_master(dev);
+ 	if (pcibios_enable_device(dev, ~0) < 0) {
+-		ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
++		ssb_err("PCI: SSB bridge enable failed\n");
+ 		return;
+ 	}
+ 
+@@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge(
+ 
+ 	/* Make sure our latency is high enough to handle the devices behind us */
+ 	lat = 168;
+-	ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
+-		   pci_name(dev), lat);
++	ssb_info("PCI: Fixing latency timer of device %s to %u\n",
++		 pci_name(dev), lat);
+ 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
+ }
+ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
+@@ -323,7 +322,7 @@ static void __devinit ssb_pcicore_init_h
+ 		return;
+ 	extpci_core = pc;
+ 
+-	ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
++	ssb_dbg("PCIcore in host mode found\n");
+ 	/* Reset devices on the external PCI bus */
+ 	val = SSB_PCICORE_CTL_RST_OE;
+ 	val |= SSB_PCICORE_CTL_CLK_OE;
+@@ -338,7 +337,7 @@ static void __devinit ssb_pcicore_init_h
+ 	udelay(1); /* Assertion time demanded by the PCI standard */
+ 
+ 	if (pc->dev->bus->has_cardbus_slot) {
+-		ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
++		ssb_dbg("CardBus slot detected\n");
+ 		pc->cardbusmode = 1;
+ 		/* GPIO 1 resets the bridge */
+ 		ssb_gpio_out(pc->dev->bus, 1, 1);
 --- a/drivers/ssb/embedded.c
 +++ b/drivers/ssb/embedded.c
 @@ -4,11 +4,13 @@
@@ -810,7 +1254,7 @@
  #include <linux/ssb/ssb.h>
  #include <linux/ssb/ssb_embedded.h>
  #include <linux/ssb/ssb_driver_pci.h>
-@@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
+@@ -32,6 +34,38 @@ int ssb_watchdog_timer_set(struct ssb_bu
  }
  EXPORT_SYMBOL(ssb_watchdog_timer_set);
  
@@ -837,9 +1281,8 @@
 +					     bus->busnumber, &wdt,
 +					     sizeof(wdt));
 +	if (IS_ERR(pdev)) {
-+		ssb_dprintk(KERN_INFO PFX
-+			    "can not register watchdog device, err: %li\n",
-+			    PTR_ERR(pdev));
++		ssb_dbg("can not register watchdog device, err: %li\n",
++			PTR_ERR(pdev));
 +		return PTR_ERR(pdev);
 +	}
 +
@@ -860,7 +1303,18 @@
  #include <linux/ssb/ssb.h>
  #include <linux/ssb/ssb_regs.h>
  #include <linux/ssb/ssb_driver_gige.h>
-@@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
+@@ -274,8 +275,8 @@ int ssb_devices_thaw(struct ssb_freeze_c
+ 
+ 		err = sdrv->probe(sdev, &sdev->id);
+ 		if (err) {
+-			ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
+-				   dev_name(sdev->dev));
++			ssb_err("Failed to thaw device %s\n",
++				dev_name(sdev->dev));
+ 			result = err;
+ 		}
+ 		ssb_device_put(sdev);
+@@ -433,10 +434,23 @@ static void ssb_devices_unregister(struc
  		if (sdev->dev)
  			device_unregister(sdev->dev);
  	}
@@ -872,7 +1326,63 @@
  }
  
  void ssb_bus_unregister(struct ssb_bus *bus)
-@@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
+ {
++	int err;
++
++	err = ssb_gpio_unregister(bus);
++	if (err == -EBUSY)
++		ssb_dbg("Some GPIOs are still in use\n");
++	else if (err)
++		ssb_dbg("Can not unregister GPIO driver: %i\n", err);
++
+ 	ssb_buses_lock();
+ 	ssb_devices_unregister(bus);
+ 	list_del(&bus->list);
+@@ -482,8 +496,7 @@ static int ssb_devices_register(struct s
+ 
+ 		devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
+ 		if (!devwrap) {
+-			ssb_printk(KERN_ERR PFX
+-				   "Could not allocate device\n");
++			ssb_err("Could not allocate device\n");
+ 			err = -ENOMEM;
+ 			goto error;
+ 		}
+@@ -522,9 +535,7 @@ static int ssb_devices_register(struct s
+ 		sdev->dev = dev;
+ 		err = device_register(dev);
+ 		if (err) {
+-			ssb_printk(KERN_ERR PFX
+-				   "Could not register %s\n",
+-				   dev_name(dev));
++			ssb_err("Could not register %s\n", dev_name(dev));
+ 			/* Set dev to NULL to not unregister
+ 			 * dev on error unwinding. */
+ 			sdev->dev = NULL;
+@@ -534,6 +545,22 @@ static int ssb_devices_register(struct s
+ 		dev_idx++;
+ 	}
+ 
++#ifdef CONFIG_SSB_DRIVER_MIPS
++	if (bus->mipscore.pflash.present) {
++		err = platform_device_register(&ssb_pflash_dev);
++		if (err)
++			pr_err("Error registering parallel flash\n");
++	}
++#endif
++
++#ifdef CONFIG_SSB_SFLASH
++	if (bus->mipscore.sflash.present) {
++		err = platform_device_register(&ssb_sflash_dev);
++		if (err)
++			pr_err("Error registering serial flash\n");
++	}
++#endif
++
+ 	return 0;
+ error:
+ 	/* Unwind the already registered devices. */
+@@ -561,6 +588,8 @@ static int __devinit ssb_attach_queued_b
  		if (err)
  			goto error;
  		ssb_pcicore_init(&bus->pcicore);
@@ -881,7 +1391,7 @@
  		ssb_bus_may_powerdown(bus);
  
  		err = ssb_devices_register(bus);
-@@ -796,7 +804,14 @@ static int __devinit ssb_bus_register(st
+@@ -796,7 +825,13 @@ static int __devinit ssb_bus_register(st
  	if (err)
  		goto err_pcmcia_exit;
  	ssb_chipcommon_init(&bus->chipco);
@@ -889,14 +1399,62 @@
  	ssb_mipscore_init(&bus->mipscore);
 +	err = ssb_gpio_init(bus);
 +	if (err == -ENOTSUPP)
-+		ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
++		ssb_dbg("GPIO driver not activated\n");
 +	else if (err)
-+		ssb_dprintk(KERN_ERR PFX
-+			   "Error registering GPIO driver: %i\n", err);
++		ssb_dbg("Error registering GPIO driver: %i\n", err);
  	err = ssb_fetch_invariants(bus, get_invariants);
  	if (err) {
  		ssb_bus_may_powerdown(bus);
-@@ -1118,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str
+@@ -847,11 +882,11 @@ int __devinit ssb_bus_pcibus_register(st
+ 
+ 	err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
+ 	if (!err) {
+-		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
+-			   "PCI device %s\n", dev_name(&host_pci->dev));
++		ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
++			 dev_name(&host_pci->dev));
+ 	} else {
+-		ssb_printk(KERN_ERR PFX "Failed to register PCI version"
+-			   " of SSB with error %d\n", err);
++		ssb_err("Failed to register PCI version of SSB with error %d\n",
++			err);
+ 	}
+ 
+ 	return err;
+@@ -872,8 +907,8 @@ int __devinit ssb_bus_pcmciabus_register
+ 
+ 	err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
+ 	if (!err) {
+-		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
+-			   "PCMCIA device %s\n", pcmcia_dev->devname);
++		ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
++			 pcmcia_dev->devname);
+ 	}
+ 
+ 	return err;
+@@ -895,8 +930,8 @@ int __devinit ssb_bus_sdiobus_register(s
+ 
+ 	err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
+ 	if (!err) {
+-		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
+-			   "SDIO device %s\n", sdio_func_id(func));
++		ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
++			 sdio_func_id(func));
+ 	}
+ 
+ 	return err;
+@@ -915,8 +950,8 @@ int __devinit ssb_bus_ssbbus_register(st
+ 
+ 	err = ssb_bus_register(bus, get_invariants, baseaddr);
+ 	if (!err) {
+-		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
+-			   "address 0x%08lX\n", baseaddr);
++		ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
++			 baseaddr);
+ 	}
+ 
+ 	return err;
+@@ -1118,8 +1153,7 @@ static u32 ssb_tmslow_reject_bitmask(str
  	case SSB_IDLOW_SSBREV_27:     /* same here */
  		return SSB_TMSLOW_REJECT;	/* this is a guess */
  	default:
@@ -906,9 +1464,589 @@
  	}
  	return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
  }
+@@ -1311,7 +1345,7 @@ out:
+ #endif
+ 	return err;
+ error:
+-	ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
++	ssb_err("Bus powerdown failed\n");
+ 	goto out;
+ }
+ EXPORT_SYMBOL(ssb_bus_may_powerdown);
+@@ -1334,7 +1368,7 @@ int ssb_bus_powerup(struct ssb_bus *bus,
+ 
+ 	return 0;
+ error:
+-	ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
++	ssb_err("Bus powerup failed\n");
+ 	return err;
+ }
+ EXPORT_SYMBOL(ssb_bus_powerup);
+@@ -1442,15 +1476,13 @@ static int __init ssb_modinit(void)
+ 
+ 	err = b43_pci_ssb_bridge_init();
+ 	if (err) {
+-		ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
+-			   "initialization failed\n");
++		ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
+ 		/* don't fail SSB init because of this */
+ 		err = 0;
+ 	}
+ 	err = ssb_gige_init();
+ 	if (err) {
+-		ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
+-			   "driver initialization failed\n");
++		ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
+ 		/* don't fail SSB init because of this */
+ 		err = 0;
+ 	}
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu
+ 	}
+ 	return 0;
+ error:
+-	ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
++	ssb_err("Failed to switch to core %u\n", coreidx);
+ 	return -ENODEV;
+ }
+ 
+@@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus *
+ 	unsigned long flags;
+ 
+ #if SSB_VERBOSE_PCICORESWITCH_DEBUG
+-	ssb_printk(KERN_INFO PFX
+-		   "Switching to %s core, index %d\n",
+-		   ssb_core_name(dev->id.coreid),
+-		   dev->core_index);
++	ssb_info("Switching to %s core, index %d\n",
++		 ssb_core_name(dev->id.coreid),
++		 dev->core_index);
+ #endif
+ 
+ 	spin_lock_irqsave(&bus->bar_lock, flags);
+@@ -231,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat
+ 	return t[crc ^ data];
+ }
+ 
++static void sprom_get_mac(char *mac, const u16 *in)
++{
++	int i;
++	for (i = 0; i < 3; i++) {
++		*mac++ = in[i] >> 8;
++		*mac++ = in[i];
++	}
++}
++
+ static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
+ {
+ 	int word;
+@@ -278,7 +286,7 @@ static int sprom_do_write(struct ssb_bus
+ 	u32 spromctl;
+ 	u16 size = bus->sprom_size;
+ 
+-	ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
++	ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
+ 	err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
+ 	if (err)
+ 		goto err_ctlreg;
+@@ -286,17 +294,17 @@ static int sprom_do_write(struct ssb_bus
+ 	err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
+ 	if (err)
+ 		goto err_ctlreg;
+-	ssb_printk(KERN_NOTICE PFX "[ 0%%");
++	ssb_notice("[ 0%%");
+ 	msleep(500);
+ 	for (i = 0; i < size; i++) {
+ 		if (i == size / 4)
+-			ssb_printk("25%%");
++			ssb_cont("25%%");
+ 		else if (i == size / 2)
+-			ssb_printk("50%%");
++			ssb_cont("50%%");
+ 		else if (i == (size * 3) / 4)
+-			ssb_printk("75%%");
++			ssb_cont("75%%");
+ 		else if (i % 2)
+-			ssb_printk(".");
++			ssb_cont(".");
+ 		writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
+ 		mmiowb();
+ 		msleep(20);
+@@ -309,12 +317,12 @@ static int sprom_do_write(struct ssb_bus
+ 	if (err)
+ 		goto err_ctlreg;
+ 	msleep(500);
+-	ssb_printk("100%% ]\n");
+-	ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
++	ssb_cont("100%% ]\n");
++	ssb_notice("SPROM written\n");
+ 
+ 	return 0;
+ err_ctlreg:
+-	ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
++	ssb_err("Could not access SPROM control register.\n");
+ 	return err;
+ }
+ 
+@@ -339,10 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_
+ 	return (s8)gain;
+ }
+ 
++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
++{
++	SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
++	SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
++	SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
++	SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
++	SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
++	SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
++	SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
++	SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
++	SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
++	SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
++	     SSB_SPROM2_MAXP_A_LO_SHIFT);
++}
++
+ static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
+ {
+-	int i;
+-	u16 v;
+ 	u16 loc[3];
+ 
+ 	if (out->revision == 3)			/* rev 3 moved MAC */
+@@ -352,19 +373,10 @@ static void sprom_extract_r123(struct ss
+ 		loc[1] = SSB_SPROM1_ET0MAC;
+ 		loc[2] = SSB_SPROM1_ET1MAC;
+ 	}
+-	for (i = 0; i < 3; i++) {
+-		v = in[SPOFF(loc[0]) + i];
+-		*(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
+-	}
++	sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
+ 	if (out->revision < 3) { 	/* only rev 1-2 have et0, et1 */
+-		for (i = 0; i < 3; i++) {
+-			v = in[SPOFF(loc[1]) + i];
+-			*(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
+-		}
+-		for (i = 0; i < 3; i++) {
+-			v = in[SPOFF(loc[2]) + i];
+-			*(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
+-		}
++		sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
++		sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
+ 	}
+ 	SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
+ 	SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
+@@ -372,6 +384,7 @@ static void sprom_extract_r123(struct ss
+ 	SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
+ 	SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
+ 	SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
++	SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
+ 	if (out->revision == 1)
+ 		SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
+ 		     SSB_SPROM1_BINF_CCODE_SHIFT);
+@@ -398,8 +411,7 @@ static void sprom_extract_r123(struct ss
+ 	     SSB_SPROM1_ITSSI_A_SHIFT);
+ 	SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
+ 	SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
+-	if (out->revision >= 2)
+-		SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
++
+ 	SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
+ 	SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
+ 
+@@ -410,6 +422,8 @@ static void sprom_extract_r123(struct ss
+ 	out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
+ 						    SSB_SPROM1_AGAIN_A,
+ 						    SSB_SPROM1_AGAIN_A_SHIFT);
++	if (out->revision >= 2)
++		sprom_extract_r23(out, in);
+ }
+ 
+ /* Revs 4 5 and 8 have partially shared layout */
+@@ -454,23 +468,20 @@ static void sprom_extract_r458(struct ss
+ 
+ static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
+ {
+-	int i;
+-	u16 v;
+ 	u16 il0mac_offset;
+ 
+ 	if (out->revision == 4)
+ 		il0mac_offset = SSB_SPROM4_IL0MAC;
+ 	else
+ 		il0mac_offset = SSB_SPROM5_IL0MAC;
+-	/* extract the MAC address */
+-	for (i = 0; i < 3; i++) {
+-		v = in[SPOFF(il0mac_offset) + i];
+-		*(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
+-	}
++
++	sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
++
+ 	SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
+ 	SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
+ 	     SSB_SPROM4_ETHPHY_ET1A_SHIFT);
+ 	SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
++	SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
+ 	if (out->revision == 4) {
+ 		SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
+ 		SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
+@@ -530,7 +541,7 @@ static void sprom_extract_r45(struct ssb
+ static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
+ {
+ 	int i;
+-	u16 v, o;
++	u16 o;
+ 	u16 pwr_info_offset[] = {
+ 		SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
+ 		SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
+@@ -539,11 +550,10 @@ static void sprom_extract_r8(struct ssb_
+ 			ARRAY_SIZE(out->core_pwr_info));
+ 
+ 	/* extract the MAC address */
+-	for (i = 0; i < 3; i++) {
+-		v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
+-		*(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
+-	}
++	sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
++
+ 	SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
++	SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
+ 	SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
+ 	SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
+ 	SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
+@@ -743,7 +753,7 @@ static int sprom_extract(struct ssb_bus
+ 	memset(out, 0, sizeof(*out));
+ 
+ 	out->revision = in[size - 1] & 0x00FF;
+-	ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
++	ssb_dbg("SPROM revision %d detected\n", out->revision);
+ 	memset(out->et0mac, 0xFF, 6);		/* preset et0 and et1 mac */
+ 	memset(out->et1mac, 0xFF, 6);
+ 
+@@ -752,7 +762,7 @@ static int sprom_extract(struct ssb_bus
+ 		 * number stored in the SPROM.
+ 		 * Always extract r1. */
+ 		out->revision = 1;
+-		ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
++		ssb_dbg("SPROM treated as revision %d\n", out->revision);
+ 	}
+ 
+ 	switch (out->revision) {
+@@ -769,9 +779,8 @@ static int sprom_extract(struct ssb_bus
+ 		sprom_extract_r8(out, in);
+ 		break;
+ 	default:
+-		ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
+-			   " revision %d detected. Will extract"
+-			   " v1\n", out->revision);
++		ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
++			 out->revision);
+ 		out->revision = 1;
+ 		sprom_extract_r123(out, in);
+ 	}
+@@ -791,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_
+ 	u16 *buf;
+ 
+ 	if (!ssb_is_sprom_available(bus)) {
+-		ssb_printk(KERN_ERR PFX "No SPROM available!\n");
++		ssb_err("No SPROM available!\n");
+ 		return -ENODEV;
+ 	}
+ 	if (bus->chipco.dev) {	/* can be unavailable! */
+@@ -810,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_
+ 	} else {
+ 		bus->sprom_offset = SSB_SPROM_BASE1;
+ 	}
+-	ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
++	ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset);
+ 
+ 	buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
+ 	if (!buf)
+@@ -835,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_
+ 			 * available for this device in some other storage */
+ 			err = ssb_fill_sprom_with_fallback(bus, sprom);
+ 			if (err) {
+-				ssb_printk(KERN_WARNING PFX "WARNING: Using"
+-					   " fallback SPROM failed (err %d)\n",
+-					   err);
++				ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n",
++					 err);
+ 			} else {
+-				ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
+-					    " revision %d provided by"
+-					    " platform.\n", sprom->revision);
++				ssb_dbg("Using SPROM revision %d provided by platform\n",
++					sprom->revision);
+ 				err = 0;
+ 				goto out_free;
+ 			}
+-			ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
+-				   " SPROM CRC (corrupt SPROM)\n");
++			ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
+ 		}
+ 	}
+ 	err = sprom_extract(bus, sprom, buf, bus->sprom_size);
+--- a/drivers/ssb/pcihost_wrapper.c
++++ b/drivers/ssb/pcihost_wrapper.c
+@@ -38,7 +38,7 @@ static int ssb_pcihost_resume(struct pci
+ 	struct ssb_bus *ssb = pci_get_drvdata(dev);
+ 	int err;
+ 
+-	pci_set_power_state(dev, 0);
++	pci_set_power_state(dev, PCI_D0);
+ 	err = pci_enable_device(dev);
+ 	if (err)
+ 		return err;
+--- a/drivers/ssb/pcmcia.c
++++ b/drivers/ssb/pcmcia.c
+@@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb
+ 
+ 	return 0;
+ error:
+-	ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
++	ssb_err("Failed to switch to core %u\n", coreidx);
+ 	return err;
+ }
+ 
+@@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu
+ 	int err;
+ 
+ #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
+-	ssb_printk(KERN_INFO PFX
+-		   "Switching to %s core, index %d\n",
+-		   ssb_core_name(dev->id.coreid),
+-		   dev->core_index);
++	ssb_info("Switching to %s core, index %d\n",
++		 ssb_core_name(dev->id.coreid),
++		 dev->core_index);
+ #endif
+ 
+ 	err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
+@@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb
+ 
+ 	return 0;
+ error:
+-	ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
++	ssb_err("Failed to switch pcmcia segment\n");
+ 	return err;
+ }
+ 
+@@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st
+ 	bool failed = 0;
+ 	size_t size = SSB_PCMCIA_SPROM_SIZE;
+ 
+-	ssb_printk(KERN_NOTICE PFX
+-		   "Writing SPROM. Do NOT turn off the power! "
+-		   "Please stand by...\n");
++	ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
+ 	err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN);
+ 	if (err) {
+-		ssb_printk(KERN_NOTICE PFX
+-			   "Could not enable SPROM write access.\n");
++		ssb_notice("Could not enable SPROM write access\n");
+ 		return -EBUSY;
+ 	}
+-	ssb_printk(KERN_NOTICE PFX "[ 0%%");
++	ssb_notice("[ 0%%");
+ 	msleep(500);
+ 	for (i = 0; i < size; i++) {
+ 		if (i == size / 4)
+-			ssb_printk("25%%");
++			ssb_cont("25%%");
+ 		else if (i == size / 2)
+-			ssb_printk("50%%");
++			ssb_cont("50%%");
+ 		else if (i == (size * 3) / 4)
+-			ssb_printk("75%%");
++			ssb_cont("75%%");
+ 		else if (i % 2)
+-			ssb_printk(".");
++			ssb_cont(".");
+ 		err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
+ 		if (err) {
+-			ssb_printk(KERN_NOTICE PFX
+-				   "Failed to write to SPROM.\n");
++			ssb_notice("Failed to write to SPROM\n");
+ 			failed = 1;
+ 			break;
+ 		}
+ 	}
+ 	err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
+ 	if (err) {
+-		ssb_printk(KERN_NOTICE PFX
+-			   "Could not disable SPROM write access.\n");
++		ssb_notice("Could not disable SPROM write access\n");
+ 		failed = 1;
+ 	}
+ 	msleep(500);
+ 	if (!failed) {
+-		ssb_printk("100%% ]\n");
+-		ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
++		ssb_cont("100%% ]\n");
++		ssb_notice("SPROM written\n");
+ 	}
+ 
+ 	return failed ? -EBUSY : 0;
+@@ -700,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants(
+ 	return -ENOSPC; /* continue with next entry */
+ 
+ error:
+-	ssb_printk(KERN_ERR PFX
++	ssb_err(
+ 		   "PCMCIA: Failed to fetch device invariants: %s\n",
+ 		   error_description);
+ 	return -ENODEV;
+@@ -722,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb
+ 	res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
+ 				ssb_pcmcia_get_mac, sprom);
+ 	if (res != 0) {
+-		ssb_printk(KERN_ERR PFX
++		ssb_err(
+ 			"PCMCIA: Failed to fetch MAC address\n");
+ 		return -ENODEV;
+ 	}
+@@ -733,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb
+ 	if ((res == 0) || (res == -ENOSPC))
+ 		return 0;
+ 
+-	ssb_printk(KERN_ERR PFX
++	ssb_err(
+ 			"PCMCIA: Failed to fetch device invariants\n");
+ 	return -ENODEV;
+ }
+@@ -843,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus)
+ 
+ 	return 0;
+ error:
+-	ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n");
++	ssb_err("Failed to initialize PCMCIA host device\n");
+ 	return err;
+ }
+--- a/drivers/ssb/scan.c
++++ b/drivers/ssb/scan.c
+@@ -125,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d
+ 		chipid_fallback = 0x4401;
+ 		break;
+ 	default:
+-		ssb_printk(KERN_ERR PFX
+-			   "PCI-ID not in fallback list\n");
++		ssb_err("PCI-ID not in fallback list\n");
+ 	}
+ 
+ 	return chipid_fallback;
+@@ -152,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid)
+ 	case 0x4704:
+ 		return 9;
+ 	default:
+-		ssb_printk(KERN_ERR PFX
+-			   "CHIPID not in nrcores fallback list\n");
++		ssb_err("CHIPID not in nrcores fallback list\n");
+ 	}
+ 
+ 	return 1;
+@@ -320,15 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 			bus->chip_package = 0;
+ 		}
+ 	}
+-	ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
+-		   "package 0x%02X\n", bus->chip_id, bus->chip_rev,
+-		   bus->chip_package);
++	ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
++		 bus->chip_id, bus->chip_rev, bus->chip_package);
+ 	if (!bus->nr_devices)
+ 		bus->nr_devices = chipid_to_nrcores(bus->chip_id);
+ 	if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
+-		ssb_printk(KERN_ERR PFX
+-			   "More than %d ssb cores found (%d)\n",
+-			   SSB_MAX_NR_CORES, bus->nr_devices);
++		ssb_err("More than %d ssb cores found (%d)\n",
++			SSB_MAX_NR_CORES, bus->nr_devices);
+ 		goto err_unmap;
+ 	}
+ 	if (bus->bustype == SSB_BUSTYPE_SSB) {
+@@ -370,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 			nr_80211_cores++;
+ 			if (nr_80211_cores > 1) {
+ 				if (!we_support_multiple_80211_cores(bus)) {
+-					ssb_dprintk(KERN_INFO PFX "Ignoring additional "
+-						    "802.11 core\n");
++					ssb_dbg("Ignoring additional 802.11 core\n");
+ 					continue;
+ 				}
+ 			}
+@@ -379,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 		case SSB_DEV_EXTIF:
+ #ifdef CONFIG_SSB_DRIVER_EXTIF
+ 			if (bus->extif.dev) {
+-				ssb_printk(KERN_WARNING PFX
+-					   "WARNING: Multiple EXTIFs found\n");
++				ssb_warn("WARNING: Multiple EXTIFs found\n");
+ 				break;
+ 			}
+ 			bus->extif.dev = dev;
+@@ -388,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 			break;
+ 		case SSB_DEV_CHIPCOMMON:
+ 			if (bus->chipco.dev) {
+-				ssb_printk(KERN_WARNING PFX
+-					   "WARNING: Multiple ChipCommon found\n");
++				ssb_warn("WARNING: Multiple ChipCommon found\n");
+ 				break;
+ 			}
+ 			bus->chipco.dev = dev;
+@@ -398,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 		case SSB_DEV_MIPS_3302:
+ #ifdef CONFIG_SSB_DRIVER_MIPS
+ 			if (bus->mipscore.dev) {
+-				ssb_printk(KERN_WARNING PFX
+-					   "WARNING: Multiple MIPS cores found\n");
++				ssb_warn("WARNING: Multiple MIPS cores found\n");
+ 				break;
+ 			}
+ 			bus->mipscore.dev = dev;
+@@ -420,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 				}
+ 			}
+ 			if (bus->pcicore.dev) {
+-				ssb_printk(KERN_WARNING PFX
+-					   "WARNING: Multiple PCI(E) cores found\n");
++				ssb_warn("WARNING: Multiple PCI(E) cores found\n");
+ 				break;
+ 			}
+ 			bus->pcicore.dev = dev;
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -54,7 +54,7 @@ static int hex2sprom(u16 *sprom, const c
+ 	while (cnt < sprom_size_words) {
+ 		memcpy(tmp, dump, 4);
+ 		dump += 4;
+-		err = strict_strtoul(tmp, 16, &parsed);
++		err = kstrtoul(tmp, 16, &parsed);
+ 		if (err)
+ 			return err;
+ 		sprom[cnt++] = swab16((u16)parsed);
+@@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
+ 		goto out_kfree;
+ 	err = ssb_devices_freeze(bus, &freeze);
+ 	if (err) {
+-		ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
++		ssb_err("SPROM write: Could not freeze all devices\n");
+ 		goto out_unlock;
+ 	}
+ 	res = sprom_write(bus, sprom);
+ 	err = ssb_devices_thaw(&freeze);
+ 	if (err)
+-		ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
++		ssb_err("SPROM write: Could not thaw all devices\n");
+ out_unlock:
+ 	mutex_unlock(&bus->sprom_mutex);
+ out_kfree:
 --- a/drivers/ssb/ssb_private.h
 +++ b/drivers/ssb/ssb_private.h
-@@ -3,6 +3,7 @@
+@@ -3,21 +3,33 @@
  
  #include <linux/ssb/ssb.h>
  #include <linux/types.h>
@@ -916,7 +2054,37 @@
  
  
  #define PFX	"ssb: "
-@@ -210,5 +211,63 @@ static inline void b43_pci_ssb_bridge_ex
+ 
+ #ifdef CONFIG_SSB_SILENT
+-# define ssb_printk(fmt, x...)	do { /* nothing */ } while (0)
++# define ssb_printk(fmt, ...)					\
++	do { if (0) printk(fmt, ##__VA_ARGS__); } while (0)
+ #else
+-# define ssb_printk		printk
++# define ssb_printk(fmt, ...)					\
++	printk(fmt, ##__VA_ARGS__)
+ #endif /* CONFIG_SSB_SILENT */
+ 
++#define ssb_emerg(fmt, ...)	ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__)
++#define ssb_err(fmt, ...)	ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__)
++#define ssb_warn(fmt, ...)	ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__)
++#define ssb_notice(fmt, ...)	ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__)
++#define ssb_info(fmt, ...)	ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__)
++#define ssb_cont(fmt, ...)	ssb_printk(KERN_CONT fmt, ##__VA_ARGS__)
++
+ /* dprintk: Debugging printk; vanishes for non-debug compilation */
+ #ifdef CONFIG_SSB_DEBUG
+-# define ssb_dprintk(fmt, x...)	ssb_printk(fmt , ##x)
++# define ssb_dbg(fmt, ...)					\
++	ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__)
+ #else
+-# define ssb_dprintk(fmt, x...)	do { /* nothing */ } while (0)
++# define ssb_dbg(fmt, ...)					\
++	do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0)
+ #endif
+ 
+ #ifdef CONFIG_SSB_DEBUG
+@@ -210,5 +222,76 @@ static inline void b43_pci_ssb_bridge_ex
  /* driver_chipcommon_pmu.c */
  extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
  extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
@@ -937,6 +2105,14 @@
 +}
 +#endif /* CONFIG_SSB_SFLASH */
 +
++#ifdef CONFIG_SSB_DRIVER_MIPS
++extern struct platform_device ssb_pflash_dev;
++#endif
++
++#ifdef CONFIG_SSB_SFLASH
++extern struct platform_device ssb_sflash_dev;
++#endif
++
 +#ifdef CONFIG_SSB_DRIVER_EXTIF
 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
@@ -972,11 +2148,16 @@
 +
 +#ifdef CONFIG_SSB_DRIVER_GPIO
 +extern int ssb_gpio_init(struct ssb_bus *bus);
++extern int ssb_gpio_unregister(struct ssb_bus *bus);
 +#else /* CONFIG_SSB_DRIVER_GPIO */
 +static inline int ssb_gpio_init(struct ssb_bus *bus)
 +{
 +	return -ENOTSUPP;
 +}
++static inline int ssb_gpio_unregister(struct ssb_bus *bus)
++{
++	return 0;
++}
 +#endif /* CONFIG_SSB_DRIVER_GPIO */
  
  #endif /* LINUX_SSB_PRIVATE_H_ */
@@ -993,7 +2174,85 @@
  
  #include <linux/ssb/ssb_regs.h>
  
-@@ -432,7 +434,11 @@ struct ssb_bus {
+@@ -24,9 +26,9 @@ struct ssb_sprom_core_pwr_info {
+ 
+ struct ssb_sprom {
+ 	u8 revision;
+-	u8 il0mac[6];		/* MAC address for 802.11b/g */
+-	u8 et0mac[6];		/* MAC address for Ethernet */
+-	u8 et1mac[6];		/* MAC address for 802.11a */
++	u8 il0mac[6] __aligned(sizeof(u16));	/* MAC address for 802.11b/g */
++	u8 et0mac[6] __aligned(sizeof(u16));	/* MAC address for Ethernet */
++	u8 et1mac[6] __aligned(sizeof(u16));	/* MAC address for 802.11a */
+ 	u8 et0phyaddr;		/* MII address for enet0 */
+ 	u8 et1phyaddr;		/* MII address for enet1 */
+ 	u8 et0mdcport;		/* MDIO for enet0 */
+@@ -338,13 +340,61 @@ enum ssb_bustype {
+ #define SSB_BOARDVENDOR_DELL	0x1028	/* Dell */
+ #define SSB_BOARDVENDOR_HP	0x0E11	/* HP */
+ /* board_type */
++#define SSB_BOARD_BCM94301CB	0x0406
++#define SSB_BOARD_BCM94301MP	0x0407
++#define SSB_BOARD_BU4309	0x040A
++#define SSB_BOARD_BCM94309CB	0x040B
++#define SSB_BOARD_BCM4309MP	0x040C
++#define SSB_BOARD_BU4306	0x0416
+ #define SSB_BOARD_BCM94306MP	0x0418
+ #define SSB_BOARD_BCM4309G	0x0421
+ #define SSB_BOARD_BCM4306CB	0x0417
+-#define SSB_BOARD_BCM4309MP	0x040C
++#define SSB_BOARD_BCM94306PC	0x0425	/* pcmcia 3.3v 4306 card */
++#define SSB_BOARD_BCM94306CBSG	0x042B	/* with SiGe PA */
++#define SSB_BOARD_PCSG94306	0x042D	/* with SiGe PA */
++#define SSB_BOARD_BU4704SD	0x042E	/* with sdram */
++#define SSB_BOARD_BCM94704AGR	0x042F	/* dual 11a/11g Router */
++#define SSB_BOARD_BCM94308MP	0x0430	/* 11a-only minipci */
++#define SSB_BOARD_BU4318	0x0447
++#define SSB_BOARD_CB4318	0x0448
++#define SSB_BOARD_MPG4318	0x0449
+ #define SSB_BOARD_MP4318	0x044A
+-#define SSB_BOARD_BU4306	0x0416
+-#define SSB_BOARD_BU4309	0x040A
++#define SSB_BOARD_SD4318	0x044B
++#define SSB_BOARD_BCM94306P	0x044C	/* with SiGe */
++#define SSB_BOARD_BCM94303MP	0x044E
++#define SSB_BOARD_BCM94306MPM	0x0450
++#define SSB_BOARD_BCM94306MPL	0x0453
++#define SSB_BOARD_PC4303	0x0454	/* pcmcia */
++#define SSB_BOARD_BCM94306MPLNA	0x0457
++#define SSB_BOARD_BCM94306MPH	0x045B
++#define SSB_BOARD_BCM94306PCIV	0x045C
++#define SSB_BOARD_BCM94318MPGH	0x0463
++#define SSB_BOARD_BU4311	0x0464
++#define SSB_BOARD_BCM94311MC	0x0465
++#define SSB_BOARD_BCM94311MCAG	0x0466
++/* 4321 boards */
++#define SSB_BOARD_BU4321	0x046B
++#define SSB_BOARD_BU4321E	0x047C
++#define SSB_BOARD_MP4321	0x046C
++#define SSB_BOARD_CB2_4321	0x046D
++#define SSB_BOARD_CB2_4321_AG	0x0066
++#define SSB_BOARD_MC4321	0x046E
++/* 4325 boards */
++#define SSB_BOARD_BCM94325DEVBU	0x0490
++#define SSB_BOARD_BCM94325BGABU	0x0491
++#define SSB_BOARD_BCM94325SDGWB	0x0492
++#define SSB_BOARD_BCM94325SDGMDL	0x04AA
++#define SSB_BOARD_BCM94325SDGMDL2	0x04C6
++#define SSB_BOARD_BCM94325SDGMDL3	0x04C9
++#define SSB_BOARD_BCM94325SDABGWBA	0x04E1
++/* 4322 boards */
++#define SSB_BOARD_BCM94322MC	0x04A4
++#define SSB_BOARD_BCM94322USB	0x04A8	/* dualband */
++#define SSB_BOARD_BCM94322HM	0x04B0
++#define SSB_BOARD_BCM94322USB2D	0x04Bf	/* single band discrete front end */
++/* 4312 boards */
++#define SSB_BOARD_BU4312	0x048A
++#define SSB_BOARD_BCM4312MCGSG	0x04B5
+ /* chip_package */
+ #define SSB_CHIPPACK_BCM4712S	1	/* Small 200pin 4712 */
+ #define SSB_CHIPPACK_BCM4712M	2	/* Medium 225pin 4712 */
+@@ -432,7 +482,11 @@ struct ssb_bus {
  #ifdef CONFIG_SSB_EMBEDDED
  	/* Lock for GPIO register access. */
  	spinlock_t gpio_lock;
@@ -1147,9 +2406,51 @@
 +
  #endif /* CONFIG_SSB_DRIVER_EXTIF */
  #endif /* LINUX_SSB_EXTIFCORE_H_ */
+--- a/include/linux/ssb/ssb_driver_gige.h
++++ b/include/linux/ssb/ssb_driver_gige.h
+@@ -97,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
+ 	return 0;
+ }
+ 
+-#ifdef CONFIG_BCM47XX
+-#include <asm/mach-bcm47xx/nvram.h>
+ /* Get the device MAC address */
+-static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
+-{
+-	char buf[20];
+-	if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
+-		return;
+-	nvram_parse_macaddr(buf, macaddr);
+-}
+-#else
+-static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
++static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
+ {
++	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
++	if (!dev)
++		return -ENODEV;
++
++	memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
++	return 0;
+ }
+-#endif
+ 
+ extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
+ 					  struct pci_dev *pdev);
+@@ -175,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
+ {
+ 	return 0;
+ }
++static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
++{
++	return -ENODEV;
++}
+ 
+ #endif /* CONFIG_SSB_DRIVER_GIGE */
+ #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
 --- a/include/linux/ssb/ssb_driver_mips.h
 +++ b/include/linux/ssb/ssb_driver_mips.h
-@@ -13,6 +13,12 @@ struct ssb_serial_port {
+@@ -13,6 +13,24 @@ struct ssb_serial_port {
  	unsigned int reg_shift;
  };
  
@@ -1159,10 +2460,22 @@
 +	u32 window;
 +	u32 window_size;
 +};
++
++#ifdef CONFIG_SSB_SFLASH
++struct ssb_sflash {
++	bool present;
++	u32 window;
++	u32 blocksize;
++	u16 numblocks;
++	u32 size;
++
++	void *priv;
++};
++#endif
  
  struct ssb_mipscore {
  	struct ssb_device *dev;
-@@ -20,9 +26,7 @@ struct ssb_mipscore {
+@@ -20,9 +38,10 @@ struct ssb_mipscore {
  	int nr_serial_ports;
  	struct ssb_serial_port serial_ports[4];
  
@@ -1170,12 +2483,35 @@
 -	u32 flash_window;
 -	u32 flash_window_size;
 +	struct ssb_pflash pflash;
++#ifdef CONFIG_SSB_SFLASH
++	struct ssb_sflash sflash;
++#endif
  };
  
  extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
+@@ -41,6 +60,11 @@ void ssb_mipscore_init(struct ssb_mipsco
+ {
+ }
+ 
++static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
++{
++	return 0;
++}
++
+ #endif /* CONFIG_SSB_DRIVER_MIPS */
+ 
+ #endif /* LINUX_SSB_MIPSCORE_H_ */
 --- a/include/linux/ssb/ssb_regs.h
 +++ b/include/linux/ssb/ssb_regs.h
-@@ -289,11 +289,11 @@
+@@ -172,6 +172,7 @@
+ #define SSB_SPROMSIZE_WORDS_R4		220
+ #define SSB_SPROMSIZE_BYTES_R123	(SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
+ #define SSB_SPROMSIZE_BYTES_R4		(SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
++#define SSB_SPROMSIZE_WORDS_R10		230
+ #define SSB_SPROM_BASE1			0x1000
+ #define SSB_SPROM_BASE31		0x0800
+ #define SSB_SPROM_REVISION		0x007E
+@@ -289,11 +290,11 @@
  #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT	5
  #define  SSB_SPROM4_ETHPHY_ET0M		(1<<14)	/* MDIO for enet0 */
  #define  SSB_SPROM4_ETHPHY_ET1M		(1<<15)	/* MDIO for enet1 */
@@ -1192,7 +2528,7 @@
  #define SSB_SPROM4_AGAIN01		0x005E	/* Antenna Gain (in dBm Q5.2) */
  #define  SSB_SPROM4_AGAIN0		0x00FF	/* Antenna 0 */
  #define  SSB_SPROM4_AGAIN0_SHIFT	0
-@@ -485,7 +485,7 @@
+@@ -485,7 +486,7 @@
  #define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT	4
  #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL	0x0020
  #define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT	5
@@ -1235,46 +2571,3 @@
  		break;
  #endif
  	}
---- a/drivers/ssb/pci.c
-+++ b/drivers/ssb/pci.c
-@@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_
- 	return (s8)gain;
- }
- 
-+static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
-+{
-+	SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
-+	SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
-+	SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
-+	SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
-+	SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
-+	SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
-+	SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
-+	SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
-+	SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
-+	SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
-+	     SSB_SPROM2_MAXP_A_LO_SHIFT);
-+}
-+
- static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
- {
- 	int i;
-@@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss
- 	     SSB_SPROM1_ITSSI_A_SHIFT);
- 	SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
- 	SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
--	if (out->revision >= 2)
--		SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
-+
- 	SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
- 	SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
- 
-@@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss
- 	out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
- 						    SSB_SPROM1_AGAIN_A,
- 						    SSB_SPROM1_AGAIN_A_SHIFT);
-+	if (out->revision >= 2)
-+		sprom_extract_r23(out, in);
- }
- 
- /* Revs 4 5 and 8 have partially shared layout */