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author | Hauke Mehrtens <hauke@openwrt.org> | 2016-04-24 19:20:10 +0000 |
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committer | Hauke Mehrtens <hauke@openwrt.org> | 2016-04-24 19:20:10 +0000 |
commit | 2052672908389b65ea68fe319d6a644f5f96ada9 (patch) | |
tree | 662702a584317ed4e27060549725a532ab7c3aba /target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch | |
parent | 8bcff05acc5fcfe8fbc8797cc0156945f3650d09 (diff) | |
download | upstream-2052672908389b65ea68fe319d6a644f5f96ada9.tar.gz upstream-2052672908389b65ea68fe319d6a644f5f96ada9.tar.bz2 upstream-2052672908389b65ea68fe319d6a644f5f96ada9.zip |
CC: kernel: Support for new Archer C7 with gd25q128 chip
Archer C7 V2.0 units from December 2015 onwards ( serials starting 215C
) have changed flash chips to the gd25q128 chip, this is supported in
trunk but not presently in 15.05. I would like stable support for this
version so I've back ported the required fix from trunk and removed a
conflicting patch from bcm53xx I've tested the patch it and I'm able to
install a build of 15.05.1 on a new Archer C7 device with this patch.
Signed-off-by: John Marrett <johnf@zioncluster.ca>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
git-svn-id: svn://svn.openwrt.org/openwrt/branches/chaos_calmer@49220 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch')
-rw-r--r-- | target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch b/target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch new file mode 100644 index 0000000000..4d0403bfd8 --- /dev/null +++ b/target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch @@ -0,0 +1,10 @@ +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -510,6 +510,7 @@ static const struct spi_device_id spi_no + /* GigaDevice */ + { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) }, + { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) }, ++ { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) }, + + /* Intel/Numonyx -- xxxs33b */ + { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, |