linux/2.6.39: R.I.P.

SVN-Revision: 31808

1 files changed, 0 insertions, 2021 deletions

diff --git a/target/linux/generic/patches-2.6.39/020-ssb_update.patch b/target/linux/generic/patches-2.6.39/020-ssb_update.patch
deleted file mode 100644
index e6dec49b05..0000000000
--- a/target/linux/generic/patches-2.6.39/020-ssb_update.patch
+++ /dev/null
@@ -1,2021 +0,0 @@
---- a/drivers/ssb/b43_pci_bridge.c
-+++ b/drivers/ssb/b43_pci_bridge.c
-@@ -5,12 +5,13 @@
-  * because of its small size we include it in the SSB core
-  * instead of creating a standalone module.
-  *
-- * Copyright 2007  Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2007  Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  */
- 
- #include <linux/pci.h>
-+#include <linux/module.h>
- #include <linux/ssb/ssb.h>
- 
- #include "ssb_private.h"
-@@ -28,6 +29,8 @@ static const struct pci_device_id b43_pc
- 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
- 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
- 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
-+	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
-+	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
- 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
- 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
- 	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
---- a/drivers/ssb/driver_chipcommon.c
-+++ b/drivers/ssb/driver_chipcommon.c
-@@ -3,7 +3,7 @@
-  * Broadcom ChipCommon core driver
-  *
-  * Copyright 2005, Broadcom Corporation
-- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  */
-@@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
- 	if (!ccdev)
- 		return;
- 	bus = ccdev->bus;
-+
-+	/* We support SLOW only on 6..9 */
-+	if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
-+		mode = SSB_CLKMODE_DYNAMIC;
-+
-+	if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
-+		return; /* PMU controls clockmode, separated function needed */
-+	SSB_WARN_ON(ccdev->id.revision >= 20);
-+
- 	/* chipcommon cores prior to rev6 don't support dynamic clock control */
- 	if (ccdev->id.revision < 6)
- 		return;
--	/* chipcommon cores rev10 are a whole new ball game */
-+
-+	/* ChipCommon cores rev10+ need testing */
- 	if (ccdev->id.revision >= 10)
- 		return;
-+
- 	if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
- 		return;
- 
- 	switch (mode) {
--	case SSB_CLKMODE_SLOW:
-+	case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
- 		tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
- 		tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
- 		chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
- 		break;
- 	case SSB_CLKMODE_FAST:
--		ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
--		tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
--		tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
--		tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
--		chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-+		if (ccdev->id.revision < 10) {
-+			ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
-+			tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-+			tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-+			tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
-+			chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-+		} else {
-+			chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
-+				(chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
-+				 SSB_CHIPCO_SYSCLKCTL_FORCEHT));
-+			/* udelay(150); TODO: not available in early init */
-+		}
- 		break;
- 	case SSB_CLKMODE_DYNAMIC:
--		tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
--		tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
--		tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
--		tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
--		if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
--			tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
--		chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
--
--		/* for dynamic control, we have to release our xtal_pu "force on" */
--		if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
--			ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
-+		if (ccdev->id.revision < 10) {
-+			tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-+			tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-+			tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
-+			tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
-+			if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
-+			    SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
-+				tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
-+			chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-+
-+			/* For dynamic control, we have to release our xtal_pu
-+			 * "force on" */
-+			if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
-+				ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
-+		} else {
-+			chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
-+				(chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
-+				 ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
-+		}
- 		break;
- 	default:
- 		SSB_WARN_ON(1);
-@@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
- 	if (cc->dev->id.revision >= 11)
- 		cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
- 	ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
-+
-+	if (cc->dev->id.revision >= 20) {
-+		chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
-+		chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
-+	}
-+
- 	ssb_pmu_init(cc);
- 	chipco_powercontrol_init(cc);
- 	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
---- a/drivers/ssb/driver_chipcommon_pmu.c
-+++ b/drivers/ssb/driver_chipcommon_pmu.c
-@@ -2,7 +2,7 @@
-  * Sonics Silicon Backplane
-  * Broadcom ChipCommon Power Management Unit driver
-  *
-- * Copyright 2009, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2009, Michael Buesch <m@bues.ch>
-  * Copyright 2007, Broadcom Corporation
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-@@ -12,6 +12,9 @@
- #include <linux/ssb/ssb_regs.h>
- #include <linux/ssb/ssb_driver_chipcommon.h>
- #include <linux/delay.h>
-+#ifdef CONFIG_BCM47XX
-+#include <asm/mach-bcm47xx/nvram.h>
-+#endif
- 
- #include "ssb_private.h"
- 
-@@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
- 	u32 pmuctl, tmp, pllctl;
- 	unsigned int i;
- 
--	if ((bus->chip_id == 0x5354) && !crystalfreq) {
--		/* The 5354 crystal freq is 25MHz */
--		crystalfreq = 25000;
--	}
- 	if (crystalfreq)
- 		e = pmu0_plltab_find_entry(crystalfreq);
- 	if (!e)
-@@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
- 	u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
- 
- 	if (bus->bustype == SSB_BUSTYPE_SSB) {
--		/* TODO: The user may override the crystal frequency. */
-+#ifdef CONFIG_BCM47XX
-+		char buf[20];
-+		if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
-+			crystalfreq = simple_strtoul(buf, NULL, 0);
-+#endif
- 	}
- 
- 	switch (bus->chip_id) {
-@@ -329,7 +332,11 @@ static void ssb_pmu_pll_init(struct ssb_
- 		ssb_pmu1_pllinit_r0(cc, crystalfreq);
- 		break;
- 	case 0x4328:
-+		ssb_pmu0_pllinit_r0(cc, crystalfreq);
-+		break;
- 	case 0x5354:
-+		if (crystalfreq == 0)
-+			crystalfreq = 25000;
- 		ssb_pmu0_pllinit_r0(cc, crystalfreq);
- 		break;
- 	case 0x4322:
-@@ -417,12 +424,14 @@ static void ssb_pmu_resources_init(struc
- 	u32 min_msk = 0, max_msk = 0;
- 	unsigned int i;
- 	const struct pmu_res_updown_tab_entry *updown_tab = NULL;
--	unsigned int updown_tab_size;
-+	unsigned int updown_tab_size = 0;
- 	const struct pmu_res_depend_tab_entry *depend_tab = NULL;
--	unsigned int depend_tab_size;
-+	unsigned int depend_tab_size = 0;
- 
- 	switch (bus->chip_id) {
- 	case 0x4312:
-+		 min_msk = 0xCBB;
-+		 break;
- 	case 0x4322:
- 		/* We keep the default settings:
- 		 * min_msk = 0xCBB
-@@ -604,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
- 
- EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
- EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
-+
-+u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
-+{
-+	struct ssb_bus *bus = cc->dev->bus;
-+
-+	switch (bus->chip_id) {
-+	case 0x5354:
-+		/* 5354 chip uses a non programmable PLL of frequency 240MHz */
-+		return 240000000;
-+	default:
-+		ssb_printk(KERN_ERR PFX
-+			   "ERROR: PMU cpu clock unknown for device %04X\n",
-+			   bus->chip_id);
-+		return 0;
-+	}
-+}
-+
-+u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
-+{
-+	struct ssb_bus *bus = cc->dev->bus;
-+
-+	switch (bus->chip_id) {
-+	case 0x5354:
-+		return 120000000;
-+	default:
-+		ssb_printk(KERN_ERR PFX
-+			   "ERROR: PMU controlclock unknown for device %04X\n",
-+			   bus->chip_id);
-+		return 0;
-+	}
-+}
---- a/drivers/ssb/driver_extif.c
-+++ b/drivers/ssb/driver_extif.c
-@@ -3,7 +3,7 @@
-  * Broadcom EXTIF core driver
-  *
-  * Copyright 2005, Broadcom Corporation
-- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
-  * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
-  * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
-  *
---- a/drivers/ssb/driver_gige.c
-+++ b/drivers/ssb/driver_gige.c
-@@ -3,7 +3,7 @@
-  * Broadcom Gigabit Ethernet core driver
-  *
-  * Copyright 2008, Broadcom Corporation
-- * Copyright 2008, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2008, Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  */
-@@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
- 	gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
- }
- 
--static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
--				    int reg, int size, u32 *val)
-+static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
-+					      unsigned int devfn, int reg,
-+					      int size, u32 *val)
- {
- 	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
- 	unsigned long flags;
-@@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
- 	return PCIBIOS_SUCCESSFUL;
- }
- 
--static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
--				     int reg, int size, u32 val)
-+static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
-+					       unsigned int devfn, int reg,
-+					       int size, u32 val)
- {
- 	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
- 	unsigned long flags;
-@@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
- 	return PCIBIOS_SUCCESSFUL;
- }
- 
--static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
-+static int __devinit ssb_gige_probe(struct ssb_device *sdev,
-+				    const struct ssb_device_id *id)
- {
- 	struct ssb_gige *dev;
- 	u32 base, tmslow, tmshigh;
---- a/drivers/ssb/driver_mipscore.c
-+++ b/drivers/ssb/driver_mipscore.c
-@@ -3,7 +3,7 @@
-  * Broadcom MIPS core driver
-  *
-  * Copyright 2005, Broadcom Corporation
-- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  */
-@@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
- 	struct ssb_bus *bus = mcore->dev->bus;
- 	u32 pll_type, n, m, rate = 0;
- 
-+	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
-+		return ssb_pmu_get_cpu_clock(&bus->chipco);
-+
- 	if (bus->extif.dev) {
- 		ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
- 	} else if (bus->chipco.dev) {
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -3,7 +3,7 @@
-  * Broadcom PCI-core driver
-  *
-  * Copyright 2005, Broadcom Corporation
-- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  */
-@@ -15,6 +15,11 @@
- 
- #include "ssb_private.h"
- 
-+static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
-+static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
-+static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
-+static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
-+				u8 address, u16 data);
- 
- static inline
- u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
-@@ -69,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
- 	u32 tmp;
- 
- 	/* We do only have one cardbus device behind the bridge. */
--	if (pc->cardbusmode && (dev >= 1))
-+	if (pc->cardbusmode && (dev > 1))
- 		goto out;
- 
- 	if (bus == 0) {
-@@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
- 	return ssb_mips_irq(extpci_core->dev) + 2;
- }
- 
--static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
-+static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
- {
- 	u32 val;
- 
-@@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
- 	register_pci_controller(&ssb_pcicore_controller);
- }
- 
--static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
-+static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
- {
- 	struct ssb_bus *bus = pc->dev->bus;
- 	u16 chipid_top;
-@@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
- }
- #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
- 
-+/**************************************************
-+ * Workarounds.
-+ **************************************************/
-+
-+static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
-+{
-+	u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
-+	if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
-+		tmp &= ~0xF000;
-+		tmp |= (pc->dev->core_index << 12);
-+		pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
-+	}
-+}
-+
-+static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
-+{
-+	return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
-+}
-+
-+static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
-+{
-+	const u8 serdes_pll_device = 0x1D;
-+	const u8 serdes_rx_device = 0x1F;
-+	u16 tmp;
-+
-+	ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
-+			    ssb_pcicore_polarity_workaround(pc));
-+	tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
-+	if (tmp & 0x4000)
-+		ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
-+}
-+
-+static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
-+{
-+	struct ssb_device *pdev = pc->dev;
-+	struct ssb_bus *bus = pdev->bus;
-+	u32 tmp;
-+
-+	tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-+	tmp |= SSB_PCICORE_SBTOPCI_PREF;
-+	tmp |= SSB_PCICORE_SBTOPCI_BURST;
-+	pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
-+
-+	if (pdev->id.revision < 5) {
-+		tmp = ssb_read32(pdev, SSB_IMCFGLO);
-+		tmp &= ~SSB_IMCFGLO_SERTO;
-+		tmp |= 2;
-+		tmp &= ~SSB_IMCFGLO_REQTO;
-+		tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
-+		ssb_write32(pdev, SSB_IMCFGLO, tmp);
-+		ssb_commit_settings(bus);
-+	} else if (pdev->id.revision >= 11) {
-+		tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-+		tmp |= SSB_PCICORE_SBTOPCI_MRM;
-+		pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
-+	}
-+}
-+
-+static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
-+{
-+	u32 tmp;
-+	u8 rev = pc->dev->id.revision;
-+
-+	if (rev == 0 || rev == 1) {
-+		/* TLP Workaround register. */
-+		tmp = ssb_pcie_read(pc, 0x4);
-+		tmp |= 0x8;
-+		ssb_pcie_write(pc, 0x4, tmp);
-+	}
-+	if (rev == 1) {
-+		/* DLLP Link Control register. */
-+		tmp = ssb_pcie_read(pc, 0x100);
-+		tmp |= 0x40;
-+		ssb_pcie_write(pc, 0x100, tmp);
-+	}
-+
-+	if (rev == 0) {
-+		const u8 serdes_rx_device = 0x1F;
-+
-+		ssb_pcie_mdio_write(pc, serdes_rx_device,
-+					2 /* Timer */, 0x8128);
-+		ssb_pcie_mdio_write(pc, serdes_rx_device,
-+					6 /* CDR */, 0x0100);
-+		ssb_pcie_mdio_write(pc, serdes_rx_device,
-+					7 /* CDR BW */, 0x1466);
-+	} else if (rev == 3 || rev == 4 || rev == 5) {
-+		/* TODO: DLLP Power Management Threshold */
-+		ssb_pcicore_serdes_workaround(pc);
-+		/* TODO: ASPM */
-+	} else if (rev == 7) {
-+		/* TODO: No PLL down */
-+	}
-+
-+	if (rev >= 6) {
-+		/* Miscellaneous Configuration Fixup */
-+		tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
-+		if (!(tmp & 0x8000))
-+			pcicore_write16(pc, SSB_PCICORE_SPROM(5),
-+					tmp | 0x8000);
-+	}
-+}
- 
- /**************************************************
-  * Generic and Clientmode operation code.
-  **************************************************/
- 
--static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
-+static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
- {
-+	struct ssb_device *pdev = pc->dev;
-+	struct ssb_bus *bus = pdev->bus;
-+
-+	if (bus->bustype == SSB_BUSTYPE_PCI)
-+		ssb_pcicore_fix_sprom_core_index(pc);
-+
- 	/* Disable PCI interrupts. */
--	ssb_write32(pc->dev, SSB_INTVEC, 0);
-+	ssb_write32(pdev, SSB_INTVEC, 0);
-+
-+	/* Additional PCIe always once-executed workarounds */
-+	if (pc->dev->id.coreid == SSB_DEV_PCIE) {
-+		ssb_pcicore_serdes_workaround(pc);
-+		/* TODO: ASPM */
-+		/* TODO: Clock Request Update */
-+	}
- }
- 
--void ssb_pcicore_init(struct ssb_pcicore *pc)
-+void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
- {
- 	struct ssb_device *dev = pc->dev;
--	struct ssb_bus *bus;
- 
- 	if (!dev)
- 		return;
--	bus = dev->bus;
- 	if (!ssb_device_is_enabled(dev))
- 		ssb_device_enable(dev, 0);
- 
-@@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
- 	pcicore_write32(pc, 0x134, data);
- }
- 
--static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
--				u8 address, u16 data)
-+static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
-+{
-+	const u16 mdio_control = 0x128;
-+	const u16 mdio_data = 0x12C;
-+	u32 v;
-+	int i;
-+
-+	v = (1 << 30); /* Start of Transaction */
-+	v |= (1 << 28); /* Write Transaction */
-+	v |= (1 << 17); /* Turnaround */
-+	v |= (0x1F << 18);
-+	v |= (phy << 4);
-+	pcicore_write32(pc, mdio_data, v);
-+
-+	udelay(10);
-+	for (i = 0; i < 200; i++) {
-+		v = pcicore_read32(pc, mdio_control);
-+		if (v & 0x100 /* Trans complete */)
-+			break;
-+		msleep(1);
-+	}
-+}
-+
-+static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
- {
- 	const u16 mdio_control = 0x128;
- 	const u16 mdio_data = 0x12C;
-+	int max_retries = 10;
-+	u16 ret = 0;
- 	u32 v;
- 	int i;
- 
-@@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
- 	v |= 0x2; /* MDIO Clock Divisor */
- 	pcicore_write32(pc, mdio_control, v);
- 
-+	if (pc->dev->id.revision >= 10) {
-+		max_retries = 200;
-+		ssb_pcie_mdio_set_phy(pc, device);
-+	}
-+
- 	v = (1 << 30); /* Start of Transaction */
--	v |= (1 << 28); /* Write Transaction */
-+	v |= (1 << 29); /* Read Transaction */
- 	v |= (1 << 17); /* Turnaround */
--	v |= (u32)device << 22;
-+	if (pc->dev->id.revision < 10)
-+		v |= (u32)device << 22;
- 	v |= (u32)address << 18;
--	v |= data;
- 	pcicore_write32(pc, mdio_data, v);
- 	/* Wait for the device to complete the transaction */
- 	udelay(10);
--	for (i = 0; i < 10; i++) {
-+	for (i = 0; i < max_retries; i++) {
- 		v = pcicore_read32(pc, mdio_control);
--		if (v & 0x100 /* Trans complete */)
-+		if (v & 0x100 /* Trans complete */) {
-+			udelay(10);
-+			ret = pcicore_read32(pc, mdio_data);
- 			break;
-+		}
- 		msleep(1);
- 	}
- 	pcicore_write32(pc, mdio_control, 0);
-+	return ret;
- }
- 
--static void ssb_broadcast_value(struct ssb_device *dev,
--				u32 address, u32 data)
-+static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
-+				u8 address, u16 data)
- {
--	/* This is used for both, PCI and ChipCommon core, so be careful. */
--	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
--	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
-+	const u16 mdio_control = 0x128;
-+	const u16 mdio_data = 0x12C;
-+	int max_retries = 10;
-+	u32 v;
-+	int i;
- 
--	ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
--	ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
--	ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
--	ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
--}
-+	v = 0x80; /* Enable Preamble Sequence */
-+	v |= 0x2; /* MDIO Clock Divisor */
-+	pcicore_write32(pc, mdio_control, v);
- 
--static void ssb_commit_settings(struct ssb_bus *bus)
--{
--	struct ssb_device *dev;
-+	if (pc->dev->id.revision >= 10) {
-+		max_retries = 200;
-+		ssb_pcie_mdio_set_phy(pc, device);
-+	}
- 
--	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
--	if (WARN_ON(!dev))
--		return;
--	/* This forces an update of the cached registers. */
--	ssb_broadcast_value(dev, 0xFD8, 0);
-+	v = (1 << 30); /* Start of Transaction */
-+	v |= (1 << 28); /* Write Transaction */
-+	v |= (1 << 17); /* Turnaround */
-+	if (pc->dev->id.revision < 10)
-+		v |= (u32)device << 22;
-+	v |= (u32)address << 18;
-+	v |= data;
-+	pcicore_write32(pc, mdio_data, v);
-+	/* Wait for the device to complete the transaction */
-+	udelay(10);
-+	for (i = 0; i < max_retries; i++) {
-+		v = pcicore_read32(pc, mdio_control);
-+		if (v & 0x100 /* Trans complete */)
-+			break;
-+		msleep(1);
-+	}
-+	pcicore_write32(pc, mdio_control, 0);
- }
- 
- int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
-@@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
- 	if (pc->setup_done)
- 		goto out;
- 	if (pdev->id.coreid == SSB_DEV_PCI) {
--		tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
--		tmp |= SSB_PCICORE_SBTOPCI_PREF;
--		tmp |= SSB_PCICORE_SBTOPCI_BURST;
--		pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
--
--		if (pdev->id.revision < 5) {
--			tmp = ssb_read32(pdev, SSB_IMCFGLO);
--			tmp &= ~SSB_IMCFGLO_SERTO;
--			tmp |= 2;
--			tmp &= ~SSB_IMCFGLO_REQTO;
--			tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
--			ssb_write32(pdev, SSB_IMCFGLO, tmp);
--			ssb_commit_settings(bus);
--		} else if (pdev->id.revision >= 11) {
--			tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
--			tmp |= SSB_PCICORE_SBTOPCI_MRM;
--			pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
--		}
-+		ssb_pcicore_pci_setup_workarounds(pc);
- 	} else {
- 		WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
--		//TODO: Better make defines for all these magic PCIE values.
--		if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
--			/* TLP Workaround register. */
--			tmp = ssb_pcie_read(pc, 0x4);
--			tmp |= 0x8;
--			ssb_pcie_write(pc, 0x4, tmp);
--		}
--		if (pdev->id.revision == 0) {
--			const u8 serdes_rx_device = 0x1F;
--
--			ssb_pcie_mdio_write(pc, serdes_rx_device,
--					    2 /* Timer */, 0x8128);
--			ssb_pcie_mdio_write(pc, serdes_rx_device,
--					    6 /* CDR */, 0x0100);
--			ssb_pcie_mdio_write(pc, serdes_rx_device,
--					    7 /* CDR BW */, 0x1466);
--		} else if (pdev->id.revision == 1) {
--			/* DLLP Link Control register. */
--			tmp = ssb_pcie_read(pc, 0x100);
--			tmp |= 0x40;
--			ssb_pcie_write(pc, 0x100, tmp);
--		}
-+		ssb_pcicore_pcie_setup_workarounds(pc);
- 	}
- 	pc->setup_done = 1;
- out:
---- a/drivers/ssb/embedded.c
-+++ b/drivers/ssb/embedded.c
-@@ -3,7 +3,7 @@
-  * Embedded systems support code
-  *
-  * Copyright 2005-2008, Broadcom Corporation
-- * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2006-2008, Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  */
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -3,7 +3,7 @@
-  * Subsystem core
-  *
-  * Copyright 2005, Broadcom Corporation
-- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  */
-@@ -12,6 +12,7 @@
- 
- #include <linux/delay.h>
- #include <linux/io.h>
-+#include <linux/module.h>
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_regs.h>
- #include <linux/ssb/ssb_driver_gige.h>
-@@ -139,19 +140,6 @@ static void ssb_device_put(struct ssb_de
- 		put_device(dev->dev);
- }
- 
--static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
--{
--	if (drv)
--		get_driver(&drv->drv);
--	return drv;
--}
--
--static inline void ssb_driver_put(struct ssb_driver *drv)
--{
--	if (drv)
--		put_driver(&drv->drv);
--}
--
- static int ssb_device_resume(struct device *dev)
- {
- 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-@@ -249,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
- 			ssb_device_put(sdev);
- 			continue;
- 		}
--		sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
--		if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
--			ssb_device_put(sdev);
-+		sdrv = drv_to_ssb_drv(sdev->dev->driver);
-+		if (SSB_WARN_ON(!sdrv->remove))
- 			continue;
--		}
- 		sdrv->remove(sdev);
- 		ctx->device_frozen[i] = 1;
- 	}
-@@ -292,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
- 				   dev_name(sdev->dev));
- 			result = err;
- 		}
--		ssb_driver_put(sdrv);
- 		ssb_device_put(sdev);
- 	}
- 
-@@ -557,7 +542,7 @@ error:
- }
- 
- /* Needs ssb_buses_lock() */
--static int ssb_attach_queued_buses(void)
-+static int __devinit ssb_attach_queued_buses(void)
- {
- 	struct ssb_bus *bus, *n;
- 	int err = 0;
-@@ -768,9 +753,9 @@ out:
- 	return err;
- }
- 
--static int ssb_bus_register(struct ssb_bus *bus,
--			    ssb_invariants_func_t get_invariants,
--			    unsigned long baseaddr)
-+static int __devinit ssb_bus_register(struct ssb_bus *bus,
-+				      ssb_invariants_func_t get_invariants,
-+				      unsigned long baseaddr)
- {
- 	int err;
- 
-@@ -851,8 +836,8 @@ err_disable_xtal:
- }
- 
- #ifdef CONFIG_SSB_PCIHOST
--int ssb_bus_pcibus_register(struct ssb_bus *bus,
--			    struct pci_dev *host_pci)
-+int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
-+				      struct pci_dev *host_pci)
- {
- 	int err;
- 
-@@ -875,9 +860,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
- #endif /* CONFIG_SSB_PCIHOST */
- 
- #ifdef CONFIG_SSB_PCMCIAHOST
--int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
--			       struct pcmcia_device *pcmcia_dev,
--			       unsigned long baseaddr)
-+int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
-+					 struct pcmcia_device *pcmcia_dev,
-+					 unsigned long baseaddr)
- {
- 	int err;
- 
-@@ -897,8 +882,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
- #endif /* CONFIG_SSB_PCMCIAHOST */
- 
- #ifdef CONFIG_SSB_SDIOHOST
--int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
--			     unsigned int quirks)
-+int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
-+				       struct sdio_func *func,
-+				       unsigned int quirks)
- {
- 	int err;
- 
-@@ -918,9 +904,9 @@ int ssb_bus_sdiobus_register(struct ssb_
- EXPORT_SYMBOL(ssb_bus_sdiobus_register);
- #endif /* CONFIG_SSB_PCMCIAHOST */
- 
--int ssb_bus_ssbbus_register(struct ssb_bus *bus,
--			    unsigned long baseaddr,
--			    ssb_invariants_func_t get_invariants)
-+int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
-+				      unsigned long baseaddr,
-+				      ssb_invariants_func_t get_invariants)
- {
- 	int err;
- 
-@@ -1001,8 +987,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
- 	switch (plltype) {
- 	case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
- 		if (m & SSB_CHIPCO_CLK_T6_MMASK)
--			return SSB_CHIPCO_CLK_T6_M0;
--		return SSB_CHIPCO_CLK_T6_M1;
-+			return SSB_CHIPCO_CLK_T6_M1;
-+		return SSB_CHIPCO_CLK_T6_M0;
- 	case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
- 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
- 	case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
-@@ -1092,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
- 	u32 plltype;
- 	u32 clkctl_n, clkctl_m;
- 
-+	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
-+		return ssb_pmu_get_controlclock(&bus->chipco);
-+
- 	if (ssb_extif_available(&bus->extif))
- 		ssb_extif_get_clockcontrol(&bus->extif, &plltype,
- 					   &clkctl_n, &clkctl_m);
-@@ -1117,23 +1106,22 @@ static u32 ssb_tmslow_reject_bitmask(str
- {
- 	u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
- 
--	/* The REJECT bit changed position in TMSLOW between
--	 * Backplane revisions. */
-+	/* The REJECT bit seems to be different for Backplane rev 2.3 */
- 	switch (rev) {
- 	case SSB_IDLOW_SSBREV_22:
--		return SSB_TMSLOW_REJECT_22;
-+	case SSB_IDLOW_SSBREV_24:
-+	case SSB_IDLOW_SSBREV_26:
-+		return SSB_TMSLOW_REJECT;
- 	case SSB_IDLOW_SSBREV_23:
- 		return SSB_TMSLOW_REJECT_23;
--	case SSB_IDLOW_SSBREV_24:     /* TODO - find the proper REJECT bits */
--	case SSB_IDLOW_SSBREV_25:     /* same here */
--	case SSB_IDLOW_SSBREV_26:     /* same here */
-+	case SSB_IDLOW_SSBREV_25:     /* TODO - find the proper REJECT bit */
- 	case SSB_IDLOW_SSBREV_27:     /* same here */
--		return SSB_TMSLOW_REJECT_23;	/* this is a guess */
-+		return SSB_TMSLOW_REJECT;	/* this is a guess */
- 	default:
- 		printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
- 		WARN_ON(1);
- 	}
--	return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
-+	return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
- }
- 
- int ssb_device_is_enabled(struct ssb_device *dev)
-@@ -1260,13 +1248,34 @@ void ssb_device_disable(struct ssb_devic
- }
- EXPORT_SYMBOL(ssb_device_disable);
- 
-+/* Some chipsets need routing known for PCIe and 64-bit DMA */
-+static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
-+{
-+	u16 chip_id = dev->bus->chip_id;
-+
-+	if (dev->id.coreid == SSB_DEV_80211) {
-+		return (chip_id == 0x4322 || chip_id == 43221 ||
-+			chip_id == 43231 || chip_id == 43222);
-+	}
-+
-+	return 0;
-+}
-+
- u32 ssb_dma_translation(struct ssb_device *dev)
- {
- 	switch (dev->bus->bustype) {
- 	case SSB_BUSTYPE_SSB:
- 		return 0;
- 	case SSB_BUSTYPE_PCI:
--		return SSB_PCI_DMA;
-+		if (pci_is_pcie(dev->bus->host_pci) &&
-+		    ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
-+			return SSB_PCIE_DMA_H32;
-+		} else {
-+			if (ssb_dma_translation_special_bit(dev))
-+				return SSB_PCIE_DMA_H32;
-+			else
-+				return SSB_PCI_DMA;
-+		}
- 	default:
- 		__ssb_dma_not_implemented(dev);
- 	}
-@@ -1309,20 +1318,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
- 
- int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
- {
--	struct ssb_chipcommon *cc;
- 	int err;
- 	enum ssb_clkmode mode;
- 
- 	err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
- 	if (err)
- 		goto error;
--	cc = &bus->chipco;
--	mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
--	ssb_chipco_set_clockmode(cc, mode);
- 
- #ifdef CONFIG_SSB_DEBUG
- 	bus->powered_up = 1;
- #endif
-+
-+	mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
-+	ssb_chipco_set_clockmode(&bus->chipco, mode);
-+
- 	return 0;
- error:
- 	ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
-@@ -1330,6 +1339,37 @@ error:
- }
- EXPORT_SYMBOL(ssb_bus_powerup);
- 
-+static void ssb_broadcast_value(struct ssb_device *dev,
-+				u32 address, u32 data)
-+{
-+#ifdef CONFIG_SSB_DRIVER_PCICORE
-+	/* This is used for both, PCI and ChipCommon core, so be careful. */
-+	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
-+	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
-+#endif
-+
-+	ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
-+	ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
-+	ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
-+	ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
-+}
-+
-+void ssb_commit_settings(struct ssb_bus *bus)
-+{
-+	struct ssb_device *dev;
-+
-+#ifdef CONFIG_SSB_DRIVER_PCICORE
-+	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
-+#else
-+	dev = bus->chipco.dev;
-+#endif
-+	if (WARN_ON(!dev))
-+		return;
-+	/* This forces an update of the cached registers. */
-+	ssb_broadcast_value(dev, 0xFD8, 0);
-+}
-+EXPORT_SYMBOL(ssb_commit_settings);
-+
- u32 ssb_admatch_base(u32 adm)
- {
- 	u32 base = 0;
---- a/drivers/ssb/pci.c
-+++ b/drivers/ssb/pci.c
-@@ -1,7 +1,7 @@
- /*
-  * Sonics Silicon Backplane PCI-Hostbus related functions.
-  *
-- * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
-+ * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
-  * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
-  * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
-  * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
-@@ -178,6 +178,18 @@ err_pci:
- #define SPEX(_outvar, _offset, _mask, _shift) \
- 	SPEX16(_outvar, _offset, _mask, _shift)
- 
-+#define SPEX_ARRAY8(_field, _offset, _mask, _shift)	\
-+	do {	\
-+		SPEX(_field[0], _offset +  0, _mask, _shift);	\
-+		SPEX(_field[1], _offset +  2, _mask, _shift);	\
-+		SPEX(_field[2], _offset +  4, _mask, _shift);	\
-+		SPEX(_field[3], _offset +  6, _mask, _shift);	\
-+		SPEX(_field[4], _offset +  8, _mask, _shift);	\
-+		SPEX(_field[5], _offset + 10, _mask, _shift);	\
-+		SPEX(_field[6], _offset + 12, _mask, _shift);	\
-+		SPEX(_field[7], _offset + 14, _mask, _shift);	\
-+	} while (0)
-+
- 
- static inline u8 ssb_crc8(u8 crc, u8 data)
- {
-@@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
- {
- 	int i;
- 	u16 v;
--	s8 gain;
- 	u16 loc[3];
- 
- 	if (out->revision == 3)			/* rev 3 moved MAC */
-@@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
- 	SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
- 	SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
- 	SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
--	SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
--	     SSB_SPROM1_BINF_CCODE_SHIFT);
-+	if (out->revision == 1)
-+		SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
-+		     SSB_SPROM1_BINF_CCODE_SHIFT);
- 	SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
- 	     SSB_SPROM1_BINF_ANTA_SHIFT);
- 	SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
-@@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
- 	SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
- 	if (out->revision >= 2)
- 		SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
-+	SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
-+	SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
- 
- 	/* Extract the antenna gain values. */
--	gain = r123_extract_antgain(out->revision, in,
--				    SSB_SPROM1_AGAIN_BG,
--				    SSB_SPROM1_AGAIN_BG_SHIFT);
--	out->antenna_gain.ghz24.a0 = gain;
--	out->antenna_gain.ghz24.a1 = gain;
--	out->antenna_gain.ghz24.a2 = gain;
--	out->antenna_gain.ghz24.a3 = gain;
--	gain = r123_extract_antgain(out->revision, in,
--				    SSB_SPROM1_AGAIN_A,
--				    SSB_SPROM1_AGAIN_A_SHIFT);
--	out->antenna_gain.ghz5.a0 = gain;
--	out->antenna_gain.ghz5.a1 = gain;
--	out->antenna_gain.ghz5.a2 = gain;
--	out->antenna_gain.ghz5.a3 = gain;
-+	out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
-+						    SSB_SPROM1_AGAIN_BG,
-+						    SSB_SPROM1_AGAIN_BG_SHIFT);
-+	out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
-+						    SSB_SPROM1_AGAIN_A,
-+						    SSB_SPROM1_AGAIN_A_SHIFT);
- }
- 
- /* Revs 4 5 and 8 have partially shared layout */
-@@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
- 	SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
- 	SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
- 	     SSB_SPROM4_ETHPHY_ET1A_SHIFT);
-+	SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
- 	if (out->revision == 4) {
--		SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
-+		SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
-+		SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
- 		SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
- 		SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
- 		SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
- 		SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
- 	} else {
--		SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
-+		SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
-+		SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
- 		SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
- 		SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
- 		SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
-@@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
- 	}
- 
- 	/* Extract the antenna gain values. */
--	SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
-+	SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
- 	     SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
--	SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
-+	SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
- 	     SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
--	SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
-+	SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
- 	     SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
--	SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
-+	SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
- 	     SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
--	memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
--	       sizeof(out->antenna_gain.ghz5));
- 
- 	sprom_extract_r458(out, in);
- 
-@@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
- static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
- {
- 	int i;
--	u16 v;
-+	u16 v, o;
-+	u16 pwr_info_offset[] = {
-+		SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
-+		SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
-+	};
-+	BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
-+			ARRAY_SIZE(out->core_pwr_info));
- 
- 	/* extract the MAC address */
- 	for (i = 0; i < 3; i++) {
- 		v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
- 		*(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
- 	}
--	SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
-+	SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
-+	SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
-+	SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
- 	SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
- 	SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
- 	SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
-@@ -596,17 +611,127 @@ static void sprom_extract_r8(struct ssb_
- 	SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
- 
- 	/* Extract the antenna gain values. */
--	SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
-+	SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
- 	     SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
--	SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
-+	SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
- 	     SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
--	SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
-+	SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
- 	     SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
--	SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
-+	SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
- 	     SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
--	memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
--	       sizeof(out->antenna_gain.ghz5));
- 
-+	/* Extract cores power info info */
-+	for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
-+		o = pwr_info_offset[i];
-+		SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
-+			SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
-+		SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
-+			SSB_SPROM8_2G_MAXP, 0);
-+
-+		SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
-+
-+		SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
-+			SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
-+		SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
-+			SSB_SPROM8_5G_MAXP, 0);
-+		SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
-+			SSB_SPROM8_5GH_MAXP, 0);
-+		SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
-+			SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
-+
-+		SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
-+		SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
-+	}
-+
-+	/* Extract FEM info */
-+	SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
-+		SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
-+	SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
-+		SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
-+	SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
-+		SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
-+	SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
-+		SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
-+	SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
-+		SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
-+
-+	SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
-+		SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
-+	SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
-+		SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
-+	SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
-+		SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
-+	SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
-+		SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
-+	SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
-+		SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
-+
-+	SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
-+	     SSB_SPROM8_LEDDC_ON_SHIFT);
-+	SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
-+	     SSB_SPROM8_LEDDC_OFF_SHIFT);
-+
-+	SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
-+	     SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
-+	SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
-+	     SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
-+	SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
-+	     SSB_SPROM8_TXRXC_SWITCH_SHIFT);
-+
-+	SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
-+
-+	SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
-+	SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
-+	SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
-+	SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
-+
-+	SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
-+	     SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
-+	SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
-+	     SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
-+	SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
-+	     SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
-+	     SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
-+	SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
-+	     SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
-+	SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
-+	     SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
-+	     SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
-+	SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
-+	     SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
-+	     SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
-+	SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
-+	     SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
-+	     SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
-+	SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
-+	     SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
-+
-+	SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
-+	SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
-+	SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
-+	SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
-+
-+	SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
-+	     SSB_SPROM8_THERMAL_TRESH_SHIFT);
-+	SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
-+	     SSB_SPROM8_THERMAL_OFFSET_SHIFT);
-+	SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
-+	     SSB_SPROM8_TEMPDELTA_PHYCAL,
-+	     SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
-+	SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
-+	     SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
-+	SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
-+	     SSB_SPROM8_TEMPDELTA_HYSTERESIS,
-+	     SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
- 	sprom_extract_r458(out, in);
- 
- 	/* TODO - get remaining rev 8 stuff needed */
-@@ -662,7 +787,6 @@ static int sprom_extract(struct ssb_bus
- static int ssb_pci_sprom_get(struct ssb_bus *bus,
- 			     struct ssb_sprom *sprom)
- {
--	const struct ssb_sprom *fallback;
- 	int err;
- 	u16 *buf;
- 
-@@ -707,10 +831,17 @@ static int ssb_pci_sprom_get(struct ssb_
- 		if (err) {
- 			/* All CRC attempts failed.
- 			 * Maybe there is no SPROM on the device?
--			 * If we have a fallback, use that. */
--			fallback = ssb_get_fallback_sprom();
--			if (fallback) {
--				memcpy(sprom, fallback, sizeof(*sprom));
-+			 * Now we ask the arch code if there is some sprom
-+			 * available for this device in some other storage */
-+			err = ssb_fill_sprom_with_fallback(bus, sprom);
-+			if (err) {
-+				ssb_printk(KERN_WARNING PFX "WARNING: Using"
-+					   " fallback SPROM failed (err %d)\n",
-+					   err);
-+			} else {
-+				ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
-+					    " revision %d provided by"
-+					    " platform.\n", sprom->revision);
- 				err = 0;
- 				goto out_free;
- 			}
-@@ -728,12 +859,8 @@ out_free:
- static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
- 				  struct ssb_boardinfo *bi)
- {
--	pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
--			     &bi->vendor);
--	pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
--			     &bi->type);
--	pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
--			     &bi->rev);
-+	bi->vendor = bus->host_pci->subsystem_vendor;
-+	bi->type = bus->host_pci->subsystem_device;
- }
- 
- int ssb_pci_get_invariants(struct ssb_bus *bus,
---- a/drivers/ssb/pcihost_wrapper.c
-+++ b/drivers/ssb/pcihost_wrapper.c
-@@ -6,7 +6,7 @@
-  * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
-  * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
-  * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
-- * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
-+ * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  */
-@@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
- # define ssb_pcihost_resume	NULL
- #endif /* CONFIG_PM */
- 
--static int ssb_pcihost_probe(struct pci_dev *dev,
--			     const struct pci_device_id *id)
-+static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
-+				       const struct pci_device_id *id)
- {
- 	struct ssb_bus *ssb;
- 	int err = -ENOMEM;
-@@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
- 	pci_set_drvdata(dev, NULL);
- }
- 
--int ssb_pcihost_register(struct pci_driver *driver)
-+int __devinit ssb_pcihost_register(struct pci_driver *driver)
- {
- 	driver->probe = ssb_pcihost_probe;
- 	driver->remove = ssb_pcihost_remove;
---- a/drivers/ssb/pcmcia.c
-+++ b/drivers/ssb/pcmcia.c
-@@ -3,7 +3,7 @@
-  * PCMCIA-Hostbus related functions
-  *
-  * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
-- * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2007-2008 Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  */
-@@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
- 	case SSB_PCMCIA_CIS_ANTGAIN:
- 		GOTO_ERROR_ON(tuple->TupleDataLen != 2,
- 			"antg tpl size");
--		sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
--		sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
--		sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
--		sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
--		sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
--		sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
--		sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
--		sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
-+		sprom->antenna_gain.a0 = tuple->TupleData[1];
-+		sprom->antenna_gain.a1 = tuple->TupleData[1];
-+		sprom->antenna_gain.a2 = tuple->TupleData[1];
-+		sprom->antenna_gain.a3 = tuple->TupleData[1];
- 		break;
- 	case SSB_PCMCIA_CIS_BFLAGS:
- 		GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
---- a/drivers/ssb/scan.c
-+++ b/drivers/ssb/scan.c
-@@ -2,7 +2,7 @@
-  * Sonics Silicon Backplane
-  * Bus scanning
-  *
-- * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
-+ * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
-  * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
-  * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
-  * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
-@@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
- #ifdef CONFIG_SSB_PCIHOST
- 	if (bus->bustype == SSB_BUSTYPE_PCI) {
- 		if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
--		    bus->host_pci->device == 0x4324)
-+		    ((bus->host_pci->device == 0x4313) ||
-+		     (bus->host_pci->device == 0x431A) ||
-+		     (bus->host_pci->device == 0x4321) ||
-+		     (bus->host_pci->device == 0x4324)))
- 			return 1;
- 	}
- #endif /* CONFIG_SSB_PCIHOST */
-@@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
- 	} else {
- 		if (bus->bustype == SSB_BUSTYPE_PCI) {
- 			bus->chip_id = pcidev_to_chipid(bus->host_pci);
--			pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
--					     &bus->chip_rev);
-+			bus->chip_rev = bus->host_pci->revision;
- 			bus->chip_package = 0;
- 		} else {
- 			bus->chip_id = 0x4710;
-@@ -316,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
- 			bus->chip_package = 0;
- 		}
- 	}
-+	ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
-+		   "package 0x%02X\n", bus->chip_id, bus->chip_rev,
-+		   bus->chip_package);
- 	if (!bus->nr_devices)
- 		bus->nr_devices = chipid_to_nrcores(bus->chip_id);
- 	if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
---- a/drivers/ssb/sdio.c
-+++ b/drivers/ssb/sdio.c
-@@ -6,7 +6,7 @@
-  *
-  * Based on drivers/ssb/pcmcia.c
-  * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
-- * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2007-2008 Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GNU/GPL. See COPYING for details.
-  *
-@@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
- 			case SSB_SDIO_CIS_ANTGAIN:
- 				GOTO_ERROR_ON(tuple->size != 2,
- 					      "antg tpl size");
--				sprom->antenna_gain.ghz24.a0 = tuple->data[1];
--				sprom->antenna_gain.ghz24.a1 = tuple->data[1];
--				sprom->antenna_gain.ghz24.a2 = tuple->data[1];
--				sprom->antenna_gain.ghz24.a3 = tuple->data[1];
--				sprom->antenna_gain.ghz5.a0 = tuple->data[1];
--				sprom->antenna_gain.ghz5.a1 = tuple->data[1];
--				sprom->antenna_gain.ghz5.a2 = tuple->data[1];
--				sprom->antenna_gain.ghz5.a3 = tuple->data[1];
-+				sprom->antenna_gain.a0 = tuple->data[1];
-+				sprom->antenna_gain.a1 = tuple->data[1];
-+				sprom->antenna_gain.a2 = tuple->data[1];
-+				sprom->antenna_gain.a3 = tuple->data[1];
- 				break;
- 			case SSB_SDIO_CIS_BFLAGS:
- 				GOTO_ERROR_ON((tuple->size != 3) &&
---- a/drivers/ssb/sprom.c
-+++ b/drivers/ssb/sprom.c
-@@ -2,7 +2,7 @@
-  * Sonics Silicon Backplane
-  * Common SPROM support routines
-  *
-- * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
-+ * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
-  * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
-  * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
-  * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
-@@ -17,7 +17,7 @@
- #include <linux/slab.h>
- 
- 
--static const struct ssb_sprom *fallback_sprom;
-+static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
- 
- 
- static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
-@@ -145,36 +145,43 @@ out:
- }
- 
- /**
-- * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
-+ * ssb_arch_register_fallback_sprom - Registers a method providing a
-+ * fallback SPROM if no SPROM is found.
-  *
-- * @sprom: The SPROM data structure to register.
-+ * @sprom_callback: The callback function.
-  *
-- * With this function the architecture implementation may register a fallback
-- * SPROM data structure. The fallback is only used for PCI based SSB devices,
-- * where no valid SPROM can be found in the shadow registers.
-+ * With this function the architecture implementation may register a
-+ * callback handler which fills the SPROM data structure. The fallback is
-+ * only used for PCI based SSB devices, where no valid SPROM can be found
-+ * in the shadow registers.
-+ *
-+ * This function is useful for weird architectures that have a half-assed
-+ * SSB device hardwired to their PCI bus.
-+ *
-+ * Note that it does only work with PCI attached SSB devices. PCMCIA
-+ * devices currently don't use this fallback.
-+ * Architectures must provide the SPROM for native SSB devices anyway, so
-+ * the fallback also isn't used for native devices.
-  *
-- * This function is useful for weird architectures that have a half-assed SSB device
-- * hardwired to their PCI bus.
-- *
-- * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
-- * don't use this fallback.
-- * Architectures must provide the SPROM for native SSB devices anyway,
-- * so the fallback also isn't used for native devices.
-- *
-- * This function is available for architecture code, only. So it is not exported.
-+ * This function is available for architecture code, only. So it is not
-+ * exported.
-  */
--int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
-+int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
-+				     struct ssb_sprom *out))
- {
--	if (fallback_sprom)
-+	if (get_fallback_sprom)
- 		return -EEXIST;
--	fallback_sprom = sprom;
-+	get_fallback_sprom = sprom_callback;
- 
- 	return 0;
- }
- 
--const struct ssb_sprom *ssb_get_fallback_sprom(void)
-+int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
- {
--	return fallback_sprom;
-+	if (!get_fallback_sprom)
-+		return -ENOENT;
-+
-+	return get_fallback_sprom(bus, out);
- }
- 
- /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
---- a/drivers/ssb/ssb_private.h
-+++ b/drivers/ssb/ssb_private.h
-@@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
- 			     const char *buf, size_t count,
- 			     int (*sprom_check_crc)(const u16 *sprom, size_t size),
- 			     int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
--extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
-+extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
-+					struct ssb_sprom *out);
- 
- 
- /* core.c */
-@@ -206,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
- }
- #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
- 
-+/* driver_chipcommon_pmu.c */
-+extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
-+extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
-+
- #endif /* LINUX_SSB_PRIVATE_H_ */
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -16,6 +16,12 @@ struct pcmcia_device;
- struct ssb_bus;
- struct ssb_driver;
- 
-+struct ssb_sprom_core_pwr_info {
-+	u8 itssi_2g, itssi_5g;
-+	u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
-+	u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
-+};
-+
- struct ssb_sprom {
- 	u8 revision;
- 	u8 il0mac[6];		/* MAC address for 802.11b/g */
-@@ -25,8 +31,13 @@ struct ssb_sprom {
- 	u8 et1phyaddr;		/* MII address for enet1 */
- 	u8 et0mdcport;		/* MDIO for enet0 */
- 	u8 et1mdcport;		/* MDIO for enet1 */
--	u8 board_rev;		/* Board revision number from SPROM. */
-+	u16 board_rev;		/* Board revision number from SPROM. */
-+	u16 board_num;		/* Board number from SPROM. */
-+	u16 board_type;		/* Board type from SPROM. */
- 	u8 country_code;	/* Country Code */
-+	char alpha2[2];		/* Country Code as two chars like EU or US */
-+	u8 leddc_on_time;	/* LED Powersave Duty Cycle On Count */
-+	u8 leddc_off_time;	/* LED Powersave Duty Cycle Off Count */
- 	u8 ant_available_a;	/* 2GHz antenna available bits (up to 4) */
- 	u8 ant_available_bg;	/* 5GHz antenna available bits (up to 4) */
- 	u16 pa0b0;
-@@ -45,10 +56,10 @@ struct ssb_sprom {
- 	u8 gpio1;		/* GPIO pin 1 */
- 	u8 gpio2;		/* GPIO pin 2 */
- 	u8 gpio3;		/* GPIO pin 3 */
--	u16 maxpwr_bg;		/* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
--	u16 maxpwr_al;		/* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
--	u16 maxpwr_a;		/* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
--	u16 maxpwr_ah;		/* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
-+	u8 maxpwr_bg;		/* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
-+	u8 maxpwr_al;		/* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
-+	u8 maxpwr_a;		/* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
-+	u8 maxpwr_ah;		/* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
- 	u8 itssi_a;		/* Idle TSSI Target for A-PHY */
- 	u8 itssi_bg;		/* Idle TSSI Target for B/G-PHY */
- 	u8 tri2g;		/* 2.4GHz TX isolation */
-@@ -59,8 +70,8 @@ struct ssb_sprom {
- 	u8 txpid5gl[4];		/* 4.9 - 5.1GHz TX power index */
- 	u8 txpid5g[4];		/* 5.1 - 5.5GHz TX power index */
- 	u8 txpid5gh[4];		/* 5.5 - ...GHz TX power index */
--	u8 rxpo2g;		/* 2GHz RX power offset */
--	u8 rxpo5g;		/* 5GHz RX power offset */
-+	s8 rxpo2g;		/* 2GHz RX power offset */
-+	s8 rxpo5g;		/* 5GHz RX power offset */
- 	u8 rssisav2g;		/* 2GHz RSSI params */
- 	u8 rssismc2g;
- 	u8 rssismf2g;
-@@ -80,26 +91,103 @@ struct ssb_sprom {
- 	u16 boardflags2_hi;	/* Board flags (bits 48-63) */
- 	/* TODO store board flags in a single u64 */
- 
-+	struct ssb_sprom_core_pwr_info core_pwr_info[4];
-+
- 	/* Antenna gain values for up to 4 antennas
- 	 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
- 	 * loss in the connectors is bigger than the gain. */
- 	struct {
--		struct {
--			s8 a0, a1, a2, a3;
--		} ghz24;	/* 2.4GHz band */
--		struct {
--			s8 a0, a1, a2, a3;
--		} ghz5;		/* 5GHz band */
-+		s8 a0, a1, a2, a3;
- 	} antenna_gain;
- 
--	/* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
-+	struct {
-+		struct {
-+			u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
-+		} ghz2;
-+		struct {
-+			u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
-+		} ghz5;
-+	} fem;
-+
-+	u16 mcs2gpo[8];
-+	u16 mcs5gpo[8];
-+	u16 mcs5glpo[8];
-+	u16 mcs5ghpo[8];
-+	u8 opo;
-+
-+	u8 rxgainerr2ga[3];
-+	u8 rxgainerr5gla[3];
-+	u8 rxgainerr5gma[3];
-+	u8 rxgainerr5gha[3];
-+	u8 rxgainerr5gua[3];
-+
-+	u8 noiselvl2ga[3];
-+	u8 noiselvl5gla[3];
-+	u8 noiselvl5gma[3];
-+	u8 noiselvl5gha[3];
-+	u8 noiselvl5gua[3];
-+
-+	u8 regrev;
-+	u8 txchain;
-+	u8 rxchain;
-+	u8 antswitch;
-+	u16 cddpo;
-+	u16 stbcpo;
-+	u16 bw40po;
-+	u16 bwduppo;
-+
-+	u8 tempthresh;
-+	u8 tempoffset;
-+	u16 rawtempsense;
-+	u8 measpower;
-+	u8 tempsense_slope;
-+	u8 tempcorrx;
-+	u8 tempsense_option;
-+	u8 freqoffset_corr;
-+	u8 iqcal_swp_dis;
-+	u8 hw_iqcal_en;
-+	u8 elna2g;
-+	u8 elna5g;
-+	u8 phycal_tempdelta;
-+	u8 temps_period;
-+	u8 temps_hysteresis;
-+	u8 measpower1;
-+	u8 measpower2;
-+	u8 pcieingress_war;
-+
-+	/* power per rate from sromrev 9 */
-+	u16 cckbw202gpo;
-+	u16 cckbw20ul2gpo;
-+	u32 legofdmbw202gpo;
-+	u32 legofdmbw20ul2gpo;
-+	u32 legofdmbw205glpo;
-+	u32 legofdmbw20ul5glpo;
-+	u32 legofdmbw205gmpo;
-+	u32 legofdmbw20ul5gmpo;
-+	u32 legofdmbw205ghpo;
-+	u32 legofdmbw20ul5ghpo;
-+	u32 mcsbw202gpo;
-+	u32 mcsbw20ul2gpo;
-+	u32 mcsbw402gpo;
-+	u32 mcsbw205glpo;
-+	u32 mcsbw20ul5glpo;
-+	u32 mcsbw405glpo;
-+	u32 mcsbw205gmpo;
-+	u32 mcsbw20ul5gmpo;
-+	u32 mcsbw405gmpo;
-+	u32 mcsbw205ghpo;
-+	u32 mcsbw20ul5ghpo;
-+	u32 mcsbw405ghpo;
-+	u16 mcs32po;
-+	u16 legofdm40duppo;
-+	u8 sar2g;
-+	u8 sar5g;
- };
- 
- /* Information about the PCB the circuitry is soldered on. */
- struct ssb_boardinfo {
- 	u16 vendor;
- 	u16 type;
--	u16 rev;
- };
- 
- 
-@@ -229,10 +317,9 @@ struct ssb_driver {
- #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
- 
- extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
--static inline int ssb_driver_register(struct ssb_driver *drv)
--{
--	return __ssb_driver_register(drv, THIS_MODULE);
--}
-+#define ssb_driver_register(drv) \
-+	__ssb_driver_register(drv, THIS_MODULE)
-+
- extern void ssb_driver_unregister(struct ssb_driver *drv);
- 
- 
-@@ -308,7 +395,7 @@ struct ssb_bus {
- 
- 	/* ID information about the Chip. */
- 	u16 chip_id;
--	u16 chip_rev;
-+	u8 chip_rev;
- 	u16 sprom_offset;
- 	u16 sprom_size;		/* number of words in sprom */
- 	u8 chip_package;
-@@ -404,7 +491,9 @@ extern bool ssb_is_sprom_available(struc
- 
- /* Set a fallback SPROM.
-  * See kdoc at the function definition for complete documentation. */
--extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
-+extern int ssb_arch_register_fallback_sprom(
-+		int (*sprom_callback)(struct ssb_bus *bus,
-+		struct ssb_sprom *out));
- 
- /* Suspend a SSB bus.
-  * Call this from the parent bus suspend routine. */
-@@ -518,6 +607,7 @@ extern int ssb_bus_may_powerdown(struct
-  * Otherwise static always-on powercontrol will be used. */
- extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
- 
-+extern void ssb_commit_settings(struct ssb_bus *bus);
- 
- /* Various helper functions */
- extern u32 ssb_admatch_base(u32 adm);
---- a/include/linux/ssb/ssb_driver_chipcommon.h
-+++ b/include/linux/ssb/ssb_driver_chipcommon.h
-@@ -8,7 +8,7 @@
-  * gpio interface, extbus, and support for serial and parallel flashes.
-  *
-  * Copyright 2005, Broadcom Corporation
-- * Copyright 2006, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2006, Michael Buesch <m@bues.ch>
-  *
-  * Licensed under the GPL version 2. See COPYING for details.
-  */
-@@ -123,6 +123,8 @@
- #define SSB_CHIPCO_FLASHDATA		0x0048
- #define SSB_CHIPCO_BCAST_ADDR		0x0050
- #define SSB_CHIPCO_BCAST_DATA		0x0054
-+#define SSB_CHIPCO_GPIOPULLUP		0x0058		/* Rev >= 20 only */
-+#define SSB_CHIPCO_GPIOPULLDOWN		0x005C		/* Rev >= 20 only */
- #define SSB_CHIPCO_GPIOIN		0x0060
- #define SSB_CHIPCO_GPIOOUT		0x0064
- #define SSB_CHIPCO_GPIOOUTEN		0x0068
-@@ -131,6 +133,9 @@
- #define SSB_CHIPCO_GPIOIRQ		0x0074
- #define SSB_CHIPCO_WATCHDOG		0x0080
- #define SSB_CHIPCO_GPIOTIMER		0x0088		/* LED powersave (corerev >= 16) */
-+#define  SSB_CHIPCO_GPIOTIMER_OFFTIME	0x0000FFFF
-+#define  SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT	0
-+#define  SSB_CHIPCO_GPIOTIMER_ONTIME	0xFFFF0000
- #define  SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT	16
- #define SSB_CHIPCO_GPIOTOUTM		0x008C		/* LED powersave (corerev >= 16) */
- #define SSB_CHIPCO_CLOCK_N		0x0090
-@@ -189,8 +194,10 @@
- #define  SSB_CHIPCO_CLKCTLST_HAVEALPREQ	0x00000008 /* ALP available request */
- #define  SSB_CHIPCO_CLKCTLST_HAVEHTREQ	0x00000010 /* HT available request */
- #define  SSB_CHIPCO_CLKCTLST_HWCROFF	0x00000020 /* Force HW clock request off */
--#define  SSB_CHIPCO_CLKCTLST_HAVEHT	0x00010000 /* HT available */
--#define  SSB_CHIPCO_CLKCTLST_HAVEALP	0x00020000 /* APL available */
-+#define  SSB_CHIPCO_CLKCTLST_HAVEALP	0x00010000 /* ALP available */
-+#define  SSB_CHIPCO_CLKCTLST_HAVEHT	0x00020000 /* HT available */
-+#define  SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT	0x00010000 /* 4328a0 has reversed bits */
-+#define  SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP	0x00020000 /* 4328a0 has reversed bits */
- #define SSB_CHIPCO_HW_WORKAROUND	0x01E4 /* Hardware workaround (rev >= 20) */
- #define SSB_CHIPCO_UART0_DATA		0x0300
- #define SSB_CHIPCO_UART0_IMR		0x0304
---- a/include/linux/ssb/ssb_driver_gige.h
-+++ b/include/linux/ssb/ssb_driver_gige.h
-@@ -2,6 +2,7 @@
- #define LINUX_SSB_DRIVER_GIGE_H_
- 
- #include <linux/ssb/ssb.h>
-+#include <linux/bug.h>
- #include <linux/pci.h>
- #include <linux/spinlock.h>
- 
---- a/include/linux/ssb/ssb_regs.h
-+++ b/include/linux/ssb/ssb_regs.h
-@@ -97,7 +97,7 @@
- #define  SSB_INTVEC_ENET1	0x00000040 /* Enable interrupts for enet 1 */
- #define SSB_TMSLOW		0x0F98     /* SB Target State Low */
- #define  SSB_TMSLOW_RESET	0x00000001 /* Reset */
--#define  SSB_TMSLOW_REJECT_22	0x00000002 /* Reject (Backplane rev 2.2) */
-+#define  SSB_TMSLOW_REJECT	0x00000002 /* Reject (Standard Backplane) */
- #define  SSB_TMSLOW_REJECT_23	0x00000004 /* Reject (Backplane rev 2.3) */
- #define  SSB_TMSLOW_CLOCK	0x00010000 /* Clock Enable */
- #define  SSB_TMSLOW_FGC		0x00020000 /* Force Gated Clocks On */
-@@ -228,6 +228,7 @@
- #define  SSB_SPROM1_AGAIN_BG_SHIFT	0
- #define  SSB_SPROM1_AGAIN_A		0xFF00	/* A-PHY */
- #define  SSB_SPROM1_AGAIN_A_SHIFT	8
-+#define SSB_SPROM1_CCODE		0x0076
- 
- /* SPROM Revision 2 (inherits from rev 1) */
- #define SSB_SPROM2_BFLHI		0x0038	/* Boardflags (high 16 bits) */
-@@ -267,6 +268,7 @@
- #define  SSB_SPROM3_OFDMGPO		0x107A	/* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
- 
- /* SPROM Revision 4 */
-+#define SSB_SPROM4_BOARDREV		0x0042	/* Board revision */
- #define SSB_SPROM4_BFLLO		0x0044	/* Boardflags (low 16 bits) */
- #define SSB_SPROM4_BFLHI		0x0046  /* Board Flags Hi */
- #define SSB_SPROM4_BFL2LO		0x0048	/* Board flags 2 (low 16 bits) */
-@@ -389,6 +391,11 @@
- #define  SSB_SPROM8_GPIOB_P2		0x00FF	/* Pin 2 */
- #define  SSB_SPROM8_GPIOB_P3		0xFF00	/* Pin 3 */
- #define  SSB_SPROM8_GPIOB_P3_SHIFT	8
-+#define SSB_SPROM8_LEDDC		0x009A
-+#define  SSB_SPROM8_LEDDC_ON		0xFF00	/* oncount */
-+#define  SSB_SPROM8_LEDDC_ON_SHIFT	8
-+#define  SSB_SPROM8_LEDDC_OFF		0x00FF	/* offcount */
-+#define  SSB_SPROM8_LEDDC_OFF_SHIFT	0
- #define SSB_SPROM8_ANTAVAIL		0x009C  /* Antenna available bitfields*/
- #define  SSB_SPROM8_ANTAVAIL_A		0xFF00	/* A-PHY bitfield */
- #define  SSB_SPROM8_ANTAVAIL_A_SHIFT	8
-@@ -404,6 +411,13 @@
- #define  SSB_SPROM8_AGAIN2_SHIFT	0
- #define  SSB_SPROM8_AGAIN3		0xFF00	/* Antenna 3 */
- #define  SSB_SPROM8_AGAIN3_SHIFT	8
-+#define SSB_SPROM8_TXRXC		0x00A2
-+#define  SSB_SPROM8_TXRXC_TXCHAIN	0x000f
-+#define  SSB_SPROM8_TXRXC_TXCHAIN_SHIFT	0
-+#define  SSB_SPROM8_TXRXC_RXCHAIN	0x00f0
-+#define  SSB_SPROM8_TXRXC_RXCHAIN_SHIFT	4
-+#define  SSB_SPROM8_TXRXC_SWITCH	0xff00
-+#define  SSB_SPROM8_TXRXC_SWITCH_SHIFT	8
- #define SSB_SPROM8_RSSIPARM2G		0x00A4	/* RSSI params for 2GHz */
- #define  SSB_SPROM8_RSSISMF2G		0x000F
- #define  SSB_SPROM8_RSSISMC2G		0x00F0
-@@ -430,8 +444,87 @@
- #define  SSB_SPROM8_TRI5GH_SHIFT	8
- #define SSB_SPROM8_RXPO			0x00AC  /* RX power offsets */
- #define  SSB_SPROM8_RXPO2G		0x00FF	/* 2GHz RX power offset */
-+#define  SSB_SPROM8_RXPO2G_SHIFT	0
- #define  SSB_SPROM8_RXPO5G		0xFF00	/* 5GHz RX power offset */
- #define  SSB_SPROM8_RXPO5G_SHIFT	8
-+#define SSB_SPROM8_FEM2G		0x00AE
-+#define SSB_SPROM8_FEM5G		0x00B0
-+#define  SSB_SROM8_FEM_TSSIPOS		0x0001
-+#define  SSB_SROM8_FEM_TSSIPOS_SHIFT	0
-+#define  SSB_SROM8_FEM_EXTPA_GAIN	0x0006
-+#define  SSB_SROM8_FEM_EXTPA_GAIN_SHIFT	1
-+#define  SSB_SROM8_FEM_PDET_RANGE	0x00F8
-+#define  SSB_SROM8_FEM_PDET_RANGE_SHIFT	3
-+#define  SSB_SROM8_FEM_TR_ISO		0x0700
-+#define  SSB_SROM8_FEM_TR_ISO_SHIFT	8
-+#define  SSB_SROM8_FEM_ANTSWLUT		0xF800
-+#define  SSB_SROM8_FEM_ANTSWLUT_SHIFT	11
-+#define SSB_SPROM8_THERMAL		0x00B2
-+#define  SSB_SPROM8_THERMAL_OFFSET	0x00ff
-+#define  SSB_SPROM8_THERMAL_OFFSET_SHIFT	0
-+#define  SSB_SPROM8_THERMAL_TRESH	0xff00
-+#define  SSB_SPROM8_THERMAL_TRESH_SHIFT	8
-+/* Temp sense related entries */
-+#define SSB_SPROM8_RAWTS		0x00B4
-+#define  SSB_SPROM8_RAWTS_RAWTEMP	0x01ff
-+#define  SSB_SPROM8_RAWTS_RAWTEMP_SHIFT	0
-+#define  SSB_SPROM8_RAWTS_MEASPOWER	0xfe00
-+#define  SSB_SPROM8_RAWTS_MEASPOWER_SHIFT	9
-+#define SSB_SPROM8_OPT_CORRX		0x00B6
-+#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE	0x00ff
-+#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT	0
-+#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX	0xfc00
-+#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT	10
-+#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION	0x0300
-+#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT	8
-+/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
-+#define SSB_SPROM8_HWIQ_IQSWP		0x00B8
-+#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR	0x000f
-+#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT	0
-+#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP	0x0010
-+#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT	4
-+#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL	0x0020
-+#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT	5
-+#define SSB_SPROM8_TEMPDELTA		0x00BA
-+#define  SSB_SPROM8_TEMPDELTA_PHYCAL	0x00ff
-+#define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT	0
-+#define  SSB_SPROM8_TEMPDELTA_PERIOD	0x0f00
-+#define  SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT	8
-+#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS	0xf000
-+#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT	12
-+
-+/* There are 4 blocks with power info sharing the same layout */
-+#define SSB_SROM8_PWR_INFO_CORE0	0x00C0
-+#define SSB_SROM8_PWR_INFO_CORE1	0x00E0
-+#define SSB_SROM8_PWR_INFO_CORE2	0x0100
-+#define SSB_SROM8_PWR_INFO_CORE3	0x0120
-+
-+#define SSB_SROM8_2G_MAXP_ITSSI		0x00
-+#define  SSB_SPROM8_2G_MAXP		0x00FF
-+#define  SSB_SPROM8_2G_ITSSI		0xFF00
-+#define  SSB_SPROM8_2G_ITSSI_SHIFT	8
-+#define SSB_SROM8_2G_PA_0		0x02	/* 2GHz power amp settings */
-+#define SSB_SROM8_2G_PA_1		0x04
-+#define SSB_SROM8_2G_PA_2		0x06
-+#define SSB_SROM8_5G_MAXP_ITSSI		0x08	/* 5GHz ITSSI and 5.3GHz Max Power */
-+#define  SSB_SPROM8_5G_MAXP		0x00FF
-+#define  SSB_SPROM8_5G_ITSSI		0xFF00
-+#define  SSB_SPROM8_5G_ITSSI_SHIFT	8
-+#define SSB_SPROM8_5GHL_MAXP		0x0A	/* 5.2GHz and 5.8GHz Max Power */
-+#define  SSB_SPROM8_5GH_MAXP		0x00FF
-+#define  SSB_SPROM8_5GL_MAXP		0xFF00
-+#define  SSB_SPROM8_5GL_MAXP_SHIFT	8
-+#define SSB_SROM8_5G_PA_0		0x0C	/* 5.3GHz power amp settings */
-+#define SSB_SROM8_5G_PA_1		0x0E
-+#define SSB_SROM8_5G_PA_2		0x10
-+#define SSB_SROM8_5GL_PA_0		0x12	/* 5.2GHz power amp settings */
-+#define SSB_SROM8_5GL_PA_1		0x14
-+#define SSB_SROM8_5GL_PA_2		0x16
-+#define SSB_SROM8_5GH_PA_0		0x18	/* 5.8GHz power amp settings */
-+#define SSB_SROM8_5GH_PA_1		0x1A
-+#define SSB_SROM8_5GH_PA_2		0x1C
-+
-+/* TODO: Make it deprecated */
- #define SSB_SPROM8_MAXP_BG		0x00C0  /* Max Power 2GHz in path 1 */
- #define  SSB_SPROM8_MAXP_BG_MASK	0x00FF  /* Mask for Max Power 2GHz */
- #define  SSB_SPROM8_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
-@@ -456,12 +549,63 @@
- #define SSB_SPROM8_PA1HIB0		0x00D8	/* 5.8GHz power amp settings */
- #define SSB_SPROM8_PA1HIB1		0x00DA
- #define SSB_SPROM8_PA1HIB2		0x00DC
-+
- #define SSB_SPROM8_CCK2GPO		0x0140	/* CCK power offset */
- #define SSB_SPROM8_OFDM2GPO		0x0142	/* 2.4GHz OFDM power offset */
- #define SSB_SPROM8_OFDM5GPO		0x0146	/* 5.3GHz OFDM power offset */
- #define SSB_SPROM8_OFDM5GLPO		0x014A	/* 5.2GHz OFDM power offset */
- #define SSB_SPROM8_OFDM5GHPO		0x014E	/* 5.8GHz OFDM power offset */
- 
-+#define SSB_SPROM8_2G_MCSPO		0x0152
-+#define SSB_SPROM8_5G_MCSPO		0x0162
-+#define SSB_SPROM8_5GL_MCSPO		0x0172
-+#define SSB_SPROM8_5GH_MCSPO		0x0182
-+
-+#define SSB_SPROM8_CDDPO		0x0192
-+#define SSB_SPROM8_STBCPO		0x0194
-+#define SSB_SPROM8_BW40PO		0x0196
-+#define SSB_SPROM8_BWDUPPO		0x0198
-+
-+/* Values for boardflags_lo read from SPROM */
-+#define SSB_BFL_BTCOEXIST		0x0001	/* implements Bluetooth coexistance */
-+#define SSB_BFL_PACTRL			0x0002	/* GPIO 9 controlling the PA */
-+#define SSB_BFL_AIRLINEMODE		0x0004	/* implements GPIO 13 radio disable indication */
-+#define SSB_BFL_RSSI			0x0008	/* software calculates nrssi slope. */
-+#define SSB_BFL_ENETSPI			0x0010	/* has ephy roboswitch spi */
-+#define SSB_BFL_XTAL_NOSLOW		0x0020	/* no slow clock available */
-+#define SSB_BFL_CCKHIPWR		0x0040	/* can do high power CCK transmission */
-+#define SSB_BFL_ENETADM			0x0080	/* has ADMtek switch */
-+#define SSB_BFL_ENETVLAN		0x0100	/* can do vlan */
-+#define SSB_BFL_AFTERBURNER		0x0200	/* supports Afterburner mode */
-+#define SSB_BFL_NOPCI			0x0400	/* board leaves PCI floating */
-+#define SSB_BFL_FEM			0x0800	/* supports the Front End Module */
-+#define SSB_BFL_EXTLNA			0x1000	/* has an external LNA */
-+#define SSB_BFL_HGPA			0x2000	/* had high gain PA */
-+#define SSB_BFL_BTCMOD			0x4000	/* BFL_BTCOEXIST is given in alternate GPIOs */
-+#define SSB_BFL_ALTIQ			0x8000	/* alternate I/Q settings */
-+
-+/* Values for boardflags_hi read from SPROM */
-+#define SSB_BFH_NOPA			0x0001	/* has no PA */
-+#define SSB_BFH_RSSIINV			0x0002	/* RSSI uses positive slope (not TSSI) */
-+#define SSB_BFH_PAREF			0x0004	/* uses the PARef LDO */
-+#define SSB_BFH_3TSWITCH		0x0008	/* uses a triple throw switch shared with bluetooth */
-+#define SSB_BFH_PHASESHIFT		0x0010	/* can support phase shifter */
-+#define SSB_BFH_BUCKBOOST		0x0020	/* has buck/booster */
-+#define SSB_BFH_FEM_BT			0x0040	/* has FEM and switch to share antenna with bluetooth */
-+
-+/* Values for boardflags2_lo read from SPROM */
-+#define SSB_BFL2_RXBB_INT_REG_DIS	0x0001	/* external RX BB regulator present */
-+#define SSB_BFL2_APLL_WAR		0x0002	/* alternative A-band PLL settings implemented */
-+#define SSB_BFL2_TXPWRCTRL_EN 		0x0004	/* permits enabling TX Power Control */
-+#define SSB_BFL2_2X4_DIV		0x0008	/* 2x4 diversity switch */
-+#define SSB_BFL2_5G_PWRGAIN		0x0010	/* supports 5G band power gain */
-+#define SSB_BFL2_PCIEWAR_OVR		0x0020	/* overrides ASPM and Clkreq settings */
-+#define SSB_BFL2_CAESERS_BRD		0x0040	/* is Caesers board (unused) */
-+#define SSB_BFL2_BTC3WIRE		0x0080	/* used 3-wire bluetooth coexist */
-+#define SSB_BFL2_SKWRKFEM_BRD		0x0100	/* 4321mcm93 uses Skyworks FEM */
-+#define SSB_BFL2_SPUR_WAR		0x0200	/* has a workaround for clock-harmonic spurs */
-+#define SSB_BFL2_GPLL_WAR		0x0400	/* altenative G-band PLL settings implemented */
-+
- /* Values for SSB_SPROM1_BINF_CCODE */
- enum {
- 	SSB_SPROM1CCODE_WORLD = 0,