kernel: update bcma and ssb to version master-2011-07-22 from wireless-testing

SVN-Revision: 27731

4 files changed, 3737 insertions, 77 deletions

diff --git a/target/linux/generic/patches-2.6.38/020-ssb_update.patch b/target/linux/generic/patches-2.6.38/020-ssb_update.patch
index a81b07e26f..3db961367b 100644
--- a/target/linux/generic/patches-2.6.38/020-ssb_update.patch
+++ b/target/linux/generic/patches-2.6.38/020-ssb_update.patch
@@ -134,3 +134,1015 @@
  #define SSB_SPROM5_IL0MAC		0x0052	/* 6 byte MAC address for a/b/g/n */
  #define SSB_SPROM5_GPIOA		0x0076	/* Gen. Purpose IO # 0 and 1 */
  #define  SSB_SPROM5_GPIOA_P0		0x00FF	/* Pin 0 */
+diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
+index 7c031fd..06d15b6 100644
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
+@@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
+ 	if (!ccdev)
+ 		return;
+ 	bus = ccdev->bus;
++
++	/* We support SLOW only on 6..9 */
++	if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
++		mode = SSB_CLKMODE_DYNAMIC;
++
++	if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
++		return; /* PMU controls clockmode, separated function needed */
++	SSB_WARN_ON(ccdev->id.revision >= 20);
++
+ 	/* chipcommon cores prior to rev6 don't support dynamic clock control */
+ 	if (ccdev->id.revision < 6)
+ 		return;
+-	/* chipcommon cores rev10 are a whole new ball game */
++
++	/* ChipCommon cores rev10+ need testing */
+ 	if (ccdev->id.revision >= 10)
+ 		return;
++
+ 	if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
+ 		return;
+ 
+ 	switch (mode) {
+-	case SSB_CLKMODE_SLOW:
++	case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
+ 		tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+ 		tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+ 		chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+ 		break;
+ 	case SSB_CLKMODE_FAST:
+-		ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
+-		tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+-		tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+-		tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
+-		chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
++		if (ccdev->id.revision < 10) {
++			ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
++			tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
++			tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
++			tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
++			chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
++		} else {
++			chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
++				(chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
++				 SSB_CHIPCO_SYSCLKCTL_FORCEHT));
++			/* udelay(150); TODO: not available in early init */
++		}
+ 		break;
+ 	case SSB_CLKMODE_DYNAMIC:
+-		tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+-		tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+-		tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
+-		tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
+-		if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
+-			tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
+-		chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+-
+-		/* for dynamic control, we have to release our xtal_pu "force on" */
+-		if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
+-			ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
++		if (ccdev->id.revision < 10) {
++			tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
++			tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
++			tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
++			tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
++			if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
++			    SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
++				tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
++			chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
++
++			/* For dynamic control, we have to release our xtal_pu
++			 * "force on" */
++			if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
++				ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
++		} else {
++			chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
++				(chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
++				 ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
++		}
+ 		break;
+ 	default:
+ 		SSB_WARN_ON(1);
+@@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chipcommon *cc)
+ 	if (cc->dev->id.revision >= 11)
+ 		cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
+ 	ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
++
++	if (cc->dev->id.revision >= 20) {
++		chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
++		chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
++	}
++
+ 	ssb_pmu_init(cc);
+ 	chipco_powercontrol_init(cc);
+ 	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c
+index 5732bb2..a7aef47 100644
+--- a/drivers/ssb/driver_chipcommon_pmu.c
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
+ 	u32 min_msk = 0, max_msk = 0;
+ 	unsigned int i;
+ 	const struct pmu_res_updown_tab_entry *updown_tab = NULL;
+-	unsigned int updown_tab_size;
++	unsigned int updown_tab_size = 0;
+ 	const struct pmu_res_depend_tab_entry *depend_tab = NULL;
+-	unsigned int depend_tab_size;
++	unsigned int depend_tab_size = 0;
+ 
+ 	switch (bus->chip_id) {
+ 	case 0x4312:
++		 min_msk = 0xCBB;
++		 break;
+ 	case 0x4322:
+ 		/* We keep the default settings:
+ 		 * min_msk = 0xCBB
+diff --git a/drivers/ssb/driver_gige.c b/drivers/ssb/driver_gige.c
+index 5ba92a2..d758909 100644
+--- a/drivers/ssb/driver_gige.c
++++ b/drivers/ssb/driver_gige.c
+@@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige *dev,
+ 	gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
+ }
+ 
+-static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+-				    int reg, int size, u32 *val)
++static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
++					      unsigned int devfn, int reg,
++					      int size, u32 *val)
+ {
+ 	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
+ 	unsigned long flags;
+@@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+ 	return PCIBIOS_SUCCESSFUL;
+ }
+ 
+-static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+-				     int reg, int size, u32 val)
++static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
++					       unsigned int devfn, int reg,
++					       int size, u32 val)
+ {
+ 	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
+ 	unsigned long flags;
+@@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+ 	return PCIBIOS_SUCCESSFUL;
+ }
+ 
+-static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
++static int __devinit ssb_gige_probe(struct ssb_device *sdev,
++				    const struct ssb_device_id *id)
+ {
+ 	struct ssb_gige *dev;
+ 	u32 base, tmslow, tmshigh;
+diff --git a/drivers/ssb/driver_pcicore.c b/drivers/ssb/driver_pcicore.c
+index 0e8d352..11d85bf 100644
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -15,6 +15,11 @@
+ 
+ #include "ssb_private.h"
+ 
++static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
++static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
++static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
++static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
++				u8 address, u16 data);
+ 
+ static inline
+ u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
+@@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ 	return ssb_mips_irq(extpci_core->dev) + 2;
+ }
+ 
+-static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
++static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
+ {
+ 	u32 val;
+ 
+@@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
+ 	register_pci_controller(&ssb_pcicore_controller);
+ }
+ 
+-static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
++static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
+ {
+ 	struct ssb_bus *bus = pc->dev->bus;
+ 	u16 chipid_top;
+@@ -403,25 +408,133 @@ static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
+ }
+ #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
+ 
++/**************************************************
++ * Workarounds.
++ **************************************************/
++
++static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
++{
++	u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
++	if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
++		tmp &= ~0xF000;
++		tmp |= (pc->dev->core_index << 12);
++		pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
++	}
++}
++
++static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
++{
++	return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
++}
++
++static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
++{
++	const u8 serdes_pll_device = 0x1D;
++	const u8 serdes_rx_device = 0x1F;
++	u16 tmp;
++
++	ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
++			    ssb_pcicore_polarity_workaround(pc));
++	tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
++	if (tmp & 0x4000)
++		ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
++}
++
++static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
++{
++	struct ssb_device *pdev = pc->dev;
++	struct ssb_bus *bus = pdev->bus;
++	u32 tmp;
++
++	tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
++	tmp |= SSB_PCICORE_SBTOPCI_PREF;
++	tmp |= SSB_PCICORE_SBTOPCI_BURST;
++	pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
++
++	if (pdev->id.revision < 5) {
++		tmp = ssb_read32(pdev, SSB_IMCFGLO);
++		tmp &= ~SSB_IMCFGLO_SERTO;
++		tmp |= 2;
++		tmp &= ~SSB_IMCFGLO_REQTO;
++		tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
++		ssb_write32(pdev, SSB_IMCFGLO, tmp);
++		ssb_commit_settings(bus);
++	} else if (pdev->id.revision >= 11) {
++		tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
++		tmp |= SSB_PCICORE_SBTOPCI_MRM;
++		pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
++	}
++}
++
++static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
++{
++	u32 tmp;
++	u8 rev = pc->dev->id.revision;
++
++	if (rev == 0 || rev == 1) {
++		/* TLP Workaround register. */
++		tmp = ssb_pcie_read(pc, 0x4);
++		tmp |= 0x8;
++		ssb_pcie_write(pc, 0x4, tmp);
++	}
++	if (rev == 1) {
++		/* DLLP Link Control register. */
++		tmp = ssb_pcie_read(pc, 0x100);
++		tmp |= 0x40;
++		ssb_pcie_write(pc, 0x100, tmp);
++	}
++
++	if (rev == 0) {
++		const u8 serdes_rx_device = 0x1F;
++
++		ssb_pcie_mdio_write(pc, serdes_rx_device,
++					2 /* Timer */, 0x8128);
++		ssb_pcie_mdio_write(pc, serdes_rx_device,
++					6 /* CDR */, 0x0100);
++		ssb_pcie_mdio_write(pc, serdes_rx_device,
++					7 /* CDR BW */, 0x1466);
++	} else if (rev == 3 || rev == 4 || rev == 5) {
++		/* TODO: DLLP Power Management Threshold */
++		ssb_pcicore_serdes_workaround(pc);
++		/* TODO: ASPM */
++	} else if (rev == 7) {
++		/* TODO: No PLL down */
++	}
++
++	if (rev >= 6) {
++		/* Miscellaneous Configuration Fixup */
++		tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
++		if (!(tmp & 0x8000))
++			pcicore_write16(pc, SSB_PCICORE_SPROM(5),
++					tmp | 0x8000);
++	}
++}
+ 
+ /**************************************************
+  * Generic and Clientmode operation code.
+  **************************************************/
+ 
+-static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
++static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
+ {
++	ssb_pcicore_fix_sprom_core_index(pc);
++
+ 	/* Disable PCI interrupts. */
+ 	ssb_write32(pc->dev, SSB_INTVEC, 0);
++
++	/* Additional PCIe always once-executed workarounds */
++	if (pc->dev->id.coreid == SSB_DEV_PCIE) {
++		ssb_pcicore_serdes_workaround(pc);
++		/* TODO: ASPM */
++		/* TODO: Clock Request Update */
++	}
+ }
+ 
+-void ssb_pcicore_init(struct ssb_pcicore *pc)
++void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
+ {
+ 	struct ssb_device *dev = pc->dev;
+-	struct ssb_bus *bus;
+ 
+ 	if (!dev)
+ 		return;
+-	bus = dev->bus;
+ 	if (!ssb_device_is_enabled(dev))
+ 		ssb_device_enable(dev, 0);
+ 
+@@ -446,11 +559,35 @@ static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
+ 	pcicore_write32(pc, 0x134, data);
+ }
+ 
+-static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
+-				u8 address, u16 data)
++static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
++{
++	const u16 mdio_control = 0x128;
++	const u16 mdio_data = 0x12C;
++	u32 v;
++	int i;
++
++	v = (1 << 30); /* Start of Transaction */
++	v |= (1 << 28); /* Write Transaction */
++	v |= (1 << 17); /* Turnaround */
++	v |= (0x1F << 18);
++	v |= (phy << 4);
++	pcicore_write32(pc, mdio_data, v);
++
++	udelay(10);
++	for (i = 0; i < 200; i++) {
++		v = pcicore_read32(pc, mdio_control);
++		if (v & 0x100 /* Trans complete */)
++			break;
++		msleep(1);
++	}
++}
++
++static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
+ {
+ 	const u16 mdio_control = 0x128;
+ 	const u16 mdio_data = 0x12C;
++	int max_retries = 10;
++	u16 ret = 0;
+ 	u32 v;
+ 	int i;
+ 
+@@ -458,46 +595,68 @@ static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
+ 	v |= 0x2; /* MDIO Clock Divisor */
+ 	pcicore_write32(pc, mdio_control, v);
+ 
++	if (pc->dev->id.revision >= 10) {
++		max_retries = 200;
++		ssb_pcie_mdio_set_phy(pc, device);
++	}
++
+ 	v = (1 << 30); /* Start of Transaction */
+-	v |= (1 << 28); /* Write Transaction */
++	v |= (1 << 29); /* Read Transaction */
+ 	v |= (1 << 17); /* Turnaround */
+-	v |= (u32)device << 22;
++	if (pc->dev->id.revision < 10)
++		v |= (u32)device << 22;
+ 	v |= (u32)address << 18;
+-	v |= data;
+ 	pcicore_write32(pc, mdio_data, v);
+ 	/* Wait for the device to complete the transaction */
+ 	udelay(10);
+-	for (i = 0; i < 10; i++) {
++	for (i = 0; i < max_retries; i++) {
+ 		v = pcicore_read32(pc, mdio_control);
+-		if (v & 0x100 /* Trans complete */)
++		if (v & 0x100 /* Trans complete */) {
++			udelay(10);
++			ret = pcicore_read32(pc, mdio_data);
+ 			break;
++		}
+ 		msleep(1);
+ 	}
+ 	pcicore_write32(pc, mdio_control, 0);
++	return ret;
+ }
+ 
+-static void ssb_broadcast_value(struct ssb_device *dev,
+-				u32 address, u32 data)
++static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
++				u8 address, u16 data)
+ {
+-	/* This is used for both, PCI and ChipCommon core, so be careful. */
+-	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+-	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+-
+-	ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+-	ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+-	ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+-	ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+-}
++	const u16 mdio_control = 0x128;
++	const u16 mdio_data = 0x12C;
++	int max_retries = 10;
++	u32 v;
++	int i;
+ 
+-static void ssb_commit_settings(struct ssb_bus *bus)
+-{
+-	struct ssb_device *dev;
++	v = 0x80; /* Enable Preamble Sequence */
++	v |= 0x2; /* MDIO Clock Divisor */
++	pcicore_write32(pc, mdio_control, v);
+ 
+-	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+-	if (WARN_ON(!dev))
+-		return;
+-	/* This forces an update of the cached registers. */
+-	ssb_broadcast_value(dev, 0xFD8, 0);
++	if (pc->dev->id.revision >= 10) {
++		max_retries = 200;
++		ssb_pcie_mdio_set_phy(pc, device);
++	}
++
++	v = (1 << 30); /* Start of Transaction */
++	v |= (1 << 28); /* Write Transaction */
++	v |= (1 << 17); /* Turnaround */
++	if (pc->dev->id.revision < 10)
++		v |= (u32)device << 22;
++	v |= (u32)address << 18;
++	v |= data;
++	pcicore_write32(pc, mdio_data, v);
++	/* Wait for the device to complete the transaction */
++	udelay(10);
++	for (i = 0; i < max_retries; i++) {
++		v = pcicore_read32(pc, mdio_control);
++		if (v & 0x100 /* Trans complete */)
++			break;
++		msleep(1);
++	}
++	pcicore_write32(pc, mdio_control, 0);
+ }
+ 
+ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+@@ -550,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+ 	if (pc->setup_done)
+ 		goto out;
+ 	if (pdev->id.coreid == SSB_DEV_PCI) {
+-		tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
+-		tmp |= SSB_PCICORE_SBTOPCI_PREF;
+-		tmp |= SSB_PCICORE_SBTOPCI_BURST;
+-		pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
+-
+-		if (pdev->id.revision < 5) {
+-			tmp = ssb_read32(pdev, SSB_IMCFGLO);
+-			tmp &= ~SSB_IMCFGLO_SERTO;
+-			tmp |= 2;
+-			tmp &= ~SSB_IMCFGLO_REQTO;
+-			tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
+-			ssb_write32(pdev, SSB_IMCFGLO, tmp);
+-			ssb_commit_settings(bus);
+-		} else if (pdev->id.revision >= 11) {
+-			tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
+-			tmp |= SSB_PCICORE_SBTOPCI_MRM;
+-			pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
+-		}
++		ssb_pcicore_pci_setup_workarounds(pc);
+ 	} else {
+ 		WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
+-		//TODO: Better make defines for all these magic PCIE values.
+-		if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
+-			/* TLP Workaround register. */
+-			tmp = ssb_pcie_read(pc, 0x4);
+-			tmp |= 0x8;
+-			ssb_pcie_write(pc, 0x4, tmp);
+-		}
+-		if (pdev->id.revision == 0) {
+-			const u8 serdes_rx_device = 0x1F;
+-
+-			ssb_pcie_mdio_write(pc, serdes_rx_device,
+-					    2 /* Timer */, 0x8128);
+-			ssb_pcie_mdio_write(pc, serdes_rx_device,
+-					    6 /* CDR */, 0x0100);
+-			ssb_pcie_mdio_write(pc, serdes_rx_device,
+-					    7 /* CDR BW */, 0x1466);
+-		} else if (pdev->id.revision == 1) {
+-			/* DLLP Link Control register. */
+-			tmp = ssb_pcie_read(pc, 0x100);
+-			tmp |= 0x40;
+-			ssb_pcie_write(pc, 0x100, tmp);
+-		}
++		ssb_pcicore_pcie_setup_workarounds(pc);
+ 	}
+ 	pc->setup_done = 1;
+ out:
+diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
+index e05ba6e..6ec6e09 100644
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -557,7 +557,7 @@ error:
+ }
+ 
+ /* Needs ssb_buses_lock() */
+-static int ssb_attach_queued_buses(void)
++static int __devinit ssb_attach_queued_buses(void)
+ {
+ 	struct ssb_bus *bus, *n;
+ 	int err = 0;
+@@ -768,9 +768,9 @@ out:
+ 	return err;
+ }
+ 
+-static int ssb_bus_register(struct ssb_bus *bus,
+-			    ssb_invariants_func_t get_invariants,
+-			    unsigned long baseaddr)
++static int __devinit ssb_bus_register(struct ssb_bus *bus,
++				      ssb_invariants_func_t get_invariants,
++				      unsigned long baseaddr)
+ {
+ 	int err;
+ 
+@@ -851,8 +851,8 @@ err_disable_xtal:
+ }
+ 
+ #ifdef CONFIG_SSB_PCIHOST
+-int ssb_bus_pcibus_register(struct ssb_bus *bus,
+-			    struct pci_dev *host_pci)
++int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
++				      struct pci_dev *host_pci)
+ {
+ 	int err;
+ 
+@@ -875,9 +875,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
+ #endif /* CONFIG_SSB_PCIHOST */
+ 
+ #ifdef CONFIG_SSB_PCMCIAHOST
+-int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
+-			       struct pcmcia_device *pcmcia_dev,
+-			       unsigned long baseaddr)
++int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
++					 struct pcmcia_device *pcmcia_dev,
++					 unsigned long baseaddr)
+ {
+ 	int err;
+ 
+@@ -897,8 +897,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
+ #endif /* CONFIG_SSB_PCMCIAHOST */
+ 
+ #ifdef CONFIG_SSB_SDIOHOST
+-int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
+-			     unsigned int quirks)
++int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
++				       struct sdio_func *func,
++				       unsigned int quirks)
+ {
+ 	int err;
+ 
+@@ -918,9 +919,9 @@ int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
+ EXPORT_SYMBOL(ssb_bus_sdiobus_register);
+ #endif /* CONFIG_SSB_PCMCIAHOST */
+ 
+-int ssb_bus_ssbbus_register(struct ssb_bus *bus,
+-			    unsigned long baseaddr,
+-			    ssb_invariants_func_t get_invariants)
++int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
++				      unsigned long baseaddr,
++				      ssb_invariants_func_t get_invariants)
+ {
+ 	int err;
+ 
+@@ -1001,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
+ 	switch (plltype) {
+ 	case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
+ 		if (m & SSB_CHIPCO_CLK_T6_MMASK)
+-			return SSB_CHIPCO_CLK_T6_M0;
+-		return SSB_CHIPCO_CLK_T6_M1;
++			return SSB_CHIPCO_CLK_T6_M1;
++		return SSB_CHIPCO_CLK_T6_M0;
+ 	case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
+ 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
+ 	case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
+@@ -1117,23 +1118,22 @@ static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
+ {
+ 	u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
+ 
+-	/* The REJECT bit changed position in TMSLOW between
+-	 * Backplane revisions. */
++	/* The REJECT bit seems to be different for Backplane rev 2.3 */
+ 	switch (rev) {
+ 	case SSB_IDLOW_SSBREV_22:
+-		return SSB_TMSLOW_REJECT_22;
++	case SSB_IDLOW_SSBREV_24:
++	case SSB_IDLOW_SSBREV_26:
++		return SSB_TMSLOW_REJECT;
+ 	case SSB_IDLOW_SSBREV_23:
+ 		return SSB_TMSLOW_REJECT_23;
+-	case SSB_IDLOW_SSBREV_24:     /* TODO - find the proper REJECT bits */
+-	case SSB_IDLOW_SSBREV_25:     /* same here */
+-	case SSB_IDLOW_SSBREV_26:     /* same here */
++	case SSB_IDLOW_SSBREV_25:     /* TODO - find the proper REJECT bit */
+ 	case SSB_IDLOW_SSBREV_27:     /* same here */
+-		return SSB_TMSLOW_REJECT_23;	/* this is a guess */
++		return SSB_TMSLOW_REJECT;	/* this is a guess */
+ 	default:
+ 		printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+ 		WARN_ON(1);
+ 	}
+-	return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
++	return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
+ }
+ 
+ int ssb_device_is_enabled(struct ssb_device *dev)
+@@ -1266,7 +1266,10 @@ u32 ssb_dma_translation(struct ssb_device *dev)
+ 	case SSB_BUSTYPE_SSB:
+ 		return 0;
+ 	case SSB_BUSTYPE_PCI:
+-		return SSB_PCI_DMA;
++		if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
++			return SSB_PCIE_DMA_H32;
++		else
++			return SSB_PCI_DMA;
+ 	default:
+ 		__ssb_dma_not_implemented(dev);
+ 	}
+@@ -1309,20 +1312,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
+ 
+ int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
+ {
+-	struct ssb_chipcommon *cc;
+ 	int err;
+ 	enum ssb_clkmode mode;
+ 
+ 	err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
+ 	if (err)
+ 		goto error;
+-	cc = &bus->chipco;
+-	mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
+-	ssb_chipco_set_clockmode(cc, mode);
+ 
+ #ifdef CONFIG_SSB_DEBUG
+ 	bus->powered_up = 1;
+ #endif
++
++	mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
++	ssb_chipco_set_clockmode(&bus->chipco, mode);
++
+ 	return 0;
+ error:
+ 	ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
+@@ -1330,6 +1333,37 @@ error:
+ }
+ EXPORT_SYMBOL(ssb_bus_powerup);
+ 
++static void ssb_broadcast_value(struct ssb_device *dev,
++				u32 address, u32 data)
++{
++#ifdef CONFIG_SSB_DRIVER_PCICORE
++	/* This is used for both, PCI and ChipCommon core, so be careful. */
++	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
++	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
++#endif
++
++	ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
++	ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
++	ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
++	ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
++}
++
++void ssb_commit_settings(struct ssb_bus *bus)
++{
++	struct ssb_device *dev;
++
++#ifdef CONFIG_SSB_DRIVER_PCICORE
++	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
++#else
++	dev = bus->chipco.dev;
++#endif
++	if (WARN_ON(!dev))
++		return;
++	/* This forces an update of the cached registers. */
++	ssb_broadcast_value(dev, 0xFD8, 0);
++}
++EXPORT_SYMBOL(ssb_commit_settings);
++
+ u32 ssb_admatch_base(u32 adm)
+ {
+ 	u32 base = 0;
+diff --git a/drivers/ssb/pci.c b/drivers/ssb/pci.c
+index a467b20..a00b35f 100644
+--- a/drivers/ssb/pci.c
++++ b/drivers/ssb/pci.c
+@@ -662,7 +662,6 @@ static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
+ static int ssb_pci_sprom_get(struct ssb_bus *bus,
+ 			     struct ssb_sprom *sprom)
+ {
+-	const struct ssb_sprom *fallback;
+ 	int err;
+ 	u16 *buf;
+ 
+@@ -670,7 +669,7 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
+ 		ssb_printk(KERN_ERR PFX "No SPROM available!\n");
+ 		return -ENODEV;
+ 	}
+-	if (bus->chipco.dev) {	/* can be unavailible! */
++	if (bus->chipco.dev) {	/* can be unavailable! */
+ 		/*
+ 		 * get SPROM offset: SSB_SPROM_BASE1 except for
+ 		 * chipcommon rev >= 31 or chip ID is 0x4312 and
+@@ -707,10 +706,17 @@ static int ssb_pci_sprom_get(struct ssb_bus *bus,
+ 		if (err) {
+ 			/* All CRC attempts failed.
+ 			 * Maybe there is no SPROM on the device?
+-			 * If we have a fallback, use that. */
+-			fallback = ssb_get_fallback_sprom();
+-			if (fallback) {
+-				memcpy(sprom, fallback, sizeof(*sprom));
++			 * Now we ask the arch code if there is some sprom
++			 * available for this device in some other storage */
++			err = ssb_fill_sprom_with_fallback(bus, sprom);
++			if (err) {
++				ssb_printk(KERN_WARNING PFX "WARNING: Using"
++					   " fallback SPROM failed (err %d)\n",
++					   err);
++			} else {
++				ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
++					    " revision %d provided by"
++					    " platform.\n", sprom->revision);
+ 				err = 0;
+ 				goto out_free;
+ 			}
+@@ -728,12 +734,9 @@ out_free:
+ static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
+ 				  struct ssb_boardinfo *bi)
+ {
+-	pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
+-			     &bi->vendor);
+-	pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
+-			     &bi->type);
+-	pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
+-			     &bi->rev);
++	bi->vendor = bus->host_pci->subsystem_vendor;
++	bi->type = bus->host_pci->subsystem_device;
++	bi->rev = bus->host_pci->revision;
+ }
+ 
+ int ssb_pci_get_invariants(struct ssb_bus *bus,
+diff --git a/drivers/ssb/pcihost_wrapper.c b/drivers/ssb/pcihost_wrapper.c
+index f6c8c81..d7a9813 100644
+--- a/drivers/ssb/pcihost_wrapper.c
++++ b/drivers/ssb/pcihost_wrapper.c
+@@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci_dev *dev)
+ # define ssb_pcihost_resume	NULL
+ #endif /* CONFIG_PM */
+ 
+-static int ssb_pcihost_probe(struct pci_dev *dev,
+-			     const struct pci_device_id *id)
++static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
++				       const struct pci_device_id *id)
+ {
+ 	struct ssb_bus *ssb;
+ 	int err = -ENOMEM;
+@@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pci_dev *dev)
+ 	pci_set_drvdata(dev, NULL);
+ }
+ 
+-int ssb_pcihost_register(struct pci_driver *driver)
++int __devinit ssb_pcihost_register(struct pci_driver *driver)
+ {
+ 	driver->probe = ssb_pcihost_probe;
+ 	driver->remove = ssb_pcihost_remove;
+diff --git a/drivers/ssb/scan.c b/drivers/ssb/scan.c
+index 29884c0..8047f9a 100644
+--- a/drivers/ssb/scan.c
++++ b/drivers/ssb/scan.c
+@@ -258,7 +258,10 @@ static int we_support_multiple_80211_cores(struct ssb_bus *bus)
+ #ifdef CONFIG_SSB_PCIHOST
+ 	if (bus->bustype == SSB_BUSTYPE_PCI) {
+ 		if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
+-		    bus->host_pci->device == 0x4324)
++		    ((bus->host_pci->device == 0x4313) ||
++		     (bus->host_pci->device == 0x431A) ||
++		     (bus->host_pci->device == 0x4321) ||
++		     (bus->host_pci->device == 0x4324)))
+ 			return 1;
+ 	}
+ #endif /* CONFIG_SSB_PCIHOST */
+@@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
+ 	} else {
+ 		if (bus->bustype == SSB_BUSTYPE_PCI) {
+ 			bus->chip_id = pcidev_to_chipid(bus->host_pci);
+-			pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
+-					     &bus->chip_rev);
++			bus->chip_rev = bus->host_pci->revision;
+ 			bus->chip_package = 0;
+ 		} else {
+ 			bus->chip_id = 0x4710;
+diff --git a/drivers/ssb/sprom.c b/drivers/ssb/sprom.c
+index 4f7cc8d..45ff0e3 100644
+--- a/drivers/ssb/sprom.c
++++ b/drivers/ssb/sprom.c
+@@ -17,7 +17,7 @@
+ #include <linux/slab.h>
+ 
+ 
+-static const struct ssb_sprom *fallback_sprom;
++static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
+ 
+ 
+ static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
+@@ -145,36 +145,43 @@ out:
+ }
+ 
+ /**
+- * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
++ * ssb_arch_register_fallback_sprom - Registers a method providing a
++ * fallback SPROM if no SPROM is found.
+  *
+- * @sprom: The SPROM data structure to register.
++ * @sprom_callback: The callback function.
+  *
+- * With this function the architecture implementation may register a fallback
+- * SPROM data structure. The fallback is only used for PCI based SSB devices,
+- * where no valid SPROM can be found in the shadow registers.
++ * With this function the architecture implementation may register a
++ * callback handler which fills the SPROM data structure. The fallback is
++ * only used for PCI based SSB devices, where no valid SPROM can be found
++ * in the shadow registers.
+  *
+- * This function is useful for weird architectures that have a half-assed SSB device
+- * hardwired to their PCI bus.
++ * This function is useful for weird architectures that have a half-assed
++ * SSB device hardwired to their PCI bus.
+  *
+- * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
+- * don't use this fallback.
+- * Architectures must provide the SPROM for native SSB devices anyway,
+- * so the fallback also isn't used for native devices.
++ * Note that it does only work with PCI attached SSB devices. PCMCIA
++ * devices currently don't use this fallback.
++ * Architectures must provide the SPROM for native SSB devices anyway, so
++ * the fallback also isn't used for native devices.
+  *
+- * This function is available for architecture code, only. So it is not exported.
++ * This function is available for architecture code, only. So it is not
++ * exported.
+  */
+-int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
++int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
++				     struct ssb_sprom *out))
+ {
+-	if (fallback_sprom)
++	if (get_fallback_sprom)
+ 		return -EEXIST;
+-	fallback_sprom = sprom;
++	get_fallback_sprom = sprom_callback;
+ 
+ 	return 0;
+ }
+ 
+-const struct ssb_sprom *ssb_get_fallback_sprom(void)
++int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
+ {
+-	return fallback_sprom;
++	if (!get_fallback_sprom)
++		return -ENOENT;
++
++	return get_fallback_sprom(bus, out);
+ }
+ 
+ /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
+@@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_bus *bus)
+ 	/* this routine differs from specs as we do not access SPROM directly
+ 	   on PCMCIA */
+ 	if (bus->bustype == SSB_BUSTYPE_PCI &&
+-	    bus->chipco.dev &&	/* can be unavailible! */
++	    bus->chipco.dev &&	/* can be unavailable! */
+ 	    bus->chipco.dev->id.revision >= 31)
+ 		return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
+ 
+diff --git a/drivers/ssb/ssb_private.h b/drivers/ssb/ssb_private.h
+index 0331139..7765301 100644
+--- a/drivers/ssb/ssb_private.h
++++ b/drivers/ssb/ssb_private.h
+@@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_bus *bus,
+ 			     const char *buf, size_t count,
+ 			     int (*sprom_check_crc)(const u16 *sprom, size_t size),
+ 			     int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
+-extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
++extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
++					struct ssb_sprom *out);
+ 
+ 
+ /* core.c */
+diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
+index 9659eff..8623217 100644
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -27,6 +27,8 @@ struct ssb_sprom {
+ 	u8 et1mdcport;		/* MDIO for enet1 */
+ 	u8 board_rev;		/* Board revision number from SPROM. */
+ 	u8 country_code;	/* Country Code */
++	u16 leddc_on_time;	/* LED Powersave Duty Cycle On Count */
++	u16 leddc_off_time;	/* LED Powersave Duty Cycle Off Count */
+ 	u8 ant_available_a;	/* 2GHz antenna available bits (up to 4) */
+ 	u8 ant_available_bg;	/* 5GHz antenna available bits (up to 4) */
+ 	u16 pa0b0;
+@@ -99,7 +101,7 @@ struct ssb_sprom {
+ struct ssb_boardinfo {
+ 	u16 vendor;
+ 	u16 type;
+-	u16 rev;
++	u8  rev;
+ };
+ 
+ 
+@@ -308,7 +310,7 @@ struct ssb_bus {
+ 
+ 	/* ID information about the Chip. */
+ 	u16 chip_id;
+-	u16 chip_rev;
++	u8 chip_rev;
+ 	u16 sprom_offset;
+ 	u16 sprom_size;		/* number of words in sprom */
+ 	u8 chip_package;
+@@ -404,7 +406,9 @@ extern bool ssb_is_sprom_available(struct ssb_bus *bus);
+ 
+ /* Set a fallback SPROM.
+  * See kdoc at the function definition for complete documentation. */
+-extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
++extern int ssb_arch_register_fallback_sprom(
++		int (*sprom_callback)(struct ssb_bus *bus,
++		struct ssb_sprom *out));
+ 
+ /* Suspend a SSB bus.
+  * Call this from the parent bus suspend routine. */
+@@ -518,6 +522,7 @@ extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
+  * Otherwise static always-on powercontrol will be used. */
+ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
+ 
++extern void ssb_commit_settings(struct ssb_bus *bus);
+ 
+ /* Various helper functions */
+ extern u32 ssb_admatch_base(u32 adm);
+diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h
+index 2cdf249..a08d693 100644
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
+@@ -123,6 +123,8 @@
+ #define SSB_CHIPCO_FLASHDATA		0x0048
+ #define SSB_CHIPCO_BCAST_ADDR		0x0050
+ #define SSB_CHIPCO_BCAST_DATA		0x0054
++#define SSB_CHIPCO_GPIOPULLUP		0x0058		/* Rev >= 20 only */
++#define SSB_CHIPCO_GPIOPULLDOWN		0x005C		/* Rev >= 20 only */
+ #define SSB_CHIPCO_GPIOIN		0x0060
+ #define SSB_CHIPCO_GPIOOUT		0x0064
+ #define SSB_CHIPCO_GPIOOUTEN		0x0068
+@@ -131,6 +133,9 @@
+ #define SSB_CHIPCO_GPIOIRQ		0x0074
+ #define SSB_CHIPCO_WATCHDOG		0x0080
+ #define SSB_CHIPCO_GPIOTIMER		0x0088		/* LED powersave (corerev >= 16) */
++#define  SSB_CHIPCO_GPIOTIMER_OFFTIME	0x0000FFFF
++#define  SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT	0
++#define  SSB_CHIPCO_GPIOTIMER_ONTIME	0xFFFF0000
+ #define  SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT	16
+ #define SSB_CHIPCO_GPIOTOUTM		0x008C		/* LED powersave (corerev >= 16) */
+ #define SSB_CHIPCO_CLOCK_N		0x0090
+@@ -189,8 +194,10 @@
+ #define  SSB_CHIPCO_CLKCTLST_HAVEALPREQ	0x00000008 /* ALP available request */
+ #define  SSB_CHIPCO_CLKCTLST_HAVEHTREQ	0x00000010 /* HT available request */
+ #define  SSB_CHIPCO_CLKCTLST_HWCROFF	0x00000020 /* Force HW clock request off */
+-#define  SSB_CHIPCO_CLKCTLST_HAVEHT	0x00010000 /* HT available */
+-#define  SSB_CHIPCO_CLKCTLST_HAVEALP	0x00020000 /* APL available */
++#define  SSB_CHIPCO_CLKCTLST_HAVEALP	0x00010000 /* ALP available */
++#define  SSB_CHIPCO_CLKCTLST_HAVEHT	0x00020000 /* HT available */
++#define  SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT	0x00010000 /* 4328a0 has reversed bits */
++#define  SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP	0x00020000 /* 4328a0 has reversed bits */
+ #define SSB_CHIPCO_HW_WORKAROUND	0x01E4 /* Hardware workaround (rev >= 20) */
+ #define SSB_CHIPCO_UART0_DATA		0x0300
+ #define SSB_CHIPCO_UART0_IMR		0x0304
+diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
+index 402955a..efbf459 100644
+--- a/include/linux/ssb/ssb_regs.h
++++ b/include/linux/ssb/ssb_regs.h
+@@ -97,7 +97,7 @@
+ #define  SSB_INTVEC_ENET1	0x00000040 /* Enable interrupts for enet 1 */
+ #define SSB_TMSLOW		0x0F98     /* SB Target State Low */
+ #define  SSB_TMSLOW_RESET	0x00000001 /* Reset */
+-#define  SSB_TMSLOW_REJECT_22	0x00000002 /* Reject (Backplane rev 2.2) */
++#define  SSB_TMSLOW_REJECT	0x00000002 /* Reject (Standard Backplane) */
+ #define  SSB_TMSLOW_REJECT_23	0x00000004 /* Reject (Backplane rev 2.3) */
+ #define  SSB_TMSLOW_CLOCK	0x00010000 /* Clock Enable */
+ #define  SSB_TMSLOW_FGC		0x00020000 /* Force Gated Clocks On */
diff --git a/target/linux/generic/patches-2.6.38/021-ssb_commit_settings_export.patch b/target/linux/generic/patches-2.6.38/021-ssb_commit_settings_export.patch
deleted file mode 100644
index 657fdd6b92..0000000000
--- a/target/linux/generic/patches-2.6.38/021-ssb_commit_settings_export.patch
+++ /dev/null
@@ -1,77 +0,0 @@
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s
- 	pcicore_write32(pc, mdio_control, 0);
- }
- 
--static void ssb_broadcast_value(struct ssb_device *dev,
--				u32 address, u32 data)
--{
--	/* This is used for both, PCI and ChipCommon core, so be careful. */
--	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
--	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
--
--	ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
--	ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
--	ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
--	ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
--}
--
--static void ssb_commit_settings(struct ssb_bus *bus)
--{
--	struct ssb_device *dev;
--
--	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
--	if (WARN_ON(!dev))
--		return;
--	/* This forces an update of the cached registers. */
--	ssb_broadcast_value(dev, 0xFD8, 0);
--}
--
- int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
- 				   struct ssb_device *dev)
- {
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -1330,6 +1330,31 @@ error:
- }
- EXPORT_SYMBOL(ssb_bus_powerup);
- 
-+static void ssb_broadcast_value(struct ssb_device *dev,
-+				u32 address, u32 data)
-+{
-+	/* This is used for both, PCI and ChipCommon core, so be careful. */
-+	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
-+	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
-+
-+	ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
-+	ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
-+	ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
-+	ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
-+}
-+
-+void ssb_commit_settings(struct ssb_bus *bus)
-+{
-+	struct ssb_device *dev;
-+
-+	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
-+	if (WARN_ON(!dev))
-+		return;
-+	/* This forces an update of the cached registers. */
-+	ssb_broadcast_value(dev, 0xFD8, 0);
-+}
-+EXPORT_SYMBOL(ssb_commit_settings);
-+
- u32 ssb_admatch_base(u32 adm)
- {
- 	u32 base = 0;
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -518,6 +518,7 @@ extern int ssb_bus_may_powerdown(struct
-  * Otherwise static always-on powercontrol will be used. */
- extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
- 
-+extern void ssb_commit_settings(struct ssb_bus *bus);
- 
- /* Various helper functions */
- extern u32 ssb_admatch_base(u32 adm);
diff --git a/target/linux/generic/patches-2.6.38/025-bcma_backport.patch b/target/linux/generic/patches-2.6.38/025-bcma_backport.patch
new file mode 100644
index 0000000000..b36bb5f8e1
--- /dev/null
+++ b/target/linux/generic/patches-2.6.38/025-bcma_backport.patch
@@ -0,0 +1,2715 @@
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-bus-bcma
+@@ -0,0 +1,31 @@
++What:		/sys/bus/bcma/devices/.../manuf
++Date:		May 2011
++KernelVersion:	2.6.40
++Contact:	Rafał Miłecki <zajec5@gmail.com>
++Description:
++		Each BCMA core has it's manufacturer id. See
++		include/linux/bcma/bcma.h for possible values.
++
++What:		/sys/bus/bcma/devices/.../id
++Date:		May 2011
++KernelVersion:	2.6.40
++Contact:	Rafał Miłecki <zajec5@gmail.com>
++Description:
++		There are a few types of BCMA cores, they can be identified by
++		id field.
++
++What:		/sys/bus/bcma/devices/.../rev
++Date:		May 2011
++KernelVersion:	2.6.40
++Contact:	Rafał Miłecki <zajec5@gmail.com>
++Description:
++		BCMA cores of the same type can still slightly differ depending
++		on their revision. Use it for detailed programming.
++
++What:		/sys/bus/bcma/devices/.../class
++Date:		May 2011
++KernelVersion:	2.6.40
++Contact:	Rafał Miłecki <zajec5@gmail.com>
++Description:
++		Each BCMA core is identified by few fields, including class it
++		belongs to. See include/linux/bcma/bcma.h for possible values.
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -5832,6 +5832,13 @@ S:	Maintained
+ F:	drivers/ssb/
+ F:	include/linux/ssb/
+ 
++BROADCOM SPECIFIC AMBA DRIVER (BCMA)
++M:	Rafał Miłecki <zajec5@gmail.com>
++L:	linux-wireless@vger.kernel.org
++S:	Maintained
++F:	drivers/bcma/
++F:	include/linux/bcma/
++
+ SONY VAIO CONTROL DEVICE DRIVER
+ M:	Mattia Dongili <malattia@linux.it>
+ L:	platform-driver-x86@vger.kernel.org
+--- a/drivers/Kconfig
++++ b/drivers/Kconfig
+@@ -68,6 +68,8 @@ source "drivers/watchdog/Kconfig"
+ 
+ source "drivers/ssb/Kconfig"
+ 
++source "drivers/bcma/Kconfig"
++
+ source "drivers/mfd/Kconfig"
+ 
+ source "drivers/regulator/Kconfig"
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -110,6 +110,7 @@ obj-$(CONFIG_HID)		+= hid/
+ obj-$(CONFIG_PPC_PS3)		+= ps3/
+ obj-$(CONFIG_OF)		+= of/
+ obj-$(CONFIG_SSB)		+= ssb/
++obj-$(CONFIG_BCMA)		+= bcma/
+ obj-$(CONFIG_VHOST_NET)		+= vhost/
+ obj-$(CONFIG_VLYNQ)		+= vlynq/
+ obj-$(CONFIG_STAGING)		+= staging/
+--- /dev/null
++++ b/drivers/bcma/Kconfig
+@@ -0,0 +1,44 @@
++config BCMA_POSSIBLE
++	bool
++	depends on HAS_IOMEM && HAS_DMA
++	default y
++
++menu "Broadcom specific AMBA"
++	depends on BCMA_POSSIBLE
++
++config BCMA
++	tristate "BCMA support"
++	depends on BCMA_POSSIBLE
++	help
++	  Bus driver for Broadcom specific Advanced Microcontroller Bus
++	  Architecture.
++
++# Support for Block-I/O. SELECT this from the driver that needs it.
++config BCMA_BLOCKIO
++	bool
++	depends on BCMA
++
++config BCMA_HOST_PCI_POSSIBLE
++	bool
++	depends on BCMA && PCI = y
++	default y
++
++config BCMA_HOST_PCI
++	bool "Support for BCMA on PCI-host bus"
++	depends on BCMA_HOST_PCI_POSSIBLE
++
++config BCMA_DRIVER_PCI_HOSTMODE
++	bool "Driver for PCI core working in hostmode"
++	depends on BCMA && MIPS
++	help
++	  PCI core hostmode operation (external PCI bus).
++
++config BCMA_DEBUG
++	bool "BCMA debugging"
++	depends on BCMA
++	help
++	  This turns on additional debugging messages.
++
++	  If unsure, say N
++
++endmenu
+--- /dev/null
++++ b/drivers/bcma/Makefile
+@@ -0,0 +1,8 @@
++bcma-y					+= main.o scan.o core.o sprom.o
++bcma-y					+= driver_chipcommon.o driver_chipcommon_pmu.o
++bcma-y					+= driver_pci.o
++bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE)	+= driver_pci_host.o
++bcma-$(CONFIG_BCMA_HOST_PCI)		+= host_pci.o
++obj-$(CONFIG_BCMA)			+= bcma.o
++
++ccflags-$(CONFIG_BCMA_DEBUG)		:= -DDEBUG
+--- /dev/null
++++ b/drivers/bcma/README
+@@ -0,0 +1,19 @@
++Broadcom introduced new bus as replacement for older SSB. It is based on AMBA,
++however from programming point of view there is nothing AMBA specific we use.
++
++Standard AMBA drivers are platform specific, have hardcoded addresses and use
++AMBA standard fields like CID and PID.
++
++In case of Broadcom's cards every device consists of:
++1) Broadcom specific AMBA device. It is put on AMBA bus, but can not be treated
++   as standard AMBA device. Reading it's CID or PID can cause machine lockup.
++2) AMBA standard devices called ports or wrappers. They have CIDs (AMBA_CID)
++   and PIDs (0x103BB369), but we do not use that info for anything. One of that
++   devices is used for managing Broadcom specific core.
++
++Addresses of AMBA devices are not hardcoded in driver and have to be read from
++EPROM.
++
++In this situation we decided to introduce separated bus. It can contain up to
++16 devices identified by Broadcom specific fields: manufacturer, id, revision
++and class.
+--- /dev/null
++++ b/drivers/bcma/TODO
+@@ -0,0 +1,3 @@
++- Interrupts
++- Defines for PCI core driver
++- Create kernel Documentation (use info from README)
+--- /dev/null
++++ b/drivers/bcma/bcma_private.h
+@@ -0,0 +1,35 @@
++#ifndef LINUX_BCMA_PRIVATE_H_
++#define LINUX_BCMA_PRIVATE_H_
++
++#ifndef pr_fmt
++#define pr_fmt(fmt)		KBUILD_MODNAME ": " fmt
++#endif
++
++#include <linux/bcma/bcma.h>
++#include <linux/delay.h>
++
++#define BCMA_CORE_SIZE		0x1000
++
++struct bcma_bus;
++
++/* main.c */
++int bcma_bus_register(struct bcma_bus *bus);
++void bcma_bus_unregister(struct bcma_bus *bus);
++
++/* scan.c */
++int bcma_bus_scan(struct bcma_bus *bus);
++
++/* sprom.c */
++int bcma_sprom_get(struct bcma_bus *bus);
++
++#ifdef CONFIG_BCMA_HOST_PCI
++/* host_pci.c */
++extern int __init bcma_host_pci_init(void);
++extern void __exit bcma_host_pci_exit(void);
++#endif /* CONFIG_BCMA_HOST_PCI */
++
++#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
++void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
++#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
++
++#endif
+--- /dev/null
++++ b/drivers/bcma/core.c
+@@ -0,0 +1,124 @@
++/*
++ * Broadcom specific AMBA
++ * Core ops
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/bcma/bcma.h>
++
++bool bcma_core_is_enabled(struct bcma_device *core)
++{
++	if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
++	    != BCMA_IOCTL_CLK)
++		return false;
++	if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
++		return false;
++	return true;
++}
++EXPORT_SYMBOL_GPL(bcma_core_is_enabled);
++
++void bcma_core_disable(struct bcma_device *core, u32 flags)
++{
++	if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
++		return;
++
++	bcma_awrite32(core, BCMA_IOCTL, flags);
++	bcma_aread32(core, BCMA_IOCTL);
++	udelay(10);
++
++	bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
++	udelay(1);
++}
++EXPORT_SYMBOL_GPL(bcma_core_disable);
++
++int bcma_core_enable(struct bcma_device *core, u32 flags)
++{
++	bcma_core_disable(core, flags);
++
++	bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC | flags));
++	bcma_aread32(core, BCMA_IOCTL);
++
++	bcma_awrite32(core, BCMA_RESET_CTL, 0);
++	udelay(1);
++
++	bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
++	bcma_aread32(core, BCMA_IOCTL);
++	udelay(1);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(bcma_core_enable);
++
++void bcma_core_set_clockmode(struct bcma_device *core,
++			     enum bcma_clkmode clkmode)
++{
++	u16 i;
++
++	WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON &&
++		core->id.id != BCMA_CORE_PCIE &&
++		core->id.id != BCMA_CORE_80211);
++
++	switch (clkmode) {
++	case BCMA_CLKMODE_FAST:
++		bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
++		udelay(64);
++		for (i = 0; i < 1500; i++) {
++			if (bcma_read32(core, BCMA_CLKCTLST) &
++			    BCMA_CLKCTLST_HAVEHT) {
++				i = 0;
++				break;
++			}
++			udelay(10);
++		}
++		if (i)
++			pr_err("HT force timeout\n");
++		break;
++	case BCMA_CLKMODE_DYNAMIC:
++		pr_warn("Dynamic clockmode not supported yet!\n");
++		break;
++	}
++}
++EXPORT_SYMBOL_GPL(bcma_core_set_clockmode);
++
++void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
++{
++	u16 i;
++
++	WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ);
++	WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST);
++
++	if (on) {
++		bcma_set32(core, BCMA_CLKCTLST, req);
++		for (i = 0; i < 10000; i++) {
++			if ((bcma_read32(core, BCMA_CLKCTLST) & status) ==
++			    status) {
++				i = 0;
++				break;
++			}
++			udelay(10);
++		}
++		if (i)
++			pr_err("PLL enable timeout\n");
++	} else {
++		pr_warn("Disabling PLL not supported yet!\n");
++	}
++}
++EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
++
++u32 bcma_core_dma_translation(struct bcma_device *core)
++{
++	switch (core->bus->hosttype) {
++	case BCMA_HOSTTYPE_PCI:
++		if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
++			return BCMA_DMA_TRANSLATION_DMA64_CMT;
++		else
++			return BCMA_DMA_TRANSLATION_DMA32_CMT;
++	default:
++		pr_err("DMA translation unknown for host %d\n",
++		       core->bus->hosttype);
++	}
++	return BCMA_DMA_TRANSLATION_NONE;
++}
++EXPORT_SYMBOL(bcma_core_dma_translation);
+--- /dev/null
++++ b/drivers/bcma/driver_chipcommon.c
+@@ -0,0 +1,103 @@
++/*
++ * Broadcom specific AMBA
++ * ChipCommon core driver
++ *
++ * Copyright 2005, Broadcom Corporation
++ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/bcma/bcma.h>
++
++static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
++					 u32 mask, u32 value)
++{
++	value &= mask;
++	value |= bcma_cc_read32(cc, offset) & ~mask;
++	bcma_cc_write32(cc, offset, value);
++
++	return value;
++}
++
++void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
++{
++	u32 leddc_on = 10;
++	u32 leddc_off = 90;
++
++	if (cc->core->id.rev >= 11)
++		cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
++	cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
++	if (cc->core->id.rev >= 35)
++		cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
++
++	if (cc->core->id.rev >= 20) {
++		bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
++		bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
++	}
++
++	if (cc->capabilities & BCMA_CC_CAP_PMU)
++		bcma_pmu_init(cc);
++	if (cc->capabilities & BCMA_CC_CAP_PCTL)
++		pr_err("Power control not implemented!\n");
++
++	if (cc->core->id.rev >= 16) {
++		if (cc->core->bus->sprom.leddc_on_time &&
++		    cc->core->bus->sprom.leddc_off_time) {
++			leddc_on = cc->core->bus->sprom.leddc_on_time;
++			leddc_off = cc->core->bus->sprom.leddc_off_time;
++		}
++		bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
++			((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
++			 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
++	}
++}
++
++/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
++void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
++{
++	/* instant NMI */
++	bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
++}
++
++void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
++{
++	bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
++}
++
++u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
++{
++	return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
++}
++
++u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
++{
++	return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
++}
++
++u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
++{
++	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
++}
++
++u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
++{
++	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
++}
++
++u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
++{
++	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
++}
++EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
++
++u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
++{
++	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
++}
++
++u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
++{
++	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
++}
+--- /dev/null
++++ b/drivers/bcma/driver_chipcommon_pmu.c
+@@ -0,0 +1,138 @@
++/*
++ * Broadcom specific AMBA
++ * ChipCommon Power Management Unit driver
++ *
++ * Copyright 2009, Michael Buesch <mb@bu3sch.de>
++ * Copyright 2007, Broadcom Corporation
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/bcma/bcma.h>
++
++static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
++					u32 offset, u32 mask, u32 set)
++{
++	u32 value;
++
++	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
++	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
++	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
++	value = bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
++	value &= mask;
++	value |= set;
++	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_DATA, value);
++	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
++}
++
++static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
++{
++	struct bcma_bus *bus = cc->core->bus;
++
++	switch (bus->chipinfo.id) {
++	case 0x4313:
++	case 0x4331:
++	case 43224:
++	case 43225:
++		break;
++	default:
++		pr_err("PLL init unknown for device 0x%04X\n",
++			bus->chipinfo.id);
++	}
++}
++
++static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
++{
++	struct bcma_bus *bus = cc->core->bus;
++	u32 min_msk = 0, max_msk = 0;
++
++	switch (bus->chipinfo.id) {
++	case 0x4313:
++		min_msk = 0x200D;
++		max_msk = 0xFFFF;
++		break;
++	case 43224:
++	case 43225:
++		break;
++	default:
++		pr_err("PMU resource config unknown for device 0x%04X\n",
++			bus->chipinfo.id);
++	}
++
++	/* Set the resource masks. */
++	if (min_msk)
++		bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
++	if (max_msk)
++		bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
++}
++
++void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
++{
++	struct bcma_bus *bus = cc->core->bus;
++
++	switch (bus->chipinfo.id) {
++	case 0x4313:
++	case 0x4331:
++	case 43224:
++	case 43225:
++		break;
++	default:
++		pr_err("PMU switch/regulators init unknown for device "
++			"0x%04X\n", bus->chipinfo.id);
++	}
++}
++
++void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
++{
++	struct bcma_bus *bus = cc->core->bus;
++
++	switch (bus->chipinfo.id) {
++	case 0x4313:
++		bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
++		break;
++	case 0x4331:
++		pr_err("Enabling Ext PA lines not implemented\n");
++		break;
++	case 43224:
++		if (bus->chipinfo.rev == 0) {
++			pr_err("Workarounds for 43224 rev 0 not fully "
++				"implemented\n");
++			bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
++		} else {
++			bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
++		}
++		break;
++	case 43225:
++		break;
++	default:
++		pr_err("Workarounds unknown for device 0x%04X\n",
++			bus->chipinfo.id);
++	}
++}
++
++void bcma_pmu_init(struct bcma_drv_cc *cc)
++{
++	u32 pmucap;
++
++	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
++	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
++
++	pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
++		 pmucap);
++
++	if (cc->pmu.rev == 1)
++		bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
++			      ~BCMA_CC_PMU_CTL_NOILPONW);
++	else
++		bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
++			     BCMA_CC_PMU_CTL_NOILPONW);
++
++	if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
++		pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
++
++	bcma_pmu_pll_init(cc);
++	bcma_pmu_resources_init(cc);
++	bcma_pmu_swreg_init(cc);
++	bcma_pmu_workarounds(cc);
++}
+--- /dev/null
++++ b/drivers/bcma/driver_pci.c
+@@ -0,0 +1,223 @@
++/*
++ * Broadcom specific AMBA
++ * PCI Core
++ *
++ * Copyright 2005, Broadcom Corporation
++ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/bcma/bcma.h>
++
++/**************************************************
++ * R/W ops.
++ **************************************************/
++
++static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
++{
++	pcicore_write32(pc, 0x130, address);
++	pcicore_read32(pc, 0x130);
++	return pcicore_read32(pc, 0x134);
++}
++
++#if 0
++static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
++{
++	pcicore_write32(pc, 0x130, address);
++	pcicore_read32(pc, 0x130);
++	pcicore_write32(pc, 0x134, data);
++}
++#endif
++
++static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
++{
++	const u16 mdio_control = 0x128;
++	const u16 mdio_data = 0x12C;
++	u32 v;
++	int i;
++
++	v = (1 << 30); /* Start of Transaction */
++	v |= (1 << 28); /* Write Transaction */
++	v |= (1 << 17); /* Turnaround */
++	v |= (0x1F << 18);
++	v |= (phy << 4);
++	pcicore_write32(pc, mdio_data, v);
++
++	udelay(10);
++	for (i = 0; i < 200; i++) {
++		v = pcicore_read32(pc, mdio_control);
++		if (v & 0x100 /* Trans complete */)
++			break;
++		msleep(1);
++	}
++}
++
++static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
++{
++	const u16 mdio_control = 0x128;
++	const u16 mdio_data = 0x12C;
++	int max_retries = 10;
++	u16 ret = 0;
++	u32 v;
++	int i;
++
++	v = 0x80; /* Enable Preamble Sequence */
++	v |= 0x2; /* MDIO Clock Divisor */
++	pcicore_write32(pc, mdio_control, v);
++
++	if (pc->core->id.rev >= 10) {
++		max_retries = 200;
++		bcma_pcie_mdio_set_phy(pc, device);
++	}
++
++	v = (1 << 30); /* Start of Transaction */
++	v |= (1 << 29); /* Read Transaction */
++	v |= (1 << 17); /* Turnaround */
++	if (pc->core->id.rev < 10)
++		v |= (u32)device << 22;
++	v |= (u32)address << 18;
++	pcicore_write32(pc, mdio_data, v);
++	/* Wait for the device to complete the transaction */
++	udelay(10);
++	for (i = 0; i < max_retries; i++) {
++		v = pcicore_read32(pc, mdio_control);
++		if (v & 0x100 /* Trans complete */) {
++			udelay(10);
++			ret = pcicore_read32(pc, mdio_data);
++			break;
++		}
++		msleep(1);
++	}
++	pcicore_write32(pc, mdio_control, 0);
++	return ret;
++}
++
++static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
++				u8 address, u16 data)
++{
++	const u16 mdio_control = 0x128;
++	const u16 mdio_data = 0x12C;
++	int max_retries = 10;
++	u32 v;
++	int i;
++
++	v = 0x80; /* Enable Preamble Sequence */
++	v |= 0x2; /* MDIO Clock Divisor */
++	pcicore_write32(pc, mdio_control, v);
++
++	if (pc->core->id.rev >= 10) {
++		max_retries = 200;
++		bcma_pcie_mdio_set_phy(pc, device);
++	}
++
++	v = (1 << 30); /* Start of Transaction */
++	v |= (1 << 28); /* Write Transaction */
++	v |= (1 << 17); /* Turnaround */
++	if (pc->core->id.rev < 10)
++		v |= (u32)device << 22;
++	v |= (u32)address << 18;
++	v |= data;
++	pcicore_write32(pc, mdio_data, v);
++	/* Wait for the device to complete the transaction */
++	udelay(10);
++	for (i = 0; i < max_retries; i++) {
++		v = pcicore_read32(pc, mdio_control);
++		if (v & 0x100 /* Trans complete */)
++			break;
++		msleep(1);
++	}
++	pcicore_write32(pc, mdio_control, 0);
++}
++
++/**************************************************
++ * Workarounds.
++ **************************************************/
++
++static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
++{
++	return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
++}
++
++static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
++{
++	const u8 serdes_pll_device = 0x1D;
++	const u8 serdes_rx_device = 0x1F;
++	u16 tmp;
++
++	bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
++			      bcma_pcicore_polarity_workaround(pc));
++	tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
++	if (tmp & 0x4000)
++		bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
++}
++
++/**************************************************
++ * Init.
++ **************************************************/
++
++static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
++{
++	bcma_pcicore_serdes_workaround(pc);
++}
++
++static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
++{
++	struct bcma_bus *bus = pc->core->bus;
++	u16 chipid_top;
++
++	chipid_top = (bus->chipinfo.id & 0xFF00);
++	if (chipid_top != 0x4700 &&
++	    chipid_top != 0x5300)
++		return false;
++
++	if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
++		return false;
++
++#if 0
++	/* TODO: on BCMA we use address from EROM instead of magic formula */
++	u32 tmp;
++	return !mips_busprobe32(tmp, (bus->mmio +
++		(pc->core->core_index * BCMA_CORE_SIZE)));
++#endif
++
++	return true;
++}
++
++void bcma_core_pci_init(struct bcma_drv_pci *pc)
++{
++	if (bcma_core_pci_is_in_hostmode(pc)) {
++#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
++		bcma_core_pci_hostmode_init(pc);
++#else
++		pr_err("Driver compiled without support for hostmode PCI\n");
++#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
++	} else {
++		bcma_core_pci_clientmode_init(pc);
++	}
++}
++
++int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
++			  bool enable)
++{
++	struct pci_dev *pdev = pc->core->bus->host_pci;
++	u32 coremask, tmp;
++	int err;
++
++	err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
++	if (err)
++		goto out;
++
++	coremask = BIT(core->core_index) << 8;
++	if (enable)
++		tmp |= coremask;
++	else
++		tmp &= ~coremask;
++
++	err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
++
++out:
++	return err;
++}
++EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
+--- /dev/null
++++ b/drivers/bcma/host_pci.c
+@@ -0,0 +1,251 @@
++/*
++ * Broadcom specific AMBA
++ * PCI Host
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/slab.h>
++#include <linux/bcma/bcma.h>
++#include <linux/pci.h>
++
++static void bcma_host_pci_switch_core(struct bcma_device *core)
++{
++	pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN,
++			       core->addr);
++	pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
++			       core->wrap);
++	core->bus->mapped_core = core;
++	pr_debug("Switched to core: 0x%X\n", core->id.id);
++}
++
++static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
++{
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	return ioread8(core->bus->mmio + offset);
++}
++
++static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
++{
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	return ioread16(core->bus->mmio + offset);
++}
++
++static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
++{
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	return ioread32(core->bus->mmio + offset);
++}
++
++static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
++				 u8 value)
++{
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	iowrite8(value, core->bus->mmio + offset);
++}
++
++static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
++				 u16 value)
++{
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	iowrite16(value, core->bus->mmio + offset);
++}
++
++static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
++				 u32 value)
++{
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	iowrite32(value, core->bus->mmio + offset);
++}
++
++#ifdef CONFIG_BCMA_BLOCKIO
++void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
++			      size_t count, u16 offset, u8 reg_width)
++{
++	void __iomem *addr = core->bus->mmio + offset;
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	switch (reg_width) {
++	case sizeof(u8):
++		ioread8_rep(addr, buffer, count);
++		break;
++	case sizeof(u16):
++		WARN_ON(count & 1);
++		ioread16_rep(addr, buffer, count >> 1);
++		break;
++	case sizeof(u32):
++		WARN_ON(count & 3);
++		ioread32_rep(addr, buffer, count >> 2);
++		break;
++	default:
++		WARN_ON(1);
++	}
++}
++
++void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
++			       size_t count, u16 offset, u8 reg_width)
++{
++	void __iomem *addr = core->bus->mmio + offset;
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	switch (reg_width) {
++	case sizeof(u8):
++		iowrite8_rep(addr, buffer, count);
++		break;
++	case sizeof(u16):
++		WARN_ON(count & 1);
++		iowrite16_rep(addr, buffer, count >> 1);
++		break;
++	case sizeof(u32):
++		WARN_ON(count & 3);
++		iowrite32_rep(addr, buffer, count >> 2);
++		break;
++	default:
++		WARN_ON(1);
++	}
++}
++#endif
++
++static u32 bcma_host_pci_aread32(struct bcma_device *core, u16 offset)
++{
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
++}
++
++static void bcma_host_pci_awrite32(struct bcma_device *core, u16 offset,
++				  u32 value)
++{
++	if (core->bus->mapped_core != core)
++		bcma_host_pci_switch_core(core);
++	iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
++}
++
++const struct bcma_host_ops bcma_host_pci_ops = {
++	.read8		= bcma_host_pci_read8,
++	.read16		= bcma_host_pci_read16,
++	.read32		= bcma_host_pci_read32,
++	.write8		= bcma_host_pci_write8,
++	.write16	= bcma_host_pci_write16,
++	.write32	= bcma_host_pci_write32,
++#ifdef CONFIG_BCMA_BLOCKIO
++	.block_read	= bcma_host_pci_block_read,
++	.block_write	= bcma_host_pci_block_write,
++#endif
++	.aread32	= bcma_host_pci_aread32,
++	.awrite32	= bcma_host_pci_awrite32,
++};
++
++static int bcma_host_pci_probe(struct pci_dev *dev,
++			     const struct pci_device_id *id)
++{
++	struct bcma_bus *bus;
++	int err = -ENOMEM;
++	const char *name;
++	u32 val;
++
++	/* Alloc */
++	bus = kzalloc(sizeof(*bus), GFP_KERNEL);
++	if (!bus)
++		goto out;
++
++	/* Basic PCI configuration */
++	err = pci_enable_device(dev);
++	if (err)
++		goto err_kfree_bus;
++
++	name = dev_name(&dev->dev);
++	if (dev->driver && dev->driver->name)
++		name = dev->driver->name;
++	err = pci_request_regions(dev, name);
++	if (err)
++		goto err_pci_disable;
++	pci_set_master(dev);
++
++	/* Disable the RETRY_TIMEOUT register (0x41) to keep
++	 * PCI Tx retries from interfering with C3 CPU state */
++	pci_read_config_dword(dev, 0x40, &val);
++	if ((val & 0x0000ff00) != 0)
++		pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
++
++	/* SSB needed additional powering up, do we have any AMBA PCI cards? */
++	if (!pci_is_pcie(dev))
++		pr_err("PCI card detected, report problems.\n");
++
++	/* Map MMIO */
++	err = -ENOMEM;
++	bus->mmio = pci_iomap(dev, 0, ~0UL);
++	if (!bus->mmio)
++		goto err_pci_release_regions;
++
++	/* Host specific */
++	bus->host_pci = dev;
++	bus->hosttype = BCMA_HOSTTYPE_PCI;
++	bus->ops = &bcma_host_pci_ops;
++
++	/* Register */
++	err = bcma_bus_register(bus);
++	if (err)
++		goto err_pci_unmap_mmio;
++
++	pci_set_drvdata(dev, bus);
++
++out:
++	return err;
++
++err_pci_unmap_mmio:
++	pci_iounmap(dev, bus->mmio);
++err_pci_release_regions:
++	pci_release_regions(dev);
++err_pci_disable:
++	pci_disable_device(dev);
++err_kfree_bus:
++	kfree(bus);
++	return err;
++}
++
++static void bcma_host_pci_remove(struct pci_dev *dev)
++{
++	struct bcma_bus *bus = pci_get_drvdata(dev);
++
++	bcma_bus_unregister(bus);
++	pci_iounmap(dev, bus->mmio);
++	pci_release_regions(dev);
++	pci_disable_device(dev);
++	kfree(bus);
++	pci_set_drvdata(dev, NULL);
++}
++
++static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
++	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
++	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
++	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
++	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
++	{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
++	{ 0, },
++};
++MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
++
++static struct pci_driver bcma_pci_bridge_driver = {
++	.name = "bcma-pci-bridge",
++	.id_table = bcma_pci_bridge_tbl,
++	.probe = bcma_host_pci_probe,
++	.remove = bcma_host_pci_remove,
++};
++
++int __init bcma_host_pci_init(void)
++{
++	return pci_register_driver(&bcma_pci_bridge_driver);
++}
++
++void __exit bcma_host_pci_exit(void)
++{
++	pci_unregister_driver(&bcma_pci_bridge_driver);
++}
+--- /dev/null
++++ b/drivers/bcma/main.c
+@@ -0,0 +1,257 @@
++/*
++ * Broadcom specific AMBA
++ * Bus subsystem
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/bcma/bcma.h>
++#include <linux/slab.h>
++
++MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
++MODULE_LICENSE("GPL");
++
++static int bcma_bus_match(struct device *dev, struct device_driver *drv);
++static int bcma_device_probe(struct device *dev);
++static int bcma_device_remove(struct device *dev);
++
++static ssize_t manuf_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct bcma_device *core = container_of(dev, struct bcma_device, dev);
++	return sprintf(buf, "0x%03X\n", core->id.manuf);
++}
++static ssize_t id_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct bcma_device *core = container_of(dev, struct bcma_device, dev);
++	return sprintf(buf, "0x%03X\n", core->id.id);
++}
++static ssize_t rev_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct bcma_device *core = container_of(dev, struct bcma_device, dev);
++	return sprintf(buf, "0x%02X\n", core->id.rev);
++}
++static ssize_t class_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	struct bcma_device *core = container_of(dev, struct bcma_device, dev);
++	return sprintf(buf, "0x%X\n", core->id.class);
++}
++static struct device_attribute bcma_device_attrs[] = {
++	__ATTR_RO(manuf),
++	__ATTR_RO(id),
++	__ATTR_RO(rev),
++	__ATTR_RO(class),
++	__ATTR_NULL,
++};
++
++static struct bus_type bcma_bus_type = {
++	.name		= "bcma",
++	.match		= bcma_bus_match,
++	.probe		= bcma_device_probe,
++	.remove		= bcma_device_remove,
++	.dev_attrs	= bcma_device_attrs,
++};
++
++static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
++{
++	struct bcma_device *core;
++
++	list_for_each_entry(core, &bus->cores, list) {
++		if (core->id.id == coreid)
++			return core;
++	}
++	return NULL;
++}
++
++static void bcma_release_core_dev(struct device *dev)
++{
++	struct bcma_device *core = container_of(dev, struct bcma_device, dev);
++	kfree(core);
++}
++
++static int bcma_register_cores(struct bcma_bus *bus)
++{
++	struct bcma_device *core;
++	int err, dev_id = 0;
++
++	list_for_each_entry(core, &bus->cores, list) {
++		/* We support that cores ourself */
++		switch (core->id.id) {
++		case BCMA_CORE_CHIPCOMMON:
++		case BCMA_CORE_PCI:
++		case BCMA_CORE_PCIE:
++			continue;
++		}
++
++		core->dev.release = bcma_release_core_dev;
++		core->dev.bus = &bcma_bus_type;
++		dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
++
++		switch (bus->hosttype) {
++		case BCMA_HOSTTYPE_PCI:
++			core->dev.parent = &bus->host_pci->dev;
++			core->dma_dev = &bus->host_pci->dev;
++			core->irq = bus->host_pci->irq;
++			break;
++		case BCMA_HOSTTYPE_NONE:
++		case BCMA_HOSTTYPE_SDIO:
++			break;
++		}
++
++		err = device_register(&core->dev);
++		if (err) {
++			pr_err("Could not register dev for core 0x%03X\n",
++			       core->id.id);
++			continue;
++		}
++		core->dev_registered = true;
++		dev_id++;
++	}
++
++	return 0;
++}
++
++static void bcma_unregister_cores(struct bcma_bus *bus)
++{
++	struct bcma_device *core;
++
++	list_for_each_entry(core, &bus->cores, list) {
++		if (core->dev_registered)
++			device_unregister(&core->dev);
++	}
++}
++
++int bcma_bus_register(struct bcma_bus *bus)
++{
++	int err;
++	struct bcma_device *core;
++
++	/* Scan for devices (cores) */
++	err = bcma_bus_scan(bus);
++	if (err) {
++		pr_err("Failed to scan: %d\n", err);
++		return -1;
++	}
++
++	/* Init CC core */
++	core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
++	if (core) {
++		bus->drv_cc.core = core;
++		bcma_core_chipcommon_init(&bus->drv_cc);
++	}
++
++	/* Init PCIE core */
++	core = bcma_find_core(bus, BCMA_CORE_PCIE);
++	if (core) {
++		bus->drv_pci.core = core;
++		bcma_core_pci_init(&bus->drv_pci);
++	}
++
++	/* Try to get SPROM */
++	err = bcma_sprom_get(bus);
++	if (err == -ENOENT) {
++		pr_err("No SPROM available\n");
++	} else if (err) {
++		pr_err("Failed to get SPROM: %d\n", err);
++		return -ENOENT;
++	}
++
++	/* Register found cores */
++	bcma_register_cores(bus);
++
++	pr_info("Bus registered\n");
++
++	return 0;
++}
++
++void bcma_bus_unregister(struct bcma_bus *bus)
++{
++	bcma_unregister_cores(bus);
++}
++
++int __bcma_driver_register(struct bcma_driver *drv, struct module *owner)
++{
++	drv->drv.name = drv->name;
++	drv->drv.bus = &bcma_bus_type;
++	drv->drv.owner = owner;
++
++	return driver_register(&drv->drv);
++}
++EXPORT_SYMBOL_GPL(__bcma_driver_register);
++
++void bcma_driver_unregister(struct bcma_driver *drv)
++{
++	driver_unregister(&drv->drv);
++}
++EXPORT_SYMBOL_GPL(bcma_driver_unregister);
++
++static int bcma_bus_match(struct device *dev, struct device_driver *drv)
++{
++	struct bcma_device *core = container_of(dev, struct bcma_device, dev);
++	struct bcma_driver *adrv = container_of(drv, struct bcma_driver, drv);
++	const struct bcma_device_id *cid = &core->id;
++	const struct bcma_device_id *did;
++
++	for (did = adrv->id_table; did->manuf || did->id || did->rev; did++) {
++	    if ((did->manuf == cid->manuf || did->manuf == BCMA_ANY_MANUF) &&
++		(did->id == cid->id || did->id == BCMA_ANY_ID) &&
++		(did->rev == cid->rev || did->rev == BCMA_ANY_REV) &&
++		(did->class == cid->class || did->class == BCMA_ANY_CLASS))
++			return 1;
++	}
++	return 0;
++}
++
++static int bcma_device_probe(struct device *dev)
++{
++	struct bcma_device *core = container_of(dev, struct bcma_device, dev);
++	struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
++					       drv);
++	int err = 0;
++
++	if (adrv->probe)
++		err = adrv->probe(core);
++
++	return err;
++}
++
++static int bcma_device_remove(struct device *dev)
++{
++	struct bcma_device *core = container_of(dev, struct bcma_device, dev);
++	struct bcma_driver *adrv = container_of(dev->driver, struct bcma_driver,
++					       drv);
++
++	if (adrv->remove)
++		adrv->remove(core);
++
++	return 0;
++}
++
++static int __init bcma_modinit(void)
++{
++	int err;
++
++	err = bus_register(&bcma_bus_type);
++	if (err)
++		return err;
++
++#ifdef CONFIG_BCMA_HOST_PCI
++	err = bcma_host_pci_init();
++	if (err) {
++		pr_err("PCI host initialization failed\n");
++		err = 0;
++	}
++#endif
++
++	return err;
++}
++fs_initcall(bcma_modinit);
++
++static void __exit bcma_modexit(void)
++{
++#ifdef CONFIG_BCMA_HOST_PCI
++	bcma_host_pci_exit();
++#endif
++	bus_unregister(&bcma_bus_type);
++}
++module_exit(bcma_modexit)
+--- /dev/null
++++ b/drivers/bcma/scan.c
+@@ -0,0 +1,360 @@
++/*
++ * Broadcom specific AMBA
++ * Bus scanning
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "scan.h"
++#include "bcma_private.h"
++
++#include <linux/bcma/bcma.h>
++#include <linux/bcma/bcma_regs.h>
++#include <linux/pci.h>
++#include <linux/io.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++
++struct bcma_device_id_name {
++	u16 id;
++	const char *name;
++};
++struct bcma_device_id_name bcma_device_names[] = {
++	{ BCMA_CORE_OOB_ROUTER, "OOB Router" },
++	{ BCMA_CORE_INVALID, "Invalid" },
++	{ BCMA_CORE_CHIPCOMMON, "ChipCommon" },
++	{ BCMA_CORE_ILINE20, "ILine 20" },
++	{ BCMA_CORE_SRAM, "SRAM" },
++	{ BCMA_CORE_SDRAM, "SDRAM" },
++	{ BCMA_CORE_PCI, "PCI" },
++	{ BCMA_CORE_MIPS, "MIPS" },
++	{ BCMA_CORE_ETHERNET, "Fast Ethernet" },
++	{ BCMA_CORE_V90, "V90" },
++	{ BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
++	{ BCMA_CORE_ADSL, "ADSL" },
++	{ BCMA_CORE_ILINE100, "ILine 100" },
++	{ BCMA_CORE_IPSEC, "IPSEC" },
++	{ BCMA_CORE_UTOPIA, "UTOPIA" },
++	{ BCMA_CORE_PCMCIA, "PCMCIA" },
++	{ BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
++	{ BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
++	{ BCMA_CORE_OFDM, "OFDM" },
++	{ BCMA_CORE_EXTIF, "EXTIF" },
++	{ BCMA_CORE_80211, "IEEE 802.11" },
++	{ BCMA_CORE_PHY_A, "PHY A" },
++	{ BCMA_CORE_PHY_B, "PHY B" },
++	{ BCMA_CORE_PHY_G, "PHY G" },
++	{ BCMA_CORE_MIPS_3302, "MIPS 3302" },
++	{ BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
++	{ BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
++	{ BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
++	{ BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
++	{ BCMA_CORE_SDIO_HOST, "SDIO Host" },
++	{ BCMA_CORE_ROBOSWITCH, "Roboswitch" },
++	{ BCMA_CORE_PARA_ATA, "PATA" },
++	{ BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
++	{ BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
++	{ BCMA_CORE_PCIE, "PCIe" },
++	{ BCMA_CORE_PHY_N, "PHY N" },
++	{ BCMA_CORE_SRAM_CTL, "SRAM Controller" },
++	{ BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
++	{ BCMA_CORE_ARM_1176, "ARM 1176" },
++	{ BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
++	{ BCMA_CORE_PHY_LP, "PHY LP" },
++	{ BCMA_CORE_PMU, "PMU" },
++	{ BCMA_CORE_PHY_SSN, "PHY SSN" },
++	{ BCMA_CORE_SDIO_DEV, "SDIO Device" },
++	{ BCMA_CORE_ARM_CM3, "ARM CM3" },
++	{ BCMA_CORE_PHY_HT, "PHY HT" },
++	{ BCMA_CORE_MIPS_74K, "MIPS 74K" },
++	{ BCMA_CORE_MAC_GBIT, "GBit MAC" },
++	{ BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
++	{ BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
++	{ BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
++	{ BCMA_CORE_SHARED_COMMON, "Common Shared" },
++	{ BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
++	{ BCMA_CORE_SPI_HOST, "SPI Host" },
++	{ BCMA_CORE_I2S, "I2S" },
++	{ BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
++	{ BCMA_CORE_SHIM, "SHIM" },
++	{ BCMA_CORE_DEFAULT, "Default" },
++};
++const char *bcma_device_name(struct bcma_device_id *id)
++{
++	int i;
++
++	if (id->manuf == BCMA_MANUF_BCM) {
++		for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
++			if (bcma_device_names[i].id == id->id)
++				return bcma_device_names[i].name;
++		}
++	}
++	return "UNKNOWN";
++}
++
++static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
++		       u16 offset)
++{
++	return readl(bus->mmio + offset);
++}
++
++static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
++{
++	if (bus->hosttype == BCMA_HOSTTYPE_PCI)
++		pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
++				       addr);
++}
++
++static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
++{
++	u32 ent = readl(*eromptr);
++	(*eromptr)++;
++	return ent;
++}
++
++static void bcma_erom_push_ent(u32 **eromptr)
++{
++	(*eromptr)--;
++}
++
++static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
++{
++	u32 ent = bcma_erom_get_ent(bus, eromptr);
++	if (!(ent & SCAN_ER_VALID))
++		return -ENOENT;
++	if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
++		return -ENOENT;
++	return ent;
++}
++
++static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
++{
++	u32 ent = bcma_erom_get_ent(bus, eromptr);
++	bcma_erom_push_ent(eromptr);
++	return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
++}
++
++static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
++{
++	u32 ent = bcma_erom_get_ent(bus, eromptr);
++	bcma_erom_push_ent(eromptr);
++	return (((ent & SCAN_ER_VALID)) &&
++		((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
++		((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
++}
++
++static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
++{
++	u32 ent;
++	while (1) {
++		ent = bcma_erom_get_ent(bus, eromptr);
++		if ((ent & SCAN_ER_VALID) &&
++		    ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
++			break;
++		if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
++			break;
++	}
++	bcma_erom_push_ent(eromptr);
++}
++
++static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
++{
++	u32 ent = bcma_erom_get_ent(bus, eromptr);
++	if (!(ent & SCAN_ER_VALID))
++		return -ENOENT;
++	if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
++		return -ENOENT;
++	return ent;
++}
++
++static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
++				  u32 type, u8 port)
++{
++	u32 addrl, addrh, sizel, sizeh = 0;
++	u32 size;
++
++	u32 ent = bcma_erom_get_ent(bus, eromptr);
++	if ((!(ent & SCAN_ER_VALID)) ||
++	    ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
++	    ((ent & SCAN_ADDR_TYPE) != type) ||
++	    (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
++		bcma_erom_push_ent(eromptr);
++		return -EINVAL;
++	}
++
++	addrl = ent & SCAN_ADDR_ADDR;
++	if (ent & SCAN_ADDR_AG32)
++		addrh = bcma_erom_get_ent(bus, eromptr);
++	else
++		addrh = 0;
++
++	if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
++		size = bcma_erom_get_ent(bus, eromptr);
++		sizel = size & SCAN_SIZE_SZ;
++		if (size & SCAN_SIZE_SG32)
++			sizeh = bcma_erom_get_ent(bus, eromptr);
++	} else
++		sizel = SCAN_ADDR_SZ_BASE <<
++				((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);
++
++	return addrl;
++}
++
++int bcma_bus_scan(struct bcma_bus *bus)
++{
++	u32 erombase;
++	u32 __iomem *eromptr, *eromend;
++
++	s32 cia, cib;
++	u8 ports[2], wrappers[2];
++
++	s32 tmp;
++	u8 i, j;
++
++	int err;
++
++	INIT_LIST_HEAD(&bus->cores);
++	bus->nr_cores = 0;
++
++	bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
++
++	tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
++	bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
++	bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
++	bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
++
++	erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
++	eromptr = bus->mmio;
++	eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
++
++	bcma_scan_switch_core(bus, erombase);
++
++	while (eromptr < eromend) {
++		struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
++		if (!core)
++			return -ENOMEM;
++		INIT_LIST_HEAD(&core->list);
++		core->bus = bus;
++
++		/* get CIs */
++		cia = bcma_erom_get_ci(bus, &eromptr);
++		if (cia < 0) {
++			bcma_erom_push_ent(&eromptr);
++			if (bcma_erom_is_end(bus, &eromptr))
++				break;
++			err= -EILSEQ;
++			goto out;
++		}
++		cib = bcma_erom_get_ci(bus, &eromptr);
++		if (cib < 0) {
++			err= -EILSEQ;
++			goto out;
++		}
++
++		/* parse CIs */
++		core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
++		core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
++		core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
++		ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
++		ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
++		wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
++		wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
++		core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
++
++		if (((core->id.manuf == BCMA_MANUF_ARM) &&
++		     (core->id.id == 0xFFF)) ||
++		    (ports[1] == 0)) {
++			bcma_erom_skip_component(bus, &eromptr);
++			continue;
++		}
++
++		/* check if component is a core at all */
++		if (wrappers[0] + wrappers[1] == 0) {
++			/* we could save addrl of the router
++			if (cid == BCMA_CORE_OOB_ROUTER)
++			 */
++			bcma_erom_skip_component(bus, &eromptr);
++			continue;
++		}
++
++		if (bcma_erom_is_bridge(bus, &eromptr)) {
++			bcma_erom_skip_component(bus, &eromptr);
++			continue;
++		}
++
++		/* get & parse master ports */
++		for (i = 0; i < ports[0]; i++) {
++			u32 mst_port_d = bcma_erom_get_mst_port(bus, &eromptr);
++			if (mst_port_d < 0) {
++				err= -EILSEQ;
++				goto out;
++			}
++		}
++
++		/* get & parse slave ports */
++		for (i = 0; i < ports[1]; i++) {
++			for (j = 0; ; j++) {
++				tmp = bcma_erom_get_addr_desc(bus, &eromptr,
++					SCAN_ADDR_TYPE_SLAVE, i);
++				if (tmp < 0) {
++					/* no more entries for port _i_ */
++					/* pr_debug("erom: slave port %d "
++					 * "has %d descriptors\n", i, j); */
++					break;
++				} else {
++					if (i == 0 && j == 0)
++						core->addr = tmp;
++				}
++			}
++		}
++
++		/* get & parse master wrappers */
++		for (i = 0; i < wrappers[0]; i++) {
++			for (j = 0; ; j++) {
++				tmp = bcma_erom_get_addr_desc(bus, &eromptr,
++					SCAN_ADDR_TYPE_MWRAP, i);
++				if (tmp < 0) {
++					/* no more entries for port _i_ */
++					/* pr_debug("erom: master wrapper %d "
++					 * "has %d descriptors\n", i, j); */
++					break;
++				} else {
++					if (i == 0 && j == 0)
++						core->wrap = tmp;
++				}
++			}
++		}
++
++		/* get & parse slave wrappers */
++		for (i = 0; i < wrappers[1]; i++) {
++			u8 hack = (ports[1] == 1) ? 0 : 1;
++			for (j = 0; ; j++) {
++				tmp = bcma_erom_get_addr_desc(bus, &eromptr,
++					SCAN_ADDR_TYPE_SWRAP, i + hack);
++				if (tmp < 0) {
++					/* no more entries for port _i_ */
++					/* pr_debug("erom: master wrapper %d "
++					 * has %d descriptors\n", i, j); */
++					break;
++				} else {
++					if (wrappers[0] == 0 && !i && !j)
++						core->wrap = tmp;
++				}
++			}
++		}
++
++		pr_info("Core %d found: %s "
++			"(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
++			bus->nr_cores, bcma_device_name(&core->id),
++			core->id.manuf, core->id.id, core->id.rev,
++			core->id.class);
++
++		core->core_index = bus->nr_cores++;
++		list_add(&core->list, &bus->cores);
++		continue;
++out:
++		return err;
++	}
++
++	return 0;
++}
+--- /dev/null
++++ b/drivers/bcma/scan.h
+@@ -0,0 +1,56 @@
++#ifndef BCMA_SCAN_H_
++#define BCMA_SCAN_H_
++
++#define BCMA_ADDR_BASE		0x18000000
++#define BCMA_WRAP_BASE		0x18100000
++
++#define SCAN_ER_VALID		0x00000001
++#define SCAN_ER_TAGX		0x00000006 /* we have to ignore 0x8 bit when checking tag for SCAN_ER_TAG_ADDR */
++#define SCAN_ER_TAG		0x0000000E
++#define  SCAN_ER_TAG_CI		0x00000000
++#define  SCAN_ER_TAG_MP		0x00000002
++#define  SCAN_ER_TAG_ADDR	0x00000004
++#define  SCAN_ER_TAG_END	0x0000000E
++#define SCAN_ER_BAD		0xFFFFFFFF
++
++#define SCAN_CIA_CLASS		0x000000F0
++#define SCAN_CIA_CLASS_SHIFT	4
++#define SCAN_CIA_ID		0x000FFF00
++#define SCAN_CIA_ID_SHIFT	8
++#define SCAN_CIA_MANUF		0xFFF00000
++#define SCAN_CIA_MANUF_SHIFT	20
++
++#define SCAN_CIB_NMP		0x000001F0
++#define SCAN_CIB_NMP_SHIFT	4
++#define SCAN_CIB_NSP		0x00003E00
++#define SCAN_CIB_NSP_SHIFT	9
++#define SCAN_CIB_NMW		0x0007C000
++#define SCAN_CIB_NMW_SHIFT	14
++#define SCAN_CIB_NSW		0x00F80000
++#define SCAN_CIB_NSW_SHIFT	17
++#define SCAN_CIB_REV		0xFF000000
++#define SCAN_CIB_REV_SHIFT	24
++
++#define SCAN_ADDR_AG32		0x00000008
++#define SCAN_ADDR_SZ		0x00000030
++#define SCAN_ADDR_SZ_SHIFT	4
++#define  SCAN_ADDR_SZ_4K	0x00000000
++#define  SCAN_ADDR_SZ_8K	0x00000010
++#define  SCAN_ADDR_SZ_16K	0x00000020
++#define  SCAN_ADDR_SZ_SZD	0x00000030
++#define SCAN_ADDR_TYPE		0x000000C0
++#define  SCAN_ADDR_TYPE_SLAVE	0x00000000
++#define  SCAN_ADDR_TYPE_BRIDGE	0x00000040
++#define  SCAN_ADDR_TYPE_SWRAP	0x00000080
++#define  SCAN_ADDR_TYPE_MWRAP	0x000000C0
++#define SCAN_ADDR_PORT		0x00000F00
++#define SCAN_ADDR_PORT_SHIFT	8
++#define SCAN_ADDR_ADDR		0xFFFFF000
++
++#define SCAN_ADDR_SZ_BASE	0x00001000	/* 4KB */
++
++#define SCAN_SIZE_SZ_ALIGN	0x00000FFF
++#define SCAN_SIZE_SZ		0xFFFFF000
++#define SCAN_SIZE_SG32		0x00000008
++
++#endif /* BCMA_SCAN_H_ */
+--- /dev/null
++++ b/include/linux/bcma/bcma.h
+@@ -0,0 +1,271 @@
++#ifndef LINUX_BCMA_H_
++#define LINUX_BCMA_H_
++
++#include <linux/pci.h>
++#include <linux/mod_devicetable.h>
++
++#include <linux/bcma/bcma_driver_chipcommon.h>
++#include <linux/bcma/bcma_driver_pci.h>
++#include <linux/ssb/ssb.h> /* SPROM sharing */
++
++#include "bcma_regs.h"
++
++struct bcma_device;
++struct bcma_bus;
++
++enum bcma_hosttype {
++	BCMA_HOSTTYPE_NONE,
++	BCMA_HOSTTYPE_PCI,
++	BCMA_HOSTTYPE_SDIO,
++};
++
++struct bcma_chipinfo {
++	u16 id;
++	u8 rev;
++	u8 pkg;
++};
++
++enum bcma_clkmode {
++	BCMA_CLKMODE_FAST,
++	BCMA_CLKMODE_DYNAMIC,
++};
++
++struct bcma_host_ops {
++	u8 (*read8)(struct bcma_device *core, u16 offset);
++	u16 (*read16)(struct bcma_device *core, u16 offset);
++	u32 (*read32)(struct bcma_device *core, u16 offset);
++	void (*write8)(struct bcma_device *core, u16 offset, u8 value);
++	void (*write16)(struct bcma_device *core, u16 offset, u16 value);
++	void (*write32)(struct bcma_device *core, u16 offset, u32 value);
++#ifdef CONFIG_BCMA_BLOCKIO
++	void (*block_read)(struct bcma_device *core, void *buffer,
++			   size_t count, u16 offset, u8 reg_width);
++	void (*block_write)(struct bcma_device *core, const void *buffer,
++			    size_t count, u16 offset, u8 reg_width);
++#endif
++	/* Agent ops */
++	u32 (*aread32)(struct bcma_device *core, u16 offset);
++	void (*awrite32)(struct bcma_device *core, u16 offset, u32 value);
++};
++
++/* Core manufacturers */
++#define BCMA_MANUF_ARM			0x43B
++#define BCMA_MANUF_MIPS			0x4A7
++#define BCMA_MANUF_BCM			0x4BF
++
++/* Core class values. */
++#define BCMA_CL_SIM			0x0
++#define BCMA_CL_EROM			0x1
++#define BCMA_CL_CORESIGHT		0x9
++#define BCMA_CL_VERIF			0xB
++#define BCMA_CL_OPTIMO			0xD
++#define BCMA_CL_GEN			0xE
++#define BCMA_CL_PRIMECELL		0xF
++
++/* Core-ID values. */
++#define BCMA_CORE_OOB_ROUTER		0x367	/* Out of band */
++#define BCMA_CORE_INVALID		0x700
++#define BCMA_CORE_CHIPCOMMON		0x800
++#define BCMA_CORE_ILINE20		0x801
++#define BCMA_CORE_SRAM			0x802
++#define BCMA_CORE_SDRAM			0x803
++#define BCMA_CORE_PCI			0x804
++#define BCMA_CORE_MIPS			0x805
++#define BCMA_CORE_ETHERNET		0x806
++#define BCMA_CORE_V90			0x807
++#define BCMA_CORE_USB11_HOSTDEV		0x808
++#define BCMA_CORE_ADSL			0x809
++#define BCMA_CORE_ILINE100		0x80A
++#define BCMA_CORE_IPSEC			0x80B
++#define BCMA_CORE_UTOPIA		0x80C
++#define BCMA_CORE_PCMCIA		0x80D
++#define BCMA_CORE_INTERNAL_MEM		0x80E
++#define BCMA_CORE_MEMC_SDRAM		0x80F
++#define BCMA_CORE_OFDM			0x810
++#define BCMA_CORE_EXTIF			0x811
++#define BCMA_CORE_80211			0x812
++#define BCMA_CORE_PHY_A			0x813
++#define BCMA_CORE_PHY_B			0x814
++#define BCMA_CORE_PHY_G			0x815
++#define BCMA_CORE_MIPS_3302		0x816
++#define BCMA_CORE_USB11_HOST		0x817
++#define BCMA_CORE_USB11_DEV		0x818
++#define BCMA_CORE_USB20_HOST		0x819
++#define BCMA_CORE_USB20_DEV		0x81A
++#define BCMA_CORE_SDIO_HOST		0x81B
++#define BCMA_CORE_ROBOSWITCH		0x81C
++#define BCMA_CORE_PARA_ATA		0x81D
++#define BCMA_CORE_SATA_XORDMA		0x81E
++#define BCMA_CORE_ETHERNET_GBIT		0x81F
++#define BCMA_CORE_PCIE			0x820
++#define BCMA_CORE_PHY_N			0x821
++#define BCMA_CORE_SRAM_CTL		0x822
++#define BCMA_CORE_MINI_MACPHY		0x823
++#define BCMA_CORE_ARM_1176		0x824
++#define BCMA_CORE_ARM_7TDMI		0x825
++#define BCMA_CORE_PHY_LP		0x826
++#define BCMA_CORE_PMU			0x827
++#define BCMA_CORE_PHY_SSN		0x828
++#define BCMA_CORE_SDIO_DEV		0x829
++#define BCMA_CORE_ARM_CM3		0x82A
++#define BCMA_CORE_PHY_HT		0x82B
++#define BCMA_CORE_MIPS_74K		0x82C
++#define BCMA_CORE_MAC_GBIT		0x82D
++#define BCMA_CORE_DDR12_MEM_CTL		0x82E
++#define BCMA_CORE_PCIE_RC		0x82F	/* PCIe Root Complex */
++#define BCMA_CORE_OCP_OCP_BRIDGE	0x830
++#define BCMA_CORE_SHARED_COMMON		0x831
++#define BCMA_CORE_OCP_AHB_BRIDGE	0x832
++#define BCMA_CORE_SPI_HOST		0x833
++#define BCMA_CORE_I2S			0x834
++#define BCMA_CORE_SDR_DDR1_MEM_CTL	0x835	/* SDR/DDR1 memory controller core */
++#define BCMA_CORE_SHIM			0x837	/* SHIM component in ubus/6362 */
++#define BCMA_CORE_DEFAULT		0xFFF
++
++#define BCMA_MAX_NR_CORES		16
++
++struct bcma_device {
++	struct bcma_bus *bus;
++	struct bcma_device_id id;
++
++	struct device dev;
++	struct device *dma_dev;
++	unsigned int irq;
++	bool dev_registered;
++
++	u8 core_index;
++
++	u32 addr;
++	u32 wrap;
++
++	void *drvdata;
++	struct list_head list;
++};
++
++static inline void *bcma_get_drvdata(struct bcma_device *core)
++{
++	return core->drvdata;
++}
++static inline void bcma_set_drvdata(struct bcma_device *core, void *drvdata)
++{
++	core->drvdata = drvdata;
++}
++
++struct bcma_driver {
++	const char *name;
++	const struct bcma_device_id *id_table;
++
++	int (*probe)(struct bcma_device *dev);
++	void (*remove)(struct bcma_device *dev);
++	int (*suspend)(struct bcma_device *dev, pm_message_t state);
++	int (*resume)(struct bcma_device *dev);
++	void (*shutdown)(struct bcma_device *dev);
++
++	struct device_driver drv;
++};
++extern
++int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
++static inline int bcma_driver_register(struct bcma_driver *drv)
++{
++	return __bcma_driver_register(drv, THIS_MODULE);
++}
++extern void bcma_driver_unregister(struct bcma_driver *drv);
++
++struct bcma_bus {
++	/* The MMIO area. */
++	void __iomem *mmio;
++
++	const struct bcma_host_ops *ops;
++
++	enum bcma_hosttype hosttype;
++	union {
++		/* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */
++		struct pci_dev *host_pci;
++		/* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
++		struct sdio_func *host_sdio;
++	};
++
++	struct bcma_chipinfo chipinfo;
++
++	struct bcma_device *mapped_core;
++	struct list_head cores;
++	u8 nr_cores;
++
++	struct bcma_drv_cc drv_cc;
++	struct bcma_drv_pci drv_pci;
++
++	/* We decided to share SPROM struct with SSB as long as we do not need
++	 * any hacks for BCMA. This simplifies drivers code. */
++	struct ssb_sprom sprom;
++};
++
++extern inline u32 bcma_read8(struct bcma_device *core, u16 offset)
++{
++	return core->bus->ops->read8(core, offset);
++}
++extern inline u32 bcma_read16(struct bcma_device *core, u16 offset)
++{
++	return core->bus->ops->read16(core, offset);
++}
++extern inline u32 bcma_read32(struct bcma_device *core, u16 offset)
++{
++	return core->bus->ops->read32(core, offset);
++}
++extern inline
++void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
++{
++	core->bus->ops->write8(core, offset, value);
++}
++extern inline
++void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
++{
++	core->bus->ops->write16(core, offset, value);
++}
++extern inline
++void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
++{
++	core->bus->ops->write32(core, offset, value);
++}
++#ifdef CONFIG_BCMA_BLOCKIO
++extern inline void bcma_block_read(struct bcma_device *core, void *buffer,
++				   size_t count, u16 offset, u8 reg_width)
++{
++	core->bus->ops->block_read(core, buffer, count, offset, reg_width);
++}
++extern inline void bcma_block_write(struct bcma_device *core, const void *buffer,
++				    size_t count, u16 offset, u8 reg_width)
++{
++	core->bus->ops->block_write(core, buffer, count, offset, reg_width);
++}
++#endif
++extern inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
++{
++	return core->bus->ops->aread32(core, offset);
++}
++extern inline
++void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
++{
++	core->bus->ops->awrite32(core, offset, value);
++}
++
++#define bcma_mask32(cc, offset, mask) \
++	bcma_write32(cc, offset, bcma_read32(cc, offset) & (mask))
++#define bcma_set32(cc, offset, set) \
++	bcma_write32(cc, offset, bcma_read32(cc, offset) | (set))
++#define bcma_maskset32(cc, offset, mask, set) \
++	bcma_write32(cc, offset, (bcma_read32(cc, offset) & (mask)) | (set))
++
++extern bool bcma_core_is_enabled(struct bcma_device *core);
++extern void bcma_core_disable(struct bcma_device *core, u32 flags);
++extern int bcma_core_enable(struct bcma_device *core, u32 flags);
++extern void bcma_core_set_clockmode(struct bcma_device *core,
++				    enum bcma_clkmode clkmode);
++extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
++			      bool on);
++#define BCMA_DMA_TRANSLATION_MASK	0xC0000000
++#define  BCMA_DMA_TRANSLATION_NONE	0x00000000
++#define  BCMA_DMA_TRANSLATION_DMA32_CMT	0x40000000 /* Client Mode Translation for 32-bit DMA */
++#define  BCMA_DMA_TRANSLATION_DMA64_CMT	0x80000000 /* Client Mode Translation for 64-bit DMA */
++extern u32 bcma_core_dma_translation(struct bcma_device *core);
++
++#endif /* LINUX_BCMA_H_ */
+--- /dev/null
++++ b/include/linux/bcma/bcma_driver_chipcommon.h
+@@ -0,0 +1,296 @@
++#ifndef LINUX_BCMA_DRIVER_CC_H_
++#define LINUX_BCMA_DRIVER_CC_H_
++
++/** ChipCommon core registers. **/
++#define BCMA_CC_ID			0x0000
++#define  BCMA_CC_ID_ID			0x0000FFFF
++#define  BCMA_CC_ID_ID_SHIFT		0
++#define  BCMA_CC_ID_REV			0x000F0000
++#define  BCMA_CC_ID_REV_SHIFT		16
++#define  BCMA_CC_ID_PKG			0x00F00000
++#define  BCMA_CC_ID_PKG_SHIFT		20
++#define  BCMA_CC_ID_NRCORES		0x0F000000
++#define  BCMA_CC_ID_NRCORES_SHIFT	24
++#define  BCMA_CC_ID_TYPE		0xF0000000
++#define  BCMA_CC_ID_TYPE_SHIFT		28
++#define BCMA_CC_CAP			0x0004		/* Capabilities */
++#define  BCMA_CC_CAP_NRUART		0x00000003	/* # of UARTs */
++#define  BCMA_CC_CAP_MIPSEB		0x00000004	/* MIPS in BigEndian Mode */
++#define  BCMA_CC_CAP_UARTCLK		0x00000018	/* UART clock select */
++#define   BCMA_CC_CAP_UARTCLK_INT	0x00000008	/* UARTs are driven by internal divided clock */
++#define  BCMA_CC_CAP_UARTGPIO		0x00000020	/* UARTs on GPIO 15-12 */
++#define  BCMA_CC_CAP_EXTBUS		0x000000C0	/* External buses present */
++#define  BCMA_CC_CAP_FLASHT		0x00000700	/* Flash Type */
++#define   BCMA_CC_FLASHT_NONE		0x00000000	/* No flash */
++#define   BCMA_CC_FLASHT_STSER		0x00000100	/* ST serial flash */
++#define   BCMA_CC_FLASHT_ATSER		0x00000200	/* Atmel serial flash */
++#define	  BCMA_CC_FLASHT_PARA		0x00000700	/* Parallel flash */
++#define  BCMA_CC_CAP_PLLT		0x00038000	/* PLL Type */
++#define   BCMA_PLLTYPE_NONE		0x00000000
++#define   BCMA_PLLTYPE_1		0x00010000	/* 48Mhz base, 3 dividers */
++#define   BCMA_PLLTYPE_2		0x00020000	/* 48Mhz, 4 dividers */
++#define   BCMA_PLLTYPE_3		0x00030000	/* 25Mhz, 2 dividers */
++#define   BCMA_PLLTYPE_4		0x00008000	/* 48Mhz, 4 dividers */
++#define   BCMA_PLLTYPE_5		0x00018000	/* 25Mhz, 4 dividers */
++#define   BCMA_PLLTYPE_6		0x00028000	/* 100/200 or 120/240 only */
++#define   BCMA_PLLTYPE_7		0x00038000	/* 25Mhz, 4 dividers */
++#define  BCMA_CC_CAP_PCTL		0x00040000	/* Power Control */
++#define  BCMA_CC_CAP_OTPS		0x00380000	/* OTP size */
++#define  BCMA_CC_CAP_OTPS_SHIFT		19
++#define  BCMA_CC_CAP_OTPS_BASE		5
++#define  BCMA_CC_CAP_JTAGM		0x00400000	/* JTAG master present */
++#define  BCMA_CC_CAP_BROM		0x00800000	/* Internal boot ROM active */
++#define  BCMA_CC_CAP_64BIT		0x08000000	/* 64-bit Backplane */
++#define  BCMA_CC_CAP_PMU		0x10000000	/* PMU available (rev >= 20) */
++#define  BCMA_CC_CAP_ECI		0x20000000	/* ECI available (rev >= 20) */
++#define  BCMA_CC_CAP_SPROM		0x40000000	/* SPROM present */
++#define BCMA_CC_CORECTL			0x0008
++#define  BCMA_CC_CORECTL_UARTCLK0	0x00000001	/* Drive UART with internal clock */
++#define	 BCMA_CC_CORECTL_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
++#define  BCMA_CC_CORECTL_UARTCLKEN	0x00000008	/* UART clock enable (rev >= 21) */
++#define BCMA_CC_BIST			0x000C
++#define BCMA_CC_OTPS			0x0010		/* OTP status */
++#define	 BCMA_CC_OTPS_PROGFAIL		0x80000000
++#define	 BCMA_CC_OTPS_PROTECT		0x00000007
++#define	 BCMA_CC_OTPS_HW_PROTECT	0x00000001
++#define	 BCMA_CC_OTPS_SW_PROTECT	0x00000002
++#define	 BCMA_CC_OTPS_CID_PROTECT	0x00000004
++#define BCMA_CC_OTPC			0x0014		/* OTP control */
++#define	 BCMA_CC_OTPC_RECWAIT		0xFF000000
++#define	 BCMA_CC_OTPC_PROGWAIT		0x00FFFF00
++#define	 BCMA_CC_OTPC_PRW_SHIFT		8
++#define	 BCMA_CC_OTPC_MAXFAIL		0x00000038
++#define	 BCMA_CC_OTPC_VSEL		0x00000006
++#define	 BCMA_CC_OTPC_SELVL		0x00000001
++#define BCMA_CC_OTPP			0x0018		/* OTP prog */
++#define	 BCMA_CC_OTPP_COL		0x000000FF
++#define	 BCMA_CC_OTPP_ROW		0x0000FF00
++#define	 BCMA_CC_OTPP_ROW_SHIFT		8
++#define	 BCMA_CC_OTPP_READERR		0x10000000
++#define	 BCMA_CC_OTPP_VALUE		0x20000000
++#define	 BCMA_CC_OTPP_READ		0x40000000
++#define	 BCMA_CC_OTPP_START		0x80000000
++#define	 BCMA_CC_OTPP_BUSY		0x80000000
++#define BCMA_CC_IRQSTAT			0x0020
++#define BCMA_CC_IRQMASK			0x0024
++#define	 BCMA_CC_IRQ_GPIO		0x00000001	/* gpio intr */
++#define	 BCMA_CC_IRQ_EXT		0x00000002	/* ro: ext intr pin (corerev >= 3) */
++#define	 BCMA_CC_IRQ_WDRESET		0x80000000	/* watchdog reset occurred */
++#define BCMA_CC_CHIPCTL			0x0028		/* Rev >= 11 only */
++#define BCMA_CC_CHIPSTAT		0x002C		/* Rev >= 11 only */
++#define BCMA_CC_JCMD			0x0030		/* Rev >= 10 only */
++#define  BCMA_CC_JCMD_START		0x80000000
++#define  BCMA_CC_JCMD_BUSY		0x80000000
++#define  BCMA_CC_JCMD_PAUSE		0x40000000
++#define  BCMA_CC_JCMD0_ACC_MASK		0x0000F000
++#define  BCMA_CC_JCMD0_ACC_IRDR		0x00000000
++#define  BCMA_CC_JCMD0_ACC_DR		0x00001000
++#define  BCMA_CC_JCMD0_ACC_IR		0x00002000
++#define  BCMA_CC_JCMD0_ACC_RESET	0x00003000
++#define  BCMA_CC_JCMD0_ACC_IRPDR	0x00004000
++#define  BCMA_CC_JCMD0_ACC_PDR		0x00005000
++#define  BCMA_CC_JCMD0_IRW_MASK		0x00000F00
++#define  BCMA_CC_JCMD_ACC_MASK		0x000F0000	/* Changes for corerev 11 */
++#define  BCMA_CC_JCMD_ACC_IRDR		0x00000000
++#define  BCMA_CC_JCMD_ACC_DR		0x00010000
++#define  BCMA_CC_JCMD_ACC_IR		0x00020000
++#define  BCMA_CC_JCMD_ACC_RESET		0x00030000
++#define  BCMA_CC_JCMD_ACC_IRPDR		0x00040000
++#define  BCMA_CC_JCMD_ACC_PDR		0x00050000
++#define  BCMA_CC_JCMD_IRW_MASK		0x00001F00
++#define  BCMA_CC_JCMD_IRW_SHIFT		8
++#define  BCMA_CC_JCMD_DRW_MASK		0x0000003F
++#define BCMA_CC_JIR			0x0034		/* Rev >= 10 only */
++#define BCMA_CC_JDR			0x0038		/* Rev >= 10 only */
++#define BCMA_CC_JCTL			0x003C		/* Rev >= 10 only */
++#define  BCMA_CC_JCTL_FORCE_CLK		4		/* Force clock */
++#define  BCMA_CC_JCTL_EXT_EN		2		/* Enable external targets */
++#define  BCMA_CC_JCTL_EN		1		/* Enable Jtag master */
++#define BCMA_CC_FLASHCTL		0x0040
++#define  BCMA_CC_FLASHCTL_START		0x80000000
++#define  BCMA_CC_FLASHCTL_BUSY		BCMA_CC_FLASHCTL_START
++#define BCMA_CC_FLASHADDR		0x0044
++#define BCMA_CC_FLASHDATA		0x0048
++#define BCMA_CC_BCAST_ADDR		0x0050
++#define BCMA_CC_BCAST_DATA		0x0054
++#define BCMA_CC_GPIOPULLUP		0x0058		/* Rev >= 20 only */
++#define BCMA_CC_GPIOPULLDOWN		0x005C		/* Rev >= 20 only */
++#define BCMA_CC_GPIOIN			0x0060
++#define BCMA_CC_GPIOOUT			0x0064
++#define BCMA_CC_GPIOOUTEN		0x0068
++#define BCMA_CC_GPIOCTL			0x006C
++#define BCMA_CC_GPIOPOL			0x0070
++#define BCMA_CC_GPIOIRQ			0x0074
++#define BCMA_CC_WATCHDOG		0x0080
++#define BCMA_CC_GPIOTIMER		0x0088		/* LED powersave (corerev >= 16) */
++#define  BCMA_CC_GPIOTIMER_OFFTIME	0x0000FFFF
++#define  BCMA_CC_GPIOTIMER_OFFTIME_SHIFT	0
++#define  BCMA_CC_GPIOTIMER_ONTIME	0xFFFF0000
++#define  BCMA_CC_GPIOTIMER_ONTIME_SHIFT	16
++#define BCMA_CC_GPIOTOUTM		0x008C		/* LED powersave (corerev >= 16) */
++#define BCMA_CC_CLOCK_N			0x0090
++#define BCMA_CC_CLOCK_SB		0x0094
++#define BCMA_CC_CLOCK_PCI		0x0098
++#define BCMA_CC_CLOCK_M2		0x009C
++#define BCMA_CC_CLOCK_MIPS		0x00A0
++#define BCMA_CC_CLKDIV			0x00A4		/* Rev >= 3 only */
++#define	 BCMA_CC_CLKDIV_SFLASH		0x0F000000
++#define	 BCMA_CC_CLKDIV_SFLASH_SHIFT	24
++#define	 BCMA_CC_CLKDIV_OTP		0x000F0000
++#define	 BCMA_CC_CLKDIV_OTP_SHIFT	16
++#define	 BCMA_CC_CLKDIV_JTAG		0x00000F00
++#define	 BCMA_CC_CLKDIV_JTAG_SHIFT	8
++#define	 BCMA_CC_CLKDIV_UART		0x000000FF
++#define BCMA_CC_CAP_EXT			0x00AC		/* Capabilities */
++#define BCMA_CC_PLLONDELAY		0x00B0		/* Rev >= 4 only */
++#define BCMA_CC_FREFSELDELAY		0x00B4		/* Rev >= 4 only */
++#define BCMA_CC_SLOWCLKCTL		0x00B8		/* 6 <= Rev <= 9 only */
++#define  BCMA_CC_SLOWCLKCTL_SRC		0x00000007	/* slow clock source mask */
++#define	  BCMA_CC_SLOWCLKCTL_SRC_LPO	0x00000000	/* source of slow clock is LPO */
++#define   BCMA_CC_SLOWCLKCTL_SRC_XTAL	0x00000001	/* source of slow clock is crystal */
++#define	  BCMA_CC_SLOECLKCTL_SRC_PCI	0x00000002	/* source of slow clock is PCI */
++#define  BCMA_CC_SLOWCLKCTL_LPOFREQ	0x00000200	/* LPOFreqSel, 1: 160Khz, 0: 32KHz */
++#define  BCMA_CC_SLOWCLKCTL_LPOPD	0x00000400	/* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
++#define  BCMA_CC_SLOWCLKCTL_FSLOW	0x00000800	/* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
++#define  BCMA_CC_SLOWCLKCTL_IPLL	0x00001000	/* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
++#define  BCMA_CC_SLOWCLKCTL_ENXTAL	0x00002000	/* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
++#define  BCMA_CC_SLOWCLKCTL_XTALPU	0x00004000	/* XtalPU (RO), 1/0: crystal running/disabled */
++#define  BCMA_CC_SLOWCLKCTL_CLKDIV	0xFFFF0000	/* ClockDivider (SlowClk = 1/(4+divisor)) */
++#define  BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT	16
++#define BCMA_CC_SYSCLKCTL		0x00C0		/* Rev >= 3 only */
++#define	 BCMA_CC_SYSCLKCTL_IDLPEN	0x00000001	/* ILPen: Enable Idle Low Power */
++#define	 BCMA_CC_SYSCLKCTL_ALPEN	0x00000002	/* ALPen: Enable Active Low Power */
++#define	 BCMA_CC_SYSCLKCTL_PLLEN	0x00000004	/* ForcePLLOn */
++#define	 BCMA_CC_SYSCLKCTL_FORCEALP	0x00000008	/* Force ALP (or HT if ALPen is not set */
++#define	 BCMA_CC_SYSCLKCTL_FORCEHT	0x00000010	/* Force HT */
++#define  BCMA_CC_SYSCLKCTL_CLKDIV	0xFFFF0000	/* ClkDiv  (ILP = 1/(4+divisor)) */
++#define  BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT	16
++#define BCMA_CC_CLKSTSTR		0x00C4		/* Rev >= 3 only */
++#define BCMA_CC_EROM			0x00FC
++#define BCMA_CC_PCMCIA_CFG		0x0100
++#define BCMA_CC_PCMCIA_MEMWAIT		0x0104
++#define BCMA_CC_PCMCIA_ATTRWAIT		0x0108
++#define BCMA_CC_PCMCIA_IOWAIT		0x010C
++#define BCMA_CC_IDE_CFG			0x0110
++#define BCMA_CC_IDE_MEMWAIT		0x0114
++#define BCMA_CC_IDE_ATTRWAIT		0x0118
++#define BCMA_CC_IDE_IOWAIT		0x011C
++#define BCMA_CC_PROG_CFG		0x0120
++#define BCMA_CC_PROG_WAITCNT		0x0124
++#define BCMA_CC_FLASH_CFG		0x0128
++#define BCMA_CC_FLASH_WAITCNT		0x012C
++/* 0x1E0 is defined as shared BCMA_CLKCTLST */
++#define BCMA_CC_HW_WORKAROUND		0x01E4 /* Hardware workaround (rev >= 20) */
++#define BCMA_CC_UART0_DATA		0x0300
++#define BCMA_CC_UART0_IMR		0x0304
++#define BCMA_CC_UART0_FCR		0x0308
++#define BCMA_CC_UART0_LCR		0x030C
++#define BCMA_CC_UART0_MCR		0x0310
++#define BCMA_CC_UART0_LSR		0x0314
++#define BCMA_CC_UART0_MSR		0x0318
++#define BCMA_CC_UART0_SCRATCH		0x031C
++#define BCMA_CC_UART1_DATA		0x0400
++#define BCMA_CC_UART1_IMR		0x0404
++#define BCMA_CC_UART1_FCR		0x0408
++#define BCMA_CC_UART1_LCR		0x040C
++#define BCMA_CC_UART1_MCR		0x0410
++#define BCMA_CC_UART1_LSR		0x0414
++#define BCMA_CC_UART1_MSR		0x0418
++#define BCMA_CC_UART1_SCRATCH		0x041C
++/* PMU registers (rev >= 20) */
++#define BCMA_CC_PMU_CTL			0x0600 /* PMU control */
++#define  BCMA_CC_PMU_CTL_ILP_DIV	0xFFFF0000 /* ILP div mask */
++#define  BCMA_CC_PMU_CTL_ILP_DIV_SHIFT	16
++#define  BCMA_CC_PMU_CTL_NOILPONW	0x00000200 /* No ILP on wait */
++#define  BCMA_CC_PMU_CTL_HTREQEN	0x00000100 /* HT req enable */
++#define  BCMA_CC_PMU_CTL_ALPREQEN	0x00000080 /* ALP req enable */
++#define  BCMA_CC_PMU_CTL_XTALFREQ	0x0000007C /* Crystal freq */
++#define  BCMA_CC_PMU_CTL_XTALFREQ_SHIFT	2
++#define  BCMA_CC_PMU_CTL_ILPDIVEN	0x00000002 /* ILP div enable */
++#define  BCMA_CC_PMU_CTL_LPOSEL		0x00000001 /* LPO sel */
++#define BCMA_CC_PMU_CAP			0x0604 /* PMU capabilities */
++#define  BCMA_CC_PMU_CAP_REVISION	0x000000FF /* Revision mask */
++#define BCMA_CC_PMU_STAT		0x0608 /* PMU status */
++#define  BCMA_CC_PMU_STAT_INTPEND	0x00000040 /* Interrupt pending */
++#define  BCMA_CC_PMU_STAT_SBCLKST	0x00000030 /* Backplane clock status? */
++#define  BCMA_CC_PMU_STAT_HAVEALP	0x00000008 /* ALP available */
++#define  BCMA_CC_PMU_STAT_HAVEHT	0x00000004 /* HT available */
++#define  BCMA_CC_PMU_STAT_RESINIT	0x00000003 /* Res init */
++#define BCMA_CC_PMU_RES_STAT		0x060C /* PMU res status */
++#define BCMA_CC_PMU_RES_PEND		0x0610 /* PMU res pending */
++#define BCMA_CC_PMU_TIMER		0x0614 /* PMU timer */
++#define BCMA_CC_PMU_MINRES_MSK		0x0618 /* PMU min res mask */
++#define BCMA_CC_PMU_MAXRES_MSK		0x061C /* PMU max res mask */
++#define BCMA_CC_PMU_RES_TABSEL		0x0620 /* PMU res table sel */
++#define BCMA_CC_PMU_RES_DEPMSK		0x0624 /* PMU res dep mask */
++#define BCMA_CC_PMU_RES_UPDNTM		0x0628 /* PMU res updown timer */
++#define BCMA_CC_PMU_RES_TIMER		0x062C /* PMU res timer */
++#define BCMA_CC_PMU_CLKSTRETCH		0x0630 /* PMU clockstretch */
++#define BCMA_CC_PMU_WATCHDOG		0x0634 /* PMU watchdog */
++#define BCMA_CC_PMU_RES_REQTS		0x0640 /* PMU res req timer sel */
++#define BCMA_CC_PMU_RES_REQT		0x0644 /* PMU res req timer */
++#define BCMA_CC_PMU_RES_REQM		0x0648 /* PMU res req mask */
++#define BCMA_CC_CHIPCTL_ADDR		0x0650
++#define BCMA_CC_CHIPCTL_DATA		0x0654
++#define BCMA_CC_REGCTL_ADDR		0x0658
++#define BCMA_CC_REGCTL_DATA		0x065C
++#define BCMA_CC_PLLCTL_ADDR		0x0660
++#define BCMA_CC_PLLCTL_DATA		0x0664
++#define BCMA_CC_SPROM			0x0800 /* SPROM beginning */
++#define BCMA_CC_SPROM_PCIE6		0x0830 /* SPROM beginning on PCIe rev >= 6 */
++
++/* Data for the PMU, if available.
++ * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
++ */
++struct bcma_chipcommon_pmu {
++	u8 rev;			/* PMU revision */
++	u32 crystalfreq;	/* The active crystal frequency (in kHz) */
++};
++
++struct bcma_drv_cc {
++	struct bcma_device *core;
++	u32 status;
++	u32 capabilities;
++	u32 capabilities_ext;
++	/* Fast Powerup Delay constant */
++	u16 fast_pwrup_delay;
++	struct bcma_chipcommon_pmu pmu;
++};
++
++/* Register access */
++#define bcma_cc_read32(cc, offset) \
++	bcma_read32((cc)->core, offset)
++#define bcma_cc_write32(cc, offset, val) \
++	bcma_write32((cc)->core, offset, val)
++
++#define bcma_cc_mask32(cc, offset, mask) \
++	bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
++#define bcma_cc_set32(cc, offset, set) \
++	bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
++#define bcma_cc_maskset32(cc, offset, mask, set) \
++	bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
++
++extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
++
++extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
++extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
++
++extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
++					  u32 ticks);
++
++void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
++
++u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
++
++/* Chipcommon GPIO pin access. */
++u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
++u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
++u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
++u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
++u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
++u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
++
++/* PMU support */
++extern void bcma_pmu_init(struct bcma_drv_cc *cc);
++
++#endif /* LINUX_BCMA_DRIVER_CC_H_ */
+--- /dev/null
++++ b/include/linux/bcma/bcma_driver_pci.h
+@@ -0,0 +1,91 @@
++#ifndef LINUX_BCMA_DRIVER_PCI_H_
++#define LINUX_BCMA_DRIVER_PCI_H_
++
++#include <linux/types.h>
++
++struct pci_dev;
++
++/** PCI core registers. **/
++#define BCMA_CORE_PCI_CTL			0x0000	/* PCI Control */
++#define  BCMA_CORE_PCI_CTL_RST_OE		0x00000001 /* PCI_RESET Output Enable */
++#define  BCMA_CORE_PCI_CTL_RST			0x00000002 /* PCI_RESET driven out to pin */
++#define  BCMA_CORE_PCI_CTL_CLK_OE		0x00000004 /* Clock gate Output Enable */
++#define  BCMA_CORE_PCI_CTL_CLK			0x00000008 /* Gate for clock driven out to pin */
++#define BCMA_CORE_PCI_ARBCTL			0x0010	/* PCI Arbiter Control */
++#define  BCMA_CORE_PCI_ARBCTL_INTERN		0x00000001 /* Use internal arbiter */
++#define  BCMA_CORE_PCI_ARBCTL_EXTERN		0x00000002 /* Use external arbiter */
++#define  BCMA_CORE_PCI_ARBCTL_PARKID		0x00000006 /* Mask, selects which agent is parked on an idle bus */
++#define   BCMA_CORE_PCI_ARBCTL_PARKID_LAST	0x00000000 /* Last requestor */
++#define   BCMA_CORE_PCI_ARBCTL_PARKID_4710	0x00000002 /* 4710 */
++#define   BCMA_CORE_PCI_ARBCTL_PARKID_EXT0	0x00000004 /* External requestor 0 */
++#define   BCMA_CORE_PCI_ARBCTL_PARKID_EXT1	0x00000006 /* External requestor 1 */
++#define BCMA_CORE_PCI_ISTAT			0x0020	/* Interrupt status */
++#define  BCMA_CORE_PCI_ISTAT_INTA		0x00000001 /* PCI INTA# */
++#define  BCMA_CORE_PCI_ISTAT_INTB		0x00000002 /* PCI INTB# */
++#define  BCMA_CORE_PCI_ISTAT_SERR		0x00000004 /* PCI SERR# (write to clear) */
++#define  BCMA_CORE_PCI_ISTAT_PERR		0x00000008 /* PCI PERR# (write to clear) */
++#define  BCMA_CORE_PCI_ISTAT_PME		0x00000010 /* PCI PME# */
++#define BCMA_CORE_PCI_IMASK			0x0024	/* Interrupt mask */
++#define  BCMA_CORE_PCI_IMASK_INTA		0x00000001 /* PCI INTA# */
++#define  BCMA_CORE_PCI_IMASK_INTB		0x00000002 /* PCI INTB# */
++#define  BCMA_CORE_PCI_IMASK_SERR		0x00000004 /* PCI SERR# */
++#define  BCMA_CORE_PCI_IMASK_PERR		0x00000008 /* PCI PERR# */
++#define  BCMA_CORE_PCI_IMASK_PME		0x00000010 /* PCI PME# */
++#define BCMA_CORE_PCI_MBOX			0x0028	/* Backplane to PCI Mailbox */
++#define  BCMA_CORE_PCI_MBOX_F0_0		0x00000100 /* PCI function 0, INT 0 */
++#define  BCMA_CORE_PCI_MBOX_F0_1		0x00000200 /* PCI function 0, INT 1 */
++#define  BCMA_CORE_PCI_MBOX_F1_0		0x00000400 /* PCI function 1, INT 0 */
++#define  BCMA_CORE_PCI_MBOX_F1_1		0x00000800 /* PCI function 1, INT 1 */
++#define  BCMA_CORE_PCI_MBOX_F2_0		0x00001000 /* PCI function 2, INT 0 */
++#define  BCMA_CORE_PCI_MBOX_F2_1		0x00002000 /* PCI function 2, INT 1 */
++#define  BCMA_CORE_PCI_MBOX_F3_0		0x00004000 /* PCI function 3, INT 0 */
++#define  BCMA_CORE_PCI_MBOX_F3_1		0x00008000 /* PCI function 3, INT 1 */
++#define BCMA_CORE_PCI_BCAST_ADDR		0x0050	/* Backplane Broadcast Address */
++#define  BCMA_CORE_PCI_BCAST_ADDR_MASK		0x000000FF
++#define BCMA_CORE_PCI_BCAST_DATA		0x0054	/* Backplane Broadcast Data */
++#define BCMA_CORE_PCI_GPIO_IN			0x0060	/* rev >= 2 only */
++#define BCMA_CORE_PCI_GPIO_OUT			0x0064	/* rev >= 2 only */
++#define BCMA_CORE_PCI_GPIO_ENABLE		0x0068	/* rev >= 2 only */
++#define BCMA_CORE_PCI_GPIO_CTL			0x006C	/* rev >= 2 only */
++#define BCMA_CORE_PCI_SBTOPCI0			0x0100	/* Backplane to PCI translation 0 (sbtopci0) */
++#define  BCMA_CORE_PCI_SBTOPCI0_MASK		0xFC000000
++#define BCMA_CORE_PCI_SBTOPCI1			0x0104	/* Backplane to PCI translation 1 (sbtopci1) */
++#define  BCMA_CORE_PCI_SBTOPCI1_MASK		0xFC000000
++#define BCMA_CORE_PCI_SBTOPCI2			0x0108	/* Backplane to PCI translation 2 (sbtopci2) */
++#define  BCMA_CORE_PCI_SBTOPCI2_MASK		0xC0000000
++#define BCMA_CORE_PCI_PCICFG0			0x0400	/* PCI config space 0 (rev >= 8) */
++#define BCMA_CORE_PCI_PCICFG1			0x0500	/* PCI config space 1 (rev >= 8) */
++#define BCMA_CORE_PCI_PCICFG2			0x0600	/* PCI config space 2 (rev >= 8) */
++#define BCMA_CORE_PCI_PCICFG3			0x0700	/* PCI config space 3 (rev >= 8) */
++#define BCMA_CORE_PCI_SPROM(wordoffset)		(0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
++
++/* SBtoPCIx */
++#define BCMA_CORE_PCI_SBTOPCI_MEM		0x00000000
++#define BCMA_CORE_PCI_SBTOPCI_IO		0x00000001
++#define BCMA_CORE_PCI_SBTOPCI_CFG0		0x00000002
++#define BCMA_CORE_PCI_SBTOPCI_CFG1		0x00000003
++#define BCMA_CORE_PCI_SBTOPCI_PREF		0x00000004 /* Prefetch enable */
++#define BCMA_CORE_PCI_SBTOPCI_BURST		0x00000008 /* Burst enable */
++#define BCMA_CORE_PCI_SBTOPCI_MRM		0x00000020 /* Memory Read Multiple */
++#define BCMA_CORE_PCI_SBTOPCI_RC		0x00000030 /* Read Command mask (rev >= 11) */
++#define  BCMA_CORE_PCI_SBTOPCI_RC_READ		0x00000000 /* Memory read */
++#define  BCMA_CORE_PCI_SBTOPCI_RC_READL		0x00000010 /* Memory read line */
++#define  BCMA_CORE_PCI_SBTOPCI_RC_READM		0x00000020 /* Memory read multiple */
++
++/* PCIcore specific boardflags */
++#define BCMA_CORE_PCI_BFL_NOPCI			0x00000400 /* Board leaves PCI floating */
++
++struct bcma_drv_pci {
++	struct bcma_device *core;
++	u8 setup_done:1;
++};
++
++/* Register access */
++#define pcicore_read32(pc, offset)		bcma_read32((pc)->core, offset)
++#define pcicore_write32(pc, offset, val)	bcma_write32((pc)->core, offset, val)
++
++extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
++extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
++				 struct bcma_device *core, bool enable);
++
++#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
+--- /dev/null
++++ b/include/linux/bcma/bcma_regs.h
+@@ -0,0 +1,59 @@
++#ifndef LINUX_BCMA_REGS_H_
++#define LINUX_BCMA_REGS_H_
++
++/* Some single registers are shared between many cores */
++/* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */
++#define BCMA_CLKCTLST			0x01E0 /* Clock control and status */
++#define  BCMA_CLKCTLST_FORCEALP		0x00000001 /* Force ALP request */
++#define  BCMA_CLKCTLST_FORCEHT		0x00000002 /* Force HT request */
++#define  BCMA_CLKCTLST_FORCEILP		0x00000004 /* Force ILP request */
++#define  BCMA_CLKCTLST_HAVEALPREQ	0x00000008 /* ALP available request */
++#define  BCMA_CLKCTLST_HAVEHTREQ	0x00000010 /* HT available request */
++#define  BCMA_CLKCTLST_HWCROFF		0x00000020 /* Force HW clock request off */
++#define  BCMA_CLKCTLST_EXTRESREQ	0x00000700 /* Mask of external resource requests */
++#define  BCMA_CLKCTLST_HAVEALP		0x00010000 /* ALP available */
++#define  BCMA_CLKCTLST_HAVEHT		0x00020000 /* HT available */
++#define  BCMA_CLKCTLST_BP_ON_ALP	0x00040000 /* RO: running on ALP clock */
++#define  BCMA_CLKCTLST_BP_ON_HT		0x00080000 /* RO: running on HT clock */
++#define  BCMA_CLKCTLST_EXTRESST		0x07000000 /* Mask of external resource status */
++/* Is there any BCM4328 on BCMA bus? */
++#define  BCMA_CLKCTLST_4328A0_HAVEHT	0x00010000 /* 4328a0 has reversed bits */
++#define  BCMA_CLKCTLST_4328A0_HAVEALP	0x00020000 /* 4328a0 has reversed bits */
++
++/* Agent registers (common for every core) */
++#define BCMA_IOCTL			0x0408 /* IO control */
++#define  BCMA_IOCTL_CLK			0x0001
++#define  BCMA_IOCTL_FGC			0x0002
++#define  BCMA_IOCTL_CORE_BITS		0x3FFC
++#define  BCMA_IOCTL_PME_EN		0x4000
++#define  BCMA_IOCTL_BIST_EN		0x8000
++#define BCMA_IOST			0x0500 /* IO status */
++#define  BCMA_IOST_CORE_BITS		0x0FFF
++#define  BCMA_IOST_DMA64		0x1000
++#define  BCMA_IOST_GATED_CLK		0x2000
++#define  BCMA_IOST_BIST_ERROR		0x4000
++#define  BCMA_IOST_BIST_DONE		0x8000
++#define BCMA_RESET_CTL			0x0800
++#define  BCMA_RESET_CTL_RESET		0x0001
++
++/* BCMA PCI config space registers. */
++#define BCMA_PCI_PMCSR			0x44
++#define  BCMA_PCI_PE			0x100
++#define BCMA_PCI_BAR0_WIN		0x80	/* Backplane address space 0 */
++#define BCMA_PCI_BAR1_WIN		0x84	/* Backplane address space 1 */
++#define BCMA_PCI_SPROMCTL		0x88	/* SPROM control */
++#define  BCMA_PCI_SPROMCTL_WE		0x10	/* SPROM write enable */
++#define BCMA_PCI_BAR1_CONTROL		0x8c	/* Address space 1 burst control */
++#define BCMA_PCI_IRQS			0x90	/* PCI interrupts */
++#define BCMA_PCI_IRQMASK		0x94	/* PCI IRQ control and mask (pcirev >= 6 only) */
++#define BCMA_PCI_BACKPLANE_IRQS		0x98	/* Backplane Interrupts */
++#define BCMA_PCI_BAR0_WIN2		0xAC
++#define BCMA_PCI_GPIO_IN		0xB0	/* GPIO Input (pcirev >= 3 only) */
++#define BCMA_PCI_GPIO_OUT		0xB4	/* GPIO Output (pcirev >= 3 only) */
++#define BCMA_PCI_GPIO_OUT_ENABLE	0xB8	/* GPIO Output Enable/Disable (pcirev >= 3 only) */
++#define  BCMA_PCI_GPIO_SCS		0x10	/* PCI config space bit 4 for 4306c0 slow clock source */
++#define  BCMA_PCI_GPIO_HWRAD		0x20	/* PCI config space GPIO 13 for hw radio disable */
++#define  BCMA_PCI_GPIO_XTAL		0x40	/* PCI config space GPIO 14 for Xtal powerup */
++#define  BCMA_PCI_GPIO_PLL		0x80	/* PCI config space GPIO 15 for PLL powerdown */
++
++#endif /* LINUX_BCMA_REGS_H_ */
+--- a/include/linux/mod_devicetable.h
++++ b/include/linux/mod_devicetable.h
+@@ -382,6 +382,23 @@ struct ssb_device_id {
+ #define SSB_ANY_ID		0xFFFF
+ #define SSB_ANY_REV		0xFF
+ 
++/* Broadcom's specific AMBA core, see drivers/bcma/ */
++struct bcma_device_id {
++	__u16	manuf;
++	__u16	id;
++	__u8	rev;
++	__u8	class;
++};
++#define BCMA_CORE(_manuf, _id, _rev, _class)  \
++	{ .manuf = _manuf, .id = _id, .rev = _rev, .class = _class, }
++#define BCMA_CORETABLE_END  \
++	{ 0, },
++
++#define BCMA_ANY_MANUF		0xFFFF
++#define BCMA_ANY_ID		0xFFFF
++#define BCMA_ANY_REV		0xFF
++#define BCMA_ANY_CLASS		0xFF
++
+ struct virtio_device_id {
+ 	__u32 device;
+ 	__u32 vendor;
+--- a/scripts/mod/file2alias.c
++++ b/scripts/mod/file2alias.c
+@@ -702,6 +702,24 @@ static int do_ssb_entry(const char *file
+ 	return 1;
+ }
+ 
++/* Looks like: bcma:mNidNrevNclN. */
++static int do_bcma_entry(const char *filename,
++			 struct bcma_device_id *id, char *alias)
++{
++	id->manuf = TO_NATIVE(id->manuf);
++	id->id = TO_NATIVE(id->id);
++	id->rev = TO_NATIVE(id->rev);
++	id->class = TO_NATIVE(id->class);
++
++	strcpy(alias, "bcma:");
++	ADD(alias, "m", id->manuf != BCMA_ANY_MANUF, id->manuf);
++	ADD(alias, "id", id->id != BCMA_ANY_ID, id->id);
++	ADD(alias, "rev", id->rev != BCMA_ANY_REV, id->rev);
++	ADD(alias, "cl", id->class != BCMA_ANY_CLASS, id->class);
++	add_wildcard(alias);
++	return 1;
++}
++
+ /* Looks like: virtio:dNvN */
+ static int do_virtio_entry(const char *filename, struct virtio_device_id *id,
+ 			   char *alias)
+@@ -968,6 +986,10 @@ void handle_moddevtable(struct module *m
+ 		do_table(symval, sym->st_size,
+ 			 sizeof(struct ssb_device_id), "ssb",
+ 			 do_ssb_entry, mod);
++	else if (sym_is(symname, "__mod_bcma_device_table"))
++		do_table(symval, sym->st_size,
++			 sizeof(struct bcma_device_id), "bcma",
++			 do_bcma_entry, mod);
+ 	else if (sym_is(symname, "__mod_virtio_device_table"))
+ 		do_table(symval, sym->st_size,
+ 			 sizeof(struct virtio_device_id), "virtio",
+--- /dev/null
++++ b/drivers/bcma/sprom.c
+@@ -0,0 +1,171 @@
++/*
++ * Broadcom specific AMBA
++ * SPROM reading
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++
++#include <linux/bcma/bcma.h>
++#include <linux/bcma/bcma_regs.h>
++#include <linux/pci.h>
++#include <linux/io.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++
++#define SPOFF(offset)	((offset) / sizeof(u16))
++
++/**************************************************
++ * R/W ops.
++ **************************************************/
++
++static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
++{
++	int i;
++	for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
++		sprom[i] = bcma_read16(bus->drv_cc.core,
++				       offset + (i * 2));
++}
++
++/**************************************************
++ * Validation.
++ **************************************************/
++
++static inline u8 bcma_crc8(u8 crc, u8 data)
++{
++	/* Polynomial:   x^8 + x^7 + x^6 + x^4 + x^2 + 1   */
++	static const u8 t[] = {
++		0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
++		0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
++		0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
++		0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
++		0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
++		0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
++		0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
++		0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
++		0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
++		0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
++		0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
++		0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
++		0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
++		0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
++		0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
++		0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
++		0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
++		0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
++		0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
++		0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
++		0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
++		0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
++		0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
++		0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
++		0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
++		0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
++		0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
++		0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
++		0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
++		0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
++		0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
++		0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
++	};
++	return t[crc ^ data];
++}
++
++static u8 bcma_sprom_crc(const u16 *sprom)
++{
++	int word;
++	u8 crc = 0xFF;
++
++	for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
++		crc = bcma_crc8(crc, sprom[word] & 0x00FF);
++		crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
++	}
++	crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
++	crc ^= 0xFF;
++
++	return crc;
++}
++
++static int bcma_sprom_check_crc(const u16 *sprom)
++{
++	u8 crc;
++	u8 expected_crc;
++	u16 tmp;
++
++	crc = bcma_sprom_crc(sprom);
++	tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
++	expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
++	if (crc != expected_crc)
++		return -EPROTO;
++
++	return 0;
++}
++
++static int bcma_sprom_valid(const u16 *sprom)
++{
++	u16 revision;
++	int err;
++
++	err = bcma_sprom_check_crc(sprom);
++	if (err)
++		return err;
++
++	revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
++	if (revision != 8 && revision != 9) {
++		pr_err("Unsupported SPROM revision: %d\n", revision);
++		return -ENOENT;
++	}
++
++	return 0;
++}
++
++/**************************************************
++ * SPROM extraction.
++ **************************************************/
++
++static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
++{
++	u16 v;
++	int i;
++
++	for (i = 0; i < 3; i++) {
++		v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
++		*(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
++	}
++}
++
++int bcma_sprom_get(struct bcma_bus *bus)
++{
++	u16 offset;
++	u16 *sprom;
++	int err = 0;
++
++	if (!bus->drv_cc.core)
++		return -EOPNOTSUPP;
++
++	if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
++		return -ENOENT;
++
++	sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
++			GFP_KERNEL);
++	if (!sprom)
++		return -ENOMEM;
++
++	/* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
++	 * According to brcm80211 this applies to cards with PCIe rev >= 6
++	 * TODO: understand this condition and use it */
++	offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
++		BCMA_CC_SPROM_PCIE6;
++	bcma_sprom_read(bus, offset, sprom);
++
++	err = bcma_sprom_valid(sprom);
++	if (err)
++		goto out;
++
++	bcma_sprom_extract_r8(bus, sprom);
++
++out:
++	kfree(sprom);
++	return err;
++}
+--- /dev/null
++++ b/drivers/bcma/driver_pci_host.c
+@@ -0,0 +1,14 @@
++/*
++ * Broadcom specific AMBA
++ * PCI Core in hostmode
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/bcma/bcma.h>
++
++void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
++{
++	pr_err("No support for PCI core in hostmode yet\n");
++}
diff --git a/target/linux/generic/patches-2.6.38/253-ssb_b43_default_on.patch b/target/linux/generic/patches-2.6.38/253-ssb_b43_default_on.patch
index 3176dcb4d8..29d2a41a3b 100644
--- a/target/linux/generic/patches-2.6.38/253-ssb_b43_default_on.patch
+++ b/target/linux/generic/patches-2.6.38/253-ssb_b43_default_on.patch
@@ -17,3 +17,13 @@
  
  config SSB_PCMCIAHOST_POSSIBLE
  	bool
+--- a/drivers/bcma/Kconfig
++++ b/drivers/bcma/Kconfig
+@@ -17,6 +17,7 @@ config BCMA
+ config BCMA_BLOCKIO
+ 	bool
+ 	depends on BCMA
++	default y
+ 
+ config BCMA_HOST_PCI_POSSIBLE
+ 	bool