kernel: add a recent upstream commit (post-3.3) to the ssb update patch, required for the next mac80211 update

SVN-Revision: 30345

1 files changed, 125 insertions, 17 deletions

diff --git a/target/linux/generic/patches-2.6.37/020-ssb_update.patch b/target/linux/generic/patches-2.6.37/020-ssb_update.patch
index b71b67598e..d773a4fc90 100644
--- a/target/linux/generic/patches-2.6.37/020-ssb_update.patch
+++ b/target/linux/generic/patches-2.6.37/020-ssb_update.patch
@@ -417,7 +417,7 @@
  	}
  	SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
  	     SSB_SPROM4_ANTAVAIL_A_SHIFT);
-@@ -471,6 +515,8 @@ static void sprom_extract_r45(struct ssb
+@@ -471,13 +515,21 @@ static void sprom_extract_r45(struct ssb
  	memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
  	       sizeof(out->antenna_gain.ghz5));
  
@@ -426,10 +426,56 @@
  	/* TODO - get remaining rev 4 stuff needed */
  }
  
-@@ -561,6 +607,31 @@ static void sprom_extract_r8(struct ssb_
+ static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
+ {
+ 	int i;
+-	u16 v;
++	u16 v, o;
++	u16 pwr_info_offset[] = {
++		SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
++		SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
++	};
++	BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
++			ARRAY_SIZE(out->core_pwr_info));
+ 
+ 	/* extract the MAC address */
+ 	for (i = 0; i < 3; i++) {
+@@ -561,6 +613,63 @@ static void sprom_extract_r8(struct ssb_
  	memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
  	       sizeof(out->antenna_gain.ghz5));
  
++	/* Extract cores power info info */
++	for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
++		o = pwr_info_offset[i];
++		SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
++			SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
++		SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
++			SSB_SPROM8_2G_MAXP, 0);
++
++		SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
++		SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
++		SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
++
++		SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
++			SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
++		SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
++			SSB_SPROM8_5G_MAXP, 0);
++		SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
++			SSB_SPROM8_5GH_MAXP, 0);
++		SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
++			SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
++
++		SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
++		SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
++	}
++
 +	/* Extract FEM info */
 +	SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
 +		SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
@@ -458,7 +504,7 @@
  	/* TODO - get remaining rev 8 stuff needed */
  }
  
-@@ -573,37 +644,34 @@ static int sprom_extract(struct ssb_bus
+@@ -573,37 +682,34 @@ static int sprom_extract(struct ssb_bus 
  	ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
  	memset(out->et0mac, 0xFF, 6);		/* preset et0 and et1 mac */
  	memset(out->et1mac, 0xFF, 6);
@@ -517,7 +563,7 @@
  	}
  
  	if (out->boardflags_lo == 0xFFFF)
-@@ -617,15 +685,14 @@ static int sprom_extract(struct ssb_bus
+@@ -617,15 +723,14 @@ static int sprom_extract(struct ssb_bus 
  static int ssb_pci_sprom_get(struct ssb_bus *bus,
  			     struct ssb_sprom *sprom)
  {
@@ -535,7 +581,7 @@
  		/*
  		 * get SPROM offset: SSB_SPROM_BASE1 except for
  		 * chipcommon rev >= 31 or chip ID is 0x4312 and
-@@ -645,7 +712,7 @@ static int ssb_pci_sprom_get(struct ssb_
+@@ -645,7 +750,7 @@ static int ssb_pci_sprom_get(struct ssb_
  
  	buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
  	if (!buf)
@@ -544,7 +590,7 @@
  	bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
  	sprom_do_read(bus, buf);
  	err = sprom_check_crc(buf, bus->sprom_size);
-@@ -655,17 +722,24 @@ static int ssb_pci_sprom_get(struct ssb_
+@@ -655,17 +760,24 @@ static int ssb_pci_sprom_get(struct ssb_
  		buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
  			      GFP_KERNEL);
  		if (!buf)
@@ -574,7 +620,7 @@
  				err = 0;
  				goto out_free;
  			}
-@@ -677,19 +751,15 @@ static int ssb_pci_sprom_get(struct ssb_
+@@ -677,19 +789,15 @@ static int ssb_pci_sprom_get(struct ssb_
  
  out_free:
  	kfree(buf);
@@ -711,7 +757,20 @@
  		}
 --- a/include/linux/ssb/ssb.h
 +++ b/include/linux/ssb/ssb.h
-@@ -25,8 +25,10 @@ struct ssb_sprom {
+@@ -16,6 +16,12 @@ struct pcmcia_device;
+ struct ssb_bus;
+ struct ssb_driver;
+ 
++struct ssb_sprom_core_pwr_info {
++	u8 itssi_2g, itssi_5g;
++	u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
++	u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
++};
++
+ struct ssb_sprom {
+ 	u8 revision;
+ 	u8 il0mac[6];		/* MAC address for 802.11b/g */
+@@ -25,8 +31,10 @@ struct ssb_sprom {
  	u8 et1phyaddr;		/* MII address for enet1 */
  	u8 et0mdcport;		/* MDIO for enet0 */
  	u8 et1mdcport;		/* MDIO for enet1 */
@@ -723,7 +782,7 @@
  	u8 ant_available_a;	/* 2GHz antenna available bits (up to 4) */
  	u8 ant_available_bg;	/* 5GHz antenna available bits (up to 4) */
  	u16 pa0b0;
-@@ -55,6 +57,10 @@ struct ssb_sprom {
+@@ -55,6 +63,10 @@ struct ssb_sprom {
  	u8 tri5gl;		/* 5.2GHz TX isolation */
  	u8 tri5g;		/* 5.3GHz TX isolation */
  	u8 tri5gh;		/* 5.8GHz TX isolation */
@@ -734,7 +793,16 @@
  	u8 rxpo2g;		/* 2GHz RX power offset */
  	u8 rxpo5g;		/* 5GHz RX power offset */
  	u8 rssisav2g;		/* 2GHz RSSI params */
-@@ -88,6 +94,15 @@ struct ssb_sprom {
+@@ -76,6 +88,8 @@ struct ssb_sprom {
+ 	u16 boardflags2_hi;	/* Board flags (bits 48-63) */
+ 	/* TODO store board flags in a single u64 */
+ 
++	struct ssb_sprom_core_pwr_info core_pwr_info[4];
++
+ 	/* Antenna gain values for up to 4 antennas
+ 	 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
+ 	 * loss in the connectors is bigger than the gain. */
+@@ -88,6 +102,15 @@ struct ssb_sprom {
  		} ghz5;		/* 5GHz band */
  	} antenna_gain;
  
@@ -750,7 +818,7 @@
  	/* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
  };
  
-@@ -95,7 +110,7 @@ struct ssb_sprom {
+@@ -95,7 +118,7 @@ struct ssb_sprom {
  struct ssb_boardinfo {
  	u16 vendor;
  	u16 type;
@@ -759,7 +827,7 @@
  };
  
  
-@@ -225,10 +240,9 @@ struct ssb_driver {
+@@ -225,10 +248,9 @@ struct ssb_driver {
  #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
  
  extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
@@ -773,7 +841,7 @@
  extern void ssb_driver_unregister(struct ssb_driver *drv);
  
  
-@@ -304,7 +318,7 @@ struct ssb_bus {
+@@ -304,7 +326,7 @@ struct ssb_bus {
  
  	/* ID information about the Chip. */
  	u16 chip_id;
@@ -782,7 +850,7 @@
  	u16 sprom_offset;
  	u16 sprom_size;		/* number of words in sprom */
  	u8 chip_package;
-@@ -400,7 +414,9 @@ extern bool ssb_is_sprom_available(struc
+@@ -400,7 +422,9 @@ extern bool ssb_is_sprom_available(struc
  
  /* Set a fallback SPROM.
   * See kdoc at the function definition for complete documentation. */
@@ -793,7 +861,7 @@
  
  /* Suspend a SSB bus.
   * Call this from the parent bus suspend routine. */
-@@ -514,6 +530,7 @@ extern int ssb_bus_may_powerdown(struct
+@@ -514,6 +538,7 @@ extern int ssb_bus_may_powerdown(struct 
   * Otherwise static always-on powercontrol will be used. */
  extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
  
@@ -888,7 +956,7 @@
  #define SSB_SPROM5_IL0MAC		0x0052	/* 6 byte MAC address for a/b/g/n */
  #define SSB_SPROM5_GPIOA		0x0076	/* Gen. Purpose IO # 0 and 1 */
  #define  SSB_SPROM5_GPIOA_P0		0x00FF	/* Pin 0 */
-@@ -387,6 +432,23 @@
+@@ -387,6 +432,56 @@
  #define  SSB_SPROM8_RXPO2G		0x00FF	/* 2GHz RX power offset */
  #define  SSB_SPROM8_RXPO5G		0xFF00	/* 5GHz RX power offset */
  #define  SSB_SPROM8_RXPO5G_SHIFT	8
@@ -909,10 +977,50 @@
 +#define SSB_SPROM8_TS_SLP_OPT_CORRX	0x00B6
 +#define SSB_SPROM8_FOC_HWIQ_IQSWP	0x00B8
 +#define SSB_SPROM8_PHYCAL_TEMPDELTA	0x00BA
++
++/* There are 4 blocks with power info sharing the same layout */
++#define SSB_SROM8_PWR_INFO_CORE0	0x00C0
++#define SSB_SROM8_PWR_INFO_CORE1	0x00E0
++#define SSB_SROM8_PWR_INFO_CORE2	0x0100
++#define SSB_SROM8_PWR_INFO_CORE3	0x0120
++
++#define SSB_SROM8_2G_MAXP_ITSSI		0x00
++#define  SSB_SPROM8_2G_MAXP		0x00FF
++#define  SSB_SPROM8_2G_ITSSI		0xFF00
++#define  SSB_SPROM8_2G_ITSSI_SHIFT	8
++#define SSB_SROM8_2G_PA_0		0x02	/* 2GHz power amp settings */
++#define SSB_SROM8_2G_PA_1		0x04
++#define SSB_SROM8_2G_PA_2		0x06
++#define SSB_SROM8_5G_MAXP_ITSSI		0x08	/* 5GHz ITSSI and 5.3GHz Max Power */
++#define  SSB_SPROM8_5G_MAXP		0x00FF
++#define  SSB_SPROM8_5G_ITSSI		0xFF00
++#define  SSB_SPROM8_5G_ITSSI_SHIFT	8
++#define SSB_SPROM8_5GHL_MAXP		0x0A	/* 5.2GHz and 5.8GHz Max Power */
++#define  SSB_SPROM8_5GH_MAXP		0x00FF
++#define  SSB_SPROM8_5GL_MAXP		0xFF00
++#define  SSB_SPROM8_5GL_MAXP_SHIFT	8
++#define SSB_SROM8_5G_PA_0		0x0C	/* 5.3GHz power amp settings */
++#define SSB_SROM8_5G_PA_1		0x0E
++#define SSB_SROM8_5G_PA_2		0x10
++#define SSB_SROM8_5GL_PA_0		0x12	/* 5.2GHz power amp settings */
++#define SSB_SROM8_5GL_PA_1		0x14
++#define SSB_SROM8_5GL_PA_2		0x16
++#define SSB_SROM8_5GH_PA_0		0x18	/* 5.8GHz power amp settings */
++#define SSB_SROM8_5GH_PA_1		0x1A
++#define SSB_SROM8_5GH_PA_2		0x1C
++
++/* TODO: Make it deprecated */
  #define SSB_SPROM8_MAXP_BG		0x00C0  /* Max Power 2GHz in path 1 */
  #define  SSB_SPROM8_MAXP_BG_MASK	0x00FF  /* Mask for Max Power 2GHz */
  #define  SSB_SPROM8_ITSSI_BG		0xFF00	/* Mask for path 1 itssi_bg */
-@@ -417,6 +479,46 @@
+@@ -411,12 +506,53 @@
+ #define SSB_SPROM8_PA1HIB0		0x00D8	/* 5.8GHz power amp settings */
+ #define SSB_SPROM8_PA1HIB1		0x00DA
+ #define SSB_SPROM8_PA1HIB2		0x00DC
++
+ #define SSB_SPROM8_CCK2GPO		0x0140	/* CCK power offset */
+ #define SSB_SPROM8_OFDM2GPO		0x0142	/* 2.4GHz OFDM power offset */
+ #define SSB_SPROM8_OFDM5GPO		0x0146	/* 5.3GHz OFDM power offset */
  #define SSB_SPROM8_OFDM5GLPO		0x014A	/* 5.2GHz OFDM power offset */
  #define SSB_SPROM8_OFDM5GHPO		0x014E	/* 5.8GHz OFDM power offset */