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authorImre Kaloz <kaloz@openwrt.org>2011-03-18 13:40:48 +0000
committerImre Kaloz <kaloz@openwrt.org>2011-03-18 13:40:48 +0000
commita8d84ae94d0d5ebef14916d79cf0f10748e89bf4 (patch)
tree4d10bf83fcf15c10d44674e06b32effe8451234d /target/linux/generic/patches-2.6.34/975-ssb_update.patch
parentde69f84399125d33f593c1a2245ca9ff886b0ae7 (diff)
downloadupstream-a8d84ae94d0d5ebef14916d79cf0f10748e89bf4.tar.gz
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remove 2.6.34 support
SVN-Revision: 26229
Diffstat (limited to 'target/linux/generic/patches-2.6.34/975-ssb_update.patch')
-rw-r--r--target/linux/generic/patches-2.6.34/975-ssb_update.patch1517
1 files changed, 0 insertions, 1517 deletions
diff --git a/target/linux/generic/patches-2.6.34/975-ssb_update.patch b/target/linux/generic/patches-2.6.34/975-ssb_update.patch
deleted file mode 100644
index bfac252f85..0000000000
--- a/target/linux/generic/patches-2.6.34/975-ssb_update.patch
+++ /dev/null
@@ -1,1517 +0,0 @@
---- a/drivers/net/b44.c
-+++ b/drivers/net/b44.c
-@@ -135,7 +135,6 @@ static void b44_init_rings(struct b44 *)
-
- static void b44_init_hw(struct b44 *, int);
-
--static int dma_desc_align_mask;
- static int dma_desc_sync_size;
- static int instance;
-
-@@ -150,9 +149,8 @@ static inline void b44_sync_dma_desc_for
- unsigned long offset,
- enum dma_data_direction dir)
- {
-- ssb_dma_sync_single_range_for_device(sdev, dma_base,
-- offset & dma_desc_align_mask,
-- dma_desc_sync_size, dir);
-+ dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
-+ dma_desc_sync_size, dir);
- }
-
- static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
-@@ -160,9 +158,8 @@ static inline void b44_sync_dma_desc_for
- unsigned long offset,
- enum dma_data_direction dir)
- {
-- ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
-- offset & dma_desc_align_mask,
-- dma_desc_sync_size, dir);
-+ dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
-+ dma_desc_sync_size, dir);
- }
-
- static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
-@@ -608,10 +605,10 @@ static void b44_tx(struct b44 *bp)
-
- BUG_ON(skb == NULL);
-
-- ssb_dma_unmap_single(bp->sdev,
-- rp->mapping,
-- skb->len,
-- DMA_TO_DEVICE);
-+ dma_unmap_single(bp->sdev->dma_dev,
-+ rp->mapping,
-+ skb->len,
-+ DMA_TO_DEVICE);
- rp->skb = NULL;
- dev_kfree_skb_irq(skb);
- }
-@@ -648,29 +645,29 @@ static int b44_alloc_rx_skb(struct b44 *
- if (skb == NULL)
- return -ENOMEM;
-
-- mapping = ssb_dma_map_single(bp->sdev, skb->data,
-- RX_PKT_BUF_SZ,
-- DMA_FROM_DEVICE);
-+ mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
-+ RX_PKT_BUF_SZ,
-+ DMA_FROM_DEVICE);
-
- /* Hardware bug work-around, the chip is unable to do PCI DMA
- to/from anything above 1GB :-( */
-- if (ssb_dma_mapping_error(bp->sdev, mapping) ||
-+ if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
- mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
- /* Sigh... */
-- if (!ssb_dma_mapping_error(bp->sdev, mapping))
-- ssb_dma_unmap_single(bp->sdev, mapping,
-+ if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
-+ dma_unmap_single(bp->sdev->dma_dev, mapping,
- RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
- dev_kfree_skb_any(skb);
- skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
- if (skb == NULL)
- return -ENOMEM;
-- mapping = ssb_dma_map_single(bp->sdev, skb->data,
-- RX_PKT_BUF_SZ,
-- DMA_FROM_DEVICE);
-- if (ssb_dma_mapping_error(bp->sdev, mapping) ||
-- mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
-- if (!ssb_dma_mapping_error(bp->sdev, mapping))
-- ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
-+ mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
-+ RX_PKT_BUF_SZ,
-+ DMA_FROM_DEVICE);
-+ if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
-+ mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
-+ if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
-+ dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
- dev_kfree_skb_any(skb);
- return -ENOMEM;
- }
-@@ -745,9 +742,9 @@ static void b44_recycle_rx(struct b44 *b
- dest_idx * sizeof(*dest_desc),
- DMA_BIDIRECTIONAL);
-
-- ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
-- RX_PKT_BUF_SZ,
-- DMA_FROM_DEVICE);
-+ dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
-+ RX_PKT_BUF_SZ,
-+ DMA_FROM_DEVICE);
- }
-
- static int b44_rx(struct b44 *bp, int budget)
-@@ -767,9 +764,9 @@ static int b44_rx(struct b44 *bp, int bu
- struct rx_header *rh;
- u16 len;
-
-- ssb_dma_sync_single_for_cpu(bp->sdev, map,
-- RX_PKT_BUF_SZ,
-- DMA_FROM_DEVICE);
-+ dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
-+ RX_PKT_BUF_SZ,
-+ DMA_FROM_DEVICE);
- rh = (struct rx_header *) skb->data;
- len = le16_to_cpu(rh->len);
- if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
-@@ -801,8 +798,8 @@ static int b44_rx(struct b44 *bp, int bu
- skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
- if (skb_size < 0)
- goto drop_it;
-- ssb_dma_unmap_single(bp->sdev, map,
-- skb_size, DMA_FROM_DEVICE);
-+ dma_unmap_single(bp->sdev->dma_dev, map,
-+ skb_size, DMA_FROM_DEVICE);
- /* Leave out rx_header */
- skb_put(skb, len + RX_PKT_OFFSET);
- skb_pull(skb, RX_PKT_OFFSET);
-@@ -954,24 +951,24 @@ static netdev_tx_t b44_start_xmit(struct
- goto err_out;
- }
-
-- mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
-- if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
-+ mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
-+ if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
- struct sk_buff *bounce_skb;
-
- /* Chip can't handle DMA to/from >1GB, use bounce buffer */
-- if (!ssb_dma_mapping_error(bp->sdev, mapping))
-- ssb_dma_unmap_single(bp->sdev, mapping, len,
-+ if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
-+ dma_unmap_single(bp->sdev->dma_dev, mapping, len,
- DMA_TO_DEVICE);
-
- bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
- if (!bounce_skb)
- goto err_out;
-
-- mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
-- len, DMA_TO_DEVICE);
-- if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
-- if (!ssb_dma_mapping_error(bp->sdev, mapping))
-- ssb_dma_unmap_single(bp->sdev, mapping,
-+ mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
-+ len, DMA_TO_DEVICE);
-+ if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
-+ if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
-+ dma_unmap_single(bp->sdev->dma_dev, mapping,
- len, DMA_TO_DEVICE);
- dev_kfree_skb_any(bounce_skb);
- goto err_out;
-@@ -1014,8 +1011,6 @@ static netdev_tx_t b44_start_xmit(struct
- if (TX_BUFFS_AVAIL(bp) < 1)
- netif_stop_queue(dev);
-
-- dev->trans_start = jiffies;
--
- out_unlock:
- spin_unlock_irqrestore(&bp->lock, flags);
-
-@@ -1070,8 +1065,8 @@ static void b44_free_rings(struct b44 *b
-
- if (rp->skb == NULL)
- continue;
-- ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
-- DMA_FROM_DEVICE);
-+ dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
-+ DMA_FROM_DEVICE);
- dev_kfree_skb_any(rp->skb);
- rp->skb = NULL;
- }
-@@ -1082,8 +1077,8 @@ static void b44_free_rings(struct b44 *b
-
- if (rp->skb == NULL)
- continue;
-- ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
-- DMA_TO_DEVICE);
-+ dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
-+ DMA_TO_DEVICE);
- dev_kfree_skb_any(rp->skb);
- rp->skb = NULL;
- }
-@@ -1105,14 +1100,12 @@ static void b44_init_rings(struct b44 *b
- memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
-
- if (bp->flags & B44_FLAG_RX_RING_HACK)
-- ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
-- DMA_TABLE_BYTES,
-- DMA_BIDIRECTIONAL);
-+ dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
-+ DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
-
- if (bp->flags & B44_FLAG_TX_RING_HACK)
-- ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
-- DMA_TABLE_BYTES,
-- DMA_TO_DEVICE);
-+ dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
-+ DMA_TABLE_BYTES, DMA_TO_DEVICE);
-
- for (i = 0; i < bp->rx_pending; i++) {
- if (b44_alloc_rx_skb(bp, -1, i) < 0)
-@@ -1132,27 +1125,23 @@ static void b44_free_consistent(struct b
- bp->tx_buffers = NULL;
- if (bp->rx_ring) {
- if (bp->flags & B44_FLAG_RX_RING_HACK) {
-- ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
-- DMA_TABLE_BYTES,
-- DMA_BIDIRECTIONAL);
-+ dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
-+ DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
- kfree(bp->rx_ring);
- } else
-- ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
-- bp->rx_ring, bp->rx_ring_dma,
-- GFP_KERNEL);
-+ dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
-+ bp->rx_ring, bp->rx_ring_dma);
- bp->rx_ring = NULL;
- bp->flags &= ~B44_FLAG_RX_RING_HACK;
- }
- if (bp->tx_ring) {
- if (bp->flags & B44_FLAG_TX_RING_HACK) {
-- ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
-- DMA_TABLE_BYTES,
-- DMA_TO_DEVICE);
-+ dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
-+ DMA_TABLE_BYTES, DMA_TO_DEVICE);
- kfree(bp->tx_ring);
- } else
-- ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
-- bp->tx_ring, bp->tx_ring_dma,
-- GFP_KERNEL);
-+ dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
-+ bp->tx_ring, bp->tx_ring_dma);
- bp->tx_ring = NULL;
- bp->flags &= ~B44_FLAG_TX_RING_HACK;
- }
-@@ -1177,7 +1166,8 @@ static int b44_alloc_consistent(struct b
- goto out_err;
-
- size = DMA_TABLE_BYTES;
-- bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
-+ bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
-+ &bp->rx_ring_dma, gfp);
- if (!bp->rx_ring) {
- /* Allocation may have failed due to pci_alloc_consistent
- insisting on use of GFP_DMA, which is more restrictive
-@@ -1189,11 +1179,11 @@ static int b44_alloc_consistent(struct b
- if (!rx_ring)
- goto out_err;
-
-- rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
-- DMA_TABLE_BYTES,
-- DMA_BIDIRECTIONAL);
-+ rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
-+ DMA_TABLE_BYTES,
-+ DMA_BIDIRECTIONAL);
-
-- if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
-+ if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
- rx_ring_dma + size > DMA_BIT_MASK(30)) {
- kfree(rx_ring);
- goto out_err;
-@@ -1204,7 +1194,8 @@ static int b44_alloc_consistent(struct b
- bp->flags |= B44_FLAG_RX_RING_HACK;
- }
-
-- bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
-+ bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
-+ &bp->tx_ring_dma, gfp);
- if (!bp->tx_ring) {
- /* Allocation may have failed due to ssb_dma_alloc_consistent
- insisting on use of GFP_DMA, which is more restrictive
-@@ -1216,11 +1207,11 @@ static int b44_alloc_consistent(struct b
- if (!tx_ring)
- goto out_err;
-
-- tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
-- DMA_TABLE_BYTES,
-- DMA_TO_DEVICE);
-+ tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
-+ DMA_TABLE_BYTES,
-+ DMA_TO_DEVICE);
-
-- if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
-+ if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
- tx_ring_dma + size > DMA_BIT_MASK(30)) {
- kfree(tx_ring);
- goto out_err;
-@@ -2176,12 +2167,14 @@ static int __devinit b44_init_one(struct
- "Failed to powerup the bus\n");
- goto err_out_free_dev;
- }
-- err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
-- if (err) {
-+
-+ if (dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(30)) ||
-+ dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(30))) {
- dev_err(sdev->dev,
- "Required 30BIT DMA mask unsupported by the system\n");
- goto err_out_powerdown;
- }
-+
- err = b44_get_invariants(bp);
- if (err) {
- dev_err(sdev->dev,
-@@ -2346,7 +2339,6 @@ static int __init b44_init(void)
- int err;
-
- /* Setup paramaters for syncing RX/TX DMA descriptors */
-- dma_desc_align_mask = ~(dma_desc_align_size - 1);
- dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
-
- err = b44_pci_init();
---- a/drivers/ssb/b43_pci_bridge.c
-+++ b/drivers/ssb/b43_pci_bridge.c
-@@ -24,6 +24,7 @@ static const struct pci_device_id b43_pc
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
-+ { PCI_DEVICE(PCI_VENDOR_ID_BCM_GVC, 0x4318) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
- { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
---- a/drivers/ssb/driver_chipcommon.c
-+++ b/drivers/ssb/driver_chipcommon.c
-@@ -209,6 +209,24 @@ static void chipco_powercontrol_init(str
- }
- }
-
-+/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
-+static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
-+{
-+ struct ssb_bus *bus = cc->dev->bus;
-+
-+ switch (bus->chip_id) {
-+ case 0x4312:
-+ case 0x4322:
-+ case 0x4328:
-+ return 7000;
-+ case 0x4325:
-+ /* TODO: */
-+ default:
-+ return 15000;
-+ }
-+}
-+
-+/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
- static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
- {
- struct ssb_bus *bus = cc->dev->bus;
-@@ -218,6 +236,12 @@ static void calc_fast_powerup_delay(stru
-
- if (bus->bustype != SSB_BUSTYPE_PCI)
- return;
-+
-+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
-+ cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
-+ return;
-+ }
-+
- if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
- return;
-
-@@ -373,6 +397,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
- {
- return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
- }
-+EXPORT_SYMBOL(ssb_chipco_gpio_control);
-
- u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
- {
---- a/drivers/ssb/driver_chipcommon_pmu.c
-+++ b/drivers/ssb/driver_chipcommon_pmu.c
-@@ -502,9 +502,9 @@ static void ssb_pmu_resources_init(struc
- chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
- }
-
-+/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
- void ssb_pmu_init(struct ssb_chipcommon *cc)
- {
-- struct ssb_bus *bus = cc->dev->bus;
- u32 pmucap;
-
- if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
-@@ -516,15 +516,12 @@ void ssb_pmu_init(struct ssb_chipcommon
- ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
- cc->pmu.rev, pmucap);
-
-- if (cc->pmu.rev >= 1) {
-- if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
-- chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
-- ~SSB_CHIPCO_PMU_CTL_NOILPONW);
-- } else {
-- chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
-- SSB_CHIPCO_PMU_CTL_NOILPONW);
-- }
-- }
-+ if (cc->pmu.rev == 1)
-+ chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
-+ ~SSB_CHIPCO_PMU_CTL_NOILPONW);
-+ else
-+ chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
-+ SSB_CHIPCO_PMU_CTL_NOILPONW);
- ssb_pmu_pll_init(cc);
- ssb_pmu_resources_init(cc);
- }
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -385,6 +385,35 @@ static int ssb_device_uevent(struct devi
- ssb_dev->id.revision);
- }
-
-+#define ssb_config_attr(attrib, field, format_string) \
-+static ssize_t \
-+attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
-+{ \
-+ return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
-+}
-+
-+ssb_config_attr(core_num, core_index, "%u\n")
-+ssb_config_attr(coreid, id.coreid, "0x%04x\n")
-+ssb_config_attr(vendor, id.vendor, "0x%04x\n")
-+ssb_config_attr(revision, id.revision, "%u\n")
-+ssb_config_attr(irq, irq, "%u\n")
-+static ssize_t
-+name_show(struct device *dev, struct device_attribute *attr, char *buf)
-+{
-+ return sprintf(buf, "%s\n",
-+ ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
-+}
-+
-+static struct device_attribute ssb_device_attrs[] = {
-+ __ATTR_RO(name),
-+ __ATTR_RO(core_num),
-+ __ATTR_RO(coreid),
-+ __ATTR_RO(vendor),
-+ __ATTR_RO(revision),
-+ __ATTR_RO(irq),
-+ __ATTR_NULL,
-+};
-+
- static struct bus_type ssb_bustype = {
- .name = "ssb",
- .match = ssb_bus_match,
-@@ -394,6 +423,7 @@ static struct bus_type ssb_bustype = {
- .suspend = ssb_device_suspend,
- .resume = ssb_device_resume,
- .uevent = ssb_device_uevent,
-+ .dev_attrs = ssb_device_attrs,
- };
-
- static void ssb_buses_lock(void)
-@@ -486,6 +516,7 @@ static int ssb_devices_register(struct s
- #ifdef CONFIG_SSB_PCIHOST
- sdev->irq = bus->host_pci->irq;
- dev->parent = &bus->host_pci->dev;
-+ sdev->dma_dev = dev->parent;
- #endif
- break;
- case SSB_BUSTYPE_PCMCIA:
-@@ -501,6 +532,7 @@ static int ssb_devices_register(struct s
- break;
- case SSB_BUSTYPE_SSB:
- dev->dma_mask = &dev->coherent_dma_mask;
-+ sdev->dma_dev = dev;
- break;
- }
-
-@@ -834,6 +866,9 @@ int ssb_bus_pcibus_register(struct ssb_b
- if (!err) {
- ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
- "PCI device %s\n", dev_name(&host_pci->dev));
-+ } else {
-+ ssb_printk(KERN_ERR PFX "Failed to register PCI version"
-+ " of SSB with error %d\n", err);
- }
-
- return err;
-@@ -1159,10 +1194,10 @@ void ssb_device_enable(struct ssb_device
- }
- EXPORT_SYMBOL(ssb_device_enable);
-
--/* Wait for a bit in a register to get set or unset.
-+/* Wait for bitmask in a register to get set or cleared.
- * timeout is in units of ten-microseconds */
--static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
-- int timeout, int set)
-+static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
-+ int timeout, int set)
- {
- int i;
- u32 val;
-@@ -1170,7 +1205,7 @@ static int ssb_wait_bit(struct ssb_devic
- for (i = 0; i < timeout; i++) {
- val = ssb_read32(dev, reg);
- if (set) {
-- if (val & bitmask)
-+ if ((val & bitmask) == bitmask)
- return 0;
- } else {
- if (!(val & bitmask))
-@@ -1187,20 +1222,38 @@ static int ssb_wait_bit(struct ssb_devic
-
- void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
- {
-- u32 reject;
-+ u32 reject, val;
-
- if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
- return;
-
- reject = ssb_tmslow_reject_bitmask(dev);
-- ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
-- ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
-- ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
-- ssb_write32(dev, SSB_TMSLOW,
-- SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
-- reject | SSB_TMSLOW_RESET |
-- core_specific_flags);
-- ssb_flush_tmslow(dev);
-+
-+ if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
-+ ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
-+ ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
-+ ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
-+
-+ if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
-+ val = ssb_read32(dev, SSB_IMSTATE);
-+ val |= SSB_IMSTATE_REJECT;
-+ ssb_write32(dev, SSB_IMSTATE, val);
-+ ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
-+ 0);
-+ }
-+
-+ ssb_write32(dev, SSB_TMSLOW,
-+ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
-+ reject | SSB_TMSLOW_RESET |
-+ core_specific_flags);
-+ ssb_flush_tmslow(dev);
-+
-+ if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
-+ val = ssb_read32(dev, SSB_IMSTATE);
-+ val &= ~SSB_IMSTATE_REJECT;
-+ ssb_write32(dev, SSB_IMSTATE, val);
-+ }
-+ }
-
- ssb_write32(dev, SSB_TMSLOW,
- reject | SSB_TMSLOW_RESET |
-@@ -1223,80 +1276,6 @@ u32 ssb_dma_translation(struct ssb_devic
- }
- EXPORT_SYMBOL(ssb_dma_translation);
-
--int ssb_dma_set_mask(struct ssb_device *dev, u64 mask)
--{
--#ifdef CONFIG_SSB_PCIHOST
-- int err;
--#endif
--
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- err = pci_set_dma_mask(dev->bus->host_pci, mask);
-- if (err)
-- return err;
-- err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask);
-- return err;
--#endif
-- case SSB_BUSTYPE_SSB:
-- return dma_set_mask(dev->dev, mask);
-- default:
-- __ssb_dma_not_implemented(dev);
-- }
-- return -ENOSYS;
--}
--EXPORT_SYMBOL(ssb_dma_set_mask);
--
--void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
-- dma_addr_t *dma_handle, gfp_t gfp_flags)
--{
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- if (gfp_flags & GFP_DMA) {
-- /* Workaround: The PCI API does not support passing
-- * a GFP flag. */
-- return dma_alloc_coherent(&dev->bus->host_pci->dev,
-- size, dma_handle, gfp_flags);
-- }
-- return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle);
--#endif
-- case SSB_BUSTYPE_SSB:
-- return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags);
-- default:
-- __ssb_dma_not_implemented(dev);
-- }
-- return NULL;
--}
--EXPORT_SYMBOL(ssb_dma_alloc_consistent);
--
--void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
-- void *vaddr, dma_addr_t dma_handle,
-- gfp_t gfp_flags)
--{
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- if (gfp_flags & GFP_DMA) {
-- /* Workaround: The PCI API does not support passing
-- * a GFP flag. */
-- dma_free_coherent(&dev->bus->host_pci->dev,
-- size, vaddr, dma_handle);
-- return;
-- }
-- pci_free_consistent(dev->bus->host_pci, size,
-- vaddr, dma_handle);
-- return;
--#endif
-- case SSB_BUSTYPE_SSB:
-- dma_free_coherent(dev->dev, size, vaddr, dma_handle);
-- return;
-- default:
-- __ssb_dma_not_implemented(dev);
-- }
--}
--EXPORT_SYMBOL(ssb_dma_free_consistent);
--
- int ssb_bus_may_powerdown(struct ssb_bus *bus)
- {
- struct ssb_chipcommon *cc;
---- a/drivers/ssb/pci.c
-+++ b/drivers/ssb/pci.c
-@@ -168,7 +168,7 @@ err_pci:
- }
-
- /* Get the word-offset for a SSB_SPROM_XXX define. */
--#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16))
-+#define SPOFF(offset) ((offset) / sizeof(u16))
- /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
- #define SPEX16(_outvar, _offset, _mask, _shift) \
- out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
-@@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ss
- out->antenna_gain.ghz5.a3 = gain;
- }
-
-+/* Revs 4 5 and 8 have partially shared layout */
-+static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
-+{
-+ SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
-+ SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
-+ SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
-+ SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
-+ SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
-+ SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
-+ SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
-+ SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
-+
-+ SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
-+ SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
-+ SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
-+ SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
-+ SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
-+ SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
-+ SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
-+ SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
-+
-+ SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
-+ SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
-+ SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
-+ SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
-+ SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
-+ SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
-+ SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
-+ SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
-+
-+ SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
-+ SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
-+ SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
-+ SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
-+ SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
-+ SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
-+ SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
-+ SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
-+}
-+
- static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
- {
- int i;
-@@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb
- SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
- SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
- SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
-+ SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
-+ SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
- } else {
- SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
- SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
- SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
-+ SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
-+ SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
- }
- SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
- SSB_SPROM4_ANTAVAIL_A_SHIFT);
-@@ -471,6 +515,8 @@ static void sprom_extract_r45(struct ssb
- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
- sizeof(out->antenna_gain.ghz5));
-
-+ sprom_extract_r458(out, in);
-+
- /* TODO - get remaining rev 4 stuff needed */
- }
-
-@@ -561,6 +607,8 @@ static void sprom_extract_r8(struct ssb_
- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
- sizeof(out->antenna_gain.ghz5));
-
-+ sprom_extract_r458(out, in);
-+
- /* TODO - get remaining rev 8 stuff needed */
- }
-
-@@ -573,37 +621,34 @@ static int sprom_extract(struct ssb_bus
- ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
- memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
- memset(out->et1mac, 0xFF, 6);
-+
- if ((bus->chip_id & 0xFF00) == 0x4400) {
- /* Workaround: The BCM44XX chip has a stupid revision
- * number stored in the SPROM.
- * Always extract r1. */
- out->revision = 1;
-+ ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
-+ }
-+
-+ switch (out->revision) {
-+ case 1:
-+ case 2:
-+ case 3:
- sprom_extract_r123(out, in);
-- } else if (bus->chip_id == 0x4321) {
-- /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
-- out->revision = 4;
-+ break;
-+ case 4:
-+ case 5:
- sprom_extract_r45(out, in);
-- } else {
-- switch (out->revision) {
-- case 1:
-- case 2:
-- case 3:
-- sprom_extract_r123(out, in);
-- break;
-- case 4:
-- case 5:
-- sprom_extract_r45(out, in);
-- break;
-- case 8:
-- sprom_extract_r8(out, in);
-- break;
-- default:
-- ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
-- " revision %d detected. Will extract"
-- " v1\n", out->revision);
-- out->revision = 1;
-- sprom_extract_r123(out, in);
-- }
-+ break;
-+ case 8:
-+ sprom_extract_r8(out, in);
-+ break;
-+ default:
-+ ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
-+ " revision %d detected. Will extract"
-+ " v1\n", out->revision);
-+ out->revision = 1;
-+ sprom_extract_r123(out, in);
- }
-
- if (out->boardflags_lo == 0xFFFF)
-@@ -618,7 +663,7 @@ static int ssb_pci_sprom_get(struct ssb_
- struct ssb_sprom *sprom)
- {
- const struct ssb_sprom *fallback;
-- int err = -ENOMEM;
-+ int err;
- u16 *buf;
-
- if (!ssb_is_sprom_available(bus)) {
-@@ -645,7 +690,7 @@ static int ssb_pci_sprom_get(struct ssb_
-
- buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
- if (!buf)
-- goto out;
-+ return -ENOMEM;
- bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
- sprom_do_read(bus, buf);
- err = sprom_check_crc(buf, bus->sprom_size);
-@@ -655,7 +700,7 @@ static int ssb_pci_sprom_get(struct ssb_
- buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
- GFP_KERNEL);
- if (!buf)
-- goto out;
-+ return -ENOMEM;
- bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
- sprom_do_read(bus, buf);
- err = sprom_check_crc(buf, bus->sprom_size);
-@@ -677,7 +722,6 @@ static int ssb_pci_sprom_get(struct ssb_
-
- out_free:
- kfree(buf);
--out:
- return err;
- }
-
---- a/drivers/ssb/pcihost_wrapper.c
-+++ b/drivers/ssb/pcihost_wrapper.c
-@@ -59,6 +59,7 @@ static int ssb_pcihost_probe(struct pci_
- struct ssb_bus *ssb;
- int err = -ENOMEM;
- const char *name;
-+ u32 val;
-
- ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
- if (!ssb)
-@@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
- goto err_pci_disable;
- pci_set_master(dev);
-
-+ /* Disable the RETRY_TIMEOUT register (0x41) to keep
-+ * PCI Tx retries from interfering with C3 CPU state */
-+ pci_read_config_dword(dev, 0x40, &val);
-+ if ((val & 0x0000ff00) != 0)
-+ pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
-+
- err = ssb_bus_pcibus_register(ssb, dev);
- if (err)
- goto err_pci_release_regions;
---- a/drivers/ssb/pcmcia.c
-+++ b/drivers/ssb/pcmcia.c
-@@ -745,7 +745,7 @@ int ssb_pcmcia_get_invariants(struct ssb
-
- /* Fetch the vendor specific tuples. */
- res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
-- ssb_pcmcia_do_get_invariants, sprom);
-+ ssb_pcmcia_do_get_invariants, iv);
- if ((res == 0) || (res == -ENOSPC))
- return 0;
-
---- a/drivers/ssb/scan.c
-+++ b/drivers/ssb/scan.c
-@@ -407,10 +407,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
- /* Ignore PCI cores on PCI-E cards.
- * Ignore PCI-E cores on PCI cards. */
- if (dev->id.coreid == SSB_DEV_PCI) {
-- if (bus->host_pci->is_pcie)
-+ if (pci_is_pcie(bus->host_pci))
- continue;
- } else {
-- if (!bus->host_pci->is_pcie)
-+ if (!pci_is_pcie(bus->host_pci))
- continue;
- }
- }
-@@ -422,6 +422,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
- bus->pcicore.dev = dev;
- #endif /* CONFIG_SSB_DRIVER_PCICORE */
- break;
-+ case SSB_DEV_ETHERNET:
-+ if (bus->bustype == SSB_BUSTYPE_PCI) {
-+ if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
-+ (bus->host_pci->device & 0xFF00) == 0x4300) {
-+ /* This is a dangling ethernet core on a
-+ * wireless device. Ignore it. */
-+ continue;
-+ }
-+ }
-+ break;
- default:
- break;
- }
---- a/include/linux/pci_ids.h
-+++ b/include/linux/pci_ids.h
-@@ -2038,6 +2038,7 @@
- #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
- #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
-
-+#define PCI_VENDOR_ID_BCM_GVC 0x14a4
- #define PCI_VENDOR_ID_BROADCOM 0x14e4
- #define PCI_DEVICE_ID_TIGON3_5752 0x1600
- #define PCI_DEVICE_ID_TIGON3_5752M 0x1601
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -55,6 +55,10 @@ struct ssb_sprom {
- u8 tri5gl; /* 5.2GHz TX isolation */
- u8 tri5g; /* 5.3GHz TX isolation */
- u8 tri5gh; /* 5.8GHz TX isolation */
-+ u8 txpid2g[4]; /* 2GHz TX power index */
-+ u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
-+ u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
-+ u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
- u8 rxpo2g; /* 2GHz RX power offset */
- u8 rxpo5g; /* 5GHz RX power offset */
- u8 rssisav2g; /* 2GHz RSSI params */
-@@ -167,7 +171,7 @@ struct ssb_device {
- * is an optimization. */
- const struct ssb_bus_ops *ops;
-
-- struct device *dev;
-+ struct device *dev, *dma_dev;
-
- struct ssb_bus *bus;
- struct ssb_device_id id;
-@@ -470,14 +474,6 @@ extern u32 ssb_dma_translation(struct ss
- #define SSB_DMA_TRANSLATION_MASK 0xC0000000
- #define SSB_DMA_TRANSLATION_SHIFT 30
-
--extern int ssb_dma_set_mask(struct ssb_device *dev, u64 mask);
--
--extern void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
-- dma_addr_t *dma_handle, gfp_t gfp_flags);
--extern void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
-- void *vaddr, dma_addr_t dma_handle,
-- gfp_t gfp_flags);
--
- static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
- {
- #ifdef CONFIG_SSB_DEBUG
-@@ -486,155 +482,6 @@ static inline void __cold __ssb_dma_not_
- #endif /* DEBUG */
- }
-
--static inline int ssb_dma_mapping_error(struct ssb_device *dev, dma_addr_t addr)
--{
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- return pci_dma_mapping_error(dev->bus->host_pci, addr);
--#endif
-- break;
-- case SSB_BUSTYPE_SSB:
-- return dma_mapping_error(dev->dev, addr);
-- default:
-- break;
-- }
-- __ssb_dma_not_implemented(dev);
-- return -ENOSYS;
--}
--
--static inline dma_addr_t ssb_dma_map_single(struct ssb_device *dev, void *p,
-- size_t size, enum dma_data_direction dir)
--{
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- return pci_map_single(dev->bus->host_pci, p, size, dir);
--#endif
-- break;
-- case SSB_BUSTYPE_SSB:
-- return dma_map_single(dev->dev, p, size, dir);
-- default:
-- break;
-- }
-- __ssb_dma_not_implemented(dev);
-- return 0;
--}
--
--static inline void ssb_dma_unmap_single(struct ssb_device *dev, dma_addr_t dma_addr,
-- size_t size, enum dma_data_direction dir)
--{
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- pci_unmap_single(dev->bus->host_pci, dma_addr, size, dir);
-- return;
--#endif
-- break;
-- case SSB_BUSTYPE_SSB:
-- dma_unmap_single(dev->dev, dma_addr, size, dir);
-- return;
-- default:
-- break;
-- }
-- __ssb_dma_not_implemented(dev);
--}
--
--static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev,
-- dma_addr_t dma_addr,
-- size_t size,
-- enum dma_data_direction dir)
--{
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
-- size, dir);
-- return;
--#endif
-- break;
-- case SSB_BUSTYPE_SSB:
-- dma_sync_single_for_cpu(dev->dev, dma_addr, size, dir);
-- return;
-- default:
-- break;
-- }
-- __ssb_dma_not_implemented(dev);
--}
--
--static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev,
-- dma_addr_t dma_addr,
-- size_t size,
-- enum dma_data_direction dir)
--{
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
-- size, dir);
-- return;
--#endif
-- break;
-- case SSB_BUSTYPE_SSB:
-- dma_sync_single_for_device(dev->dev, dma_addr, size, dir);
-- return;
-- default:
-- break;
-- }
-- __ssb_dma_not_implemented(dev);
--}
--
--static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev,
-- dma_addr_t dma_addr,
-- unsigned long offset,
-- size_t size,
-- enum dma_data_direction dir)
--{
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- /* Just sync everything. That's all the PCI API can do. */
-- pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
-- offset + size, dir);
-- return;
--#endif
-- break;
-- case SSB_BUSTYPE_SSB:
-- dma_sync_single_range_for_cpu(dev->dev, dma_addr, offset,
-- size, dir);
-- return;
-- default:
-- break;
-- }
-- __ssb_dma_not_implemented(dev);
--}
--
--static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev,
-- dma_addr_t dma_addr,
-- unsigned long offset,
-- size_t size,
-- enum dma_data_direction dir)
--{
-- switch (dev->bus->bustype) {
-- case SSB_BUSTYPE_PCI:
--#ifdef CONFIG_SSB_PCIHOST
-- /* Just sync everything. That's all the PCI API can do. */
-- pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
-- offset + size, dir);
-- return;
--#endif
-- break;
-- case SSB_BUSTYPE_SSB:
-- dma_sync_single_range_for_device(dev->dev, dma_addr, offset,
-- size, dir);
-- return;
-- default:
-- break;
-- }
-- __ssb_dma_not_implemented(dev);
--}
--
--
- #ifdef CONFIG_SSB_PCIHOST
- /* PCI-host wrapper driver */
- extern int ssb_pcihost_register(struct pci_driver *driver);
---- a/include/linux/ssb/ssb_regs.h
-+++ b/include/linux/ssb/ssb_regs.h
-@@ -85,6 +85,8 @@
- #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
- #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
- #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
-+#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
-+#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
- #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
- #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
- #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
-@@ -172,25 +174,25 @@
- #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
- #define SSB_SPROM_BASE1 0x1000
- #define SSB_SPROM_BASE31 0x0800
--#define SSB_SPROM_REVISION 0x107E
-+#define SSB_SPROM_REVISION 0x007E
- #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
- #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
- #define SSB_SPROM_REVISION_CRC_SHIFT 8
-
- /* SPROM Revision 1 */
--#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
--#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
--#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
--#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
--#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
--#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
--#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
-+#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
-+#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
-+#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
-+#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
-+#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
-+#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
-+#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
- #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
- #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
- #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
- #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
- #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
--#define SSB_SPROM1_BINF 0x105C /* Board info */
-+#define SSB_SPROM1_BINF 0x005C /* Board info */
- #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
- #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
- #define SSB_SPROM1_BINF_CCODE_SHIFT 8
-@@ -198,63 +200,63 @@
- #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
- #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
- #define SSB_SPROM1_BINF_ANTA_SHIFT 14
--#define SSB_SPROM1_PA0B0 0x105E
--#define SSB_SPROM1_PA0B1 0x1060
--#define SSB_SPROM1_PA0B2 0x1062
--#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
-+#define SSB_SPROM1_PA0B0 0x005E
-+#define SSB_SPROM1_PA0B1 0x0060
-+#define SSB_SPROM1_PA0B2 0x0062
-+#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
- #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
- #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
- #define SSB_SPROM1_GPIOA_P1_SHIFT 8
--#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
-+#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
- #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
- #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
- #define SSB_SPROM1_GPIOB_P3_SHIFT 8
--#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
-+#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
- #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
- #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
- #define SSB_SPROM1_MAXPWR_A_SHIFT 8
--#define SSB_SPROM1_PA1B0 0x106A
--#define SSB_SPROM1_PA1B1 0x106C
--#define SSB_SPROM1_PA1B2 0x106E
--#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
-+#define SSB_SPROM1_PA1B0 0x006A
-+#define SSB_SPROM1_PA1B1 0x006C
-+#define SSB_SPROM1_PA1B2 0x006E
-+#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
- #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
- #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
- #define SSB_SPROM1_ITSSI_A_SHIFT 8
--#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
--#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
-+#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
-+#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
- #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
- #define SSB_SPROM1_AGAIN_BG_SHIFT 0
- #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
- #define SSB_SPROM1_AGAIN_A_SHIFT 8
-
- /* SPROM Revision 2 (inherits from rev 1) */
--#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
--#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
-+#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
-+#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
- #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
- #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
- #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
--#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
--#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
--#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
--#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
--#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
--#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
--#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
-+#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
-+#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
-+#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
-+#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
-+#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
-+#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
-+#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
- #define SSB_SPROM2_OPO_VALUE 0x00FF
- #define SSB_SPROM2_OPO_UNUSED 0xFF00
--#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
-+#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
-
- /* SPROM Revision 3 (inherits most data from rev 2) */
--#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
--#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
--#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
--#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
--#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
-+#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
-+#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
-+#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
-+#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
- #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
- #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
- #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
- #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
--#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
-+#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
-+#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
- #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
- #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
- #define SSB_SPROM3_CCKPO_2M_SHIFT 4
-@@ -265,100 +267,144 @@
- #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
-
- /* SPROM Revision 4 */
--#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
--#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
-+#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
-+#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
-+#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
-+#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
-+#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
-+#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
-+#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
-+#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
-+#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
-+#define SSB_SPROM4_GPIOA_P1_SHIFT 8
-+#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
-+#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
-+#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
-+#define SSB_SPROM4_GPIOB_P3_SHIFT 8
-+#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
- #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
- #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
- #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
- #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
- #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
--#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
--#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
--#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
--#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
--#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
--#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
--#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
--#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
-+#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
-+#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
-+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
-+#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
-+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
-+#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
- #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
- #define SSB_SPROM4_AGAIN0_SHIFT 0
- #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
- #define SSB_SPROM4_AGAIN1_SHIFT 8
--#define SSB_SPROM4_AGAIN23 0x1060
-+#define SSB_SPROM4_AGAIN23 0x0060
- #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
- #define SSB_SPROM4_AGAIN2_SHIFT 0
- #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
- #define SSB_SPROM4_AGAIN3_SHIFT 8
--#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
--#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
-+#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
-+#define SSB_SPROM4_TXPID2G0 0x00FF
-+#define SSB_SPROM4_TXPID2G0_SHIFT 0
-+#define SSB_SPROM4_TXPID2G1 0xFF00
-+#define SSB_SPROM4_TXPID2G1_SHIFT 8
-+#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
-+#define SSB_SPROM4_TXPID2G2 0x00FF
-+#define SSB_SPROM4_TXPID2G2_SHIFT 0
-+#define SSB_SPROM4_TXPID2G3 0xFF00
-+#define SSB_SPROM4_TXPID2G3_SHIFT 8
-+#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
-+#define SSB_SPROM4_TXPID5G0 0x00FF
-+#define SSB_SPROM4_TXPID5G0_SHIFT 0
-+#define SSB_SPROM4_TXPID5G1 0xFF00
-+#define SSB_SPROM4_TXPID5G1_SHIFT 8
-+#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
-+#define SSB_SPROM4_TXPID5G2 0x00FF
-+#define SSB_SPROM4_TXPID5G2_SHIFT 0
-+#define SSB_SPROM4_TXPID5G3 0xFF00
-+#define SSB_SPROM4_TXPID5G3_SHIFT 8
-+#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
-+#define SSB_SPROM4_TXPID5GL0 0x00FF
-+#define SSB_SPROM4_TXPID5GL0_SHIFT 0
-+#define SSB_SPROM4_TXPID5GL1 0xFF00
-+#define SSB_SPROM4_TXPID5GL1_SHIFT 8
-+#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
-+#define SSB_SPROM4_TXPID5GL2 0x00FF
-+#define SSB_SPROM4_TXPID5GL2_SHIFT 0
-+#define SSB_SPROM4_TXPID5GL3 0xFF00
-+#define SSB_SPROM4_TXPID5GL3_SHIFT 8
-+#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
-+#define SSB_SPROM4_TXPID5GH0 0x00FF
-+#define SSB_SPROM4_TXPID5GH0_SHIFT 0
-+#define SSB_SPROM4_TXPID5GH1 0xFF00
-+#define SSB_SPROM4_TXPID5GH1_SHIFT 8
-+#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
-+#define SSB_SPROM4_TXPID5GH2 0x00FF
-+#define SSB_SPROM4_TXPID5GH2_SHIFT 0
-+#define SSB_SPROM4_TXPID5GH3 0xFF00
-+#define SSB_SPROM4_TXPID5GH3_SHIFT 8
-+#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
- #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
- #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
- #define SSB_SPROM4_ITSSI_BG_SHIFT 8
--#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
-+#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
- #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
- #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
- #define SSB_SPROM4_ITSSI_A_SHIFT 8
--#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
--#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
--#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
--#define SSB_SPROM4_GPIOA_P1_SHIFT 8
--#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
--#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
--#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
--#define SSB_SPROM4_GPIOB_P3_SHIFT 8
--#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
--#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
--#define SSB_SPROM4_PA0B2 0x1086
--#define SSB_SPROM4_PA1B0 0x108E
--#define SSB_SPROM4_PA1B1 0x1090
--#define SSB_SPROM4_PA1B2 0x1092
-+#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
-+#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
-+#define SSB_SPROM4_PA0B2 0x0086
-+#define SSB_SPROM4_PA1B0 0x008E
-+#define SSB_SPROM4_PA1B1 0x0090
-+#define SSB_SPROM4_PA1B2 0x0092
-
- /* SPROM Revision 5 (inherits most data from rev 4) */
--#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
--#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
--#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
--#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
--#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
-+#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
-+#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
-+#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
-+#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
-+#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
-+#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
-+#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
- #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
- #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
- #define SSB_SPROM5_GPIOA_P1_SHIFT 8
--#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
-+#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
- #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
- #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
- #define SSB_SPROM5_GPIOB_P3_SHIFT 8
-
- /* SPROM Revision 8 */
--#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
--#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
--#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
--#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
--#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
--#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
--#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
--#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
--#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
--#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
--#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
--#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
--#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
-+#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
-+#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
-+#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
-+#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
-+#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
-+#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
-+#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
-+#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
-+#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
-+#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
-+#define SSB_SPROM8_GPIOA_P1_SHIFT 8
-+#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
-+#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
-+#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
-+#define SSB_SPROM8_GPIOB_P3_SHIFT 8
-+#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
-+#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
-+#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
-+#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
-+#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
-+#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
- #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
- #define SSB_SPROM8_AGAIN0_SHIFT 0
- #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
- #define SSB_SPROM8_AGAIN1_SHIFT 8
--#define SSB_SPROM8_AGAIN23 0x10A0
-+#define SSB_SPROM8_AGAIN23 0x00A0
- #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
- #define SSB_SPROM8_AGAIN2_SHIFT 0
- #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
- #define SSB_SPROM8_AGAIN3_SHIFT 8
--#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
--#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
--#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
--#define SSB_SPROM8_GPIOA_P1_SHIFT 8
--#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
--#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
--#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
--#define SSB_SPROM8_GPIOB_P3_SHIFT 8
--#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
-+#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
- #define SSB_SPROM8_RSSISMF2G 0x000F
- #define SSB_SPROM8_RSSISMC2G 0x00F0
- #define SSB_SPROM8_RSSISMC2G_SHIFT 4
-@@ -366,7 +412,7 @@
- #define SSB_SPROM8_RSSISAV2G_SHIFT 8
- #define SSB_SPROM8_BXA2G 0x1800
- #define SSB_SPROM8_BXA2G_SHIFT 11
--#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
-+#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
- #define SSB_SPROM8_RSSISMF5G 0x000F
- #define SSB_SPROM8_RSSISMC5G 0x00F0
- #define SSB_SPROM8_RSSISMC5G_SHIFT 4
-@@ -374,47 +420,47 @@
- #define SSB_SPROM8_RSSISAV5G_SHIFT 8
- #define SSB_SPROM8_BXA5G 0x1800
- #define SSB_SPROM8_BXA5G_SHIFT 11
--#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
-+#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
- #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
- #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
- #define SSB_SPROM8_TRI5G_SHIFT 8
--#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
-+#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
- #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
- #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
- #define SSB_SPROM8_TRI5GH_SHIFT 8
--#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
-+#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
- #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
- #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
- #define SSB_SPROM8_RXPO5G_SHIFT 8
--#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
-+#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
- #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
- #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
- #define SSB_SPROM8_ITSSI_BG_SHIFT 8
--#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
--#define SSB_SPROM8_PA0B1 0x10C4
--#define SSB_SPROM8_PA0B2 0x10C6
--#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
-+#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
-+#define SSB_SPROM8_PA0B1 0x00C4
-+#define SSB_SPROM8_PA0B2 0x00C6
-+#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
- #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
- #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
- #define SSB_SPROM8_ITSSI_A_SHIFT 8
--#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
-+#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
- #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
- #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
- #define SSB_SPROM8_MAXP_AL_SHIFT 8
--#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
--#define SSB_SPROM8_PA1B1 0x10CE
--#define SSB_SPROM8_PA1B2 0x10D0
--#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
--#define SSB_SPROM8_PA1LOB1 0x10D4
--#define SSB_SPROM8_PA1LOB2 0x10D6
--#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
--#define SSB_SPROM8_PA1HIB1 0x10DA
--#define SSB_SPROM8_PA1HIB2 0x10DC
--#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
--#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
--#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
--#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
--#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
-+#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
-+#define SSB_SPROM8_PA1B1 0x00CE
-+#define SSB_SPROM8_PA1B2 0x00D0
-+#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
-+#define SSB_SPROM8_PA1LOB1 0x00D4
-+#define SSB_SPROM8_PA1LOB2 0x00D6
-+#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
-+#define SSB_SPROM8_PA1HIB1 0x00DA
-+#define SSB_SPROM8_PA1HIB2 0x00DC
-+#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
-+#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
-+#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
-+#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
-+#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
-
- /* Values for SSB_SPROM1_BINF_CCODE */
- enum {