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| author | Jonas Gorski <jogo@openwrt.org> | 2015-04-10 10:29:04 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2015-04-10 10:29:04 +0000 |
| commit | 4e826d8303d305027bcfd726372a6cc2cf381d74 (patch) | |
| tree | 3f32e3d0e152d88b3739189bdcfb78c1e740a631 /target/linux/generic/files/drivers/net/phy/b53/b53_regs.h | |
| parent | 61885f95f07ee2a10d5165470e091bfec7fdc4ff (diff) | |
| download | upstream-4e826d8303d305027bcfd726372a6cc2cf381d74.tar.gz upstream-4e826d8303d305027bcfd726372a6cc2cf381d74.tar.bz2 upstream-4e826d8303d305027bcfd726372a6cc2cf381d74.zip | |
b53: clean up code to match kernel style better
* properly enclose macro arguments in paranthesis on use
* remove trailing white space
* convert C99 // comments
* add missing blank lines after declaration
* remove braces from single statement blocks
* split lines > 80 chars (except for one)
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45356
Diffstat (limited to 'target/linux/generic/files/drivers/net/phy/b53/b53_regs.h')
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/b53/b53_regs.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h index 7e50bb4e67..534170832a 100644 --- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h @@ -31,12 +31,12 @@ #define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */ /* PHY Registers */ -#define B53_PORT_MII_PAGE(i) (0x10 + i) /* Port i MII Registers */ +#define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */ #define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */ #define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */ /* MIB registers */ -#define B53_MIB_PAGE(i) (0x20 + i) +#define B53_MIB_PAGE(i) (0x20 + (i)) /* Quality of Service (QoS) Registers */ #define B53_QOS_PAGE 0x30 @@ -58,7 +58,7 @@ *************************************************************************/ /* Port Control Register (8 bit) */ -#define B53_PORT_CTRL(i) (0x00 + i) +#define B53_PORT_CTRL(i) (0x00 + (i)) #define PORT_CTRL_RX_DISABLE BIT(0) #define PORT_CTRL_TX_DISABLE BIT(1) #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ @@ -109,7 +109,7 @@ * Please note that not all ports are available on every hardware, e.g. BCM5301X * don't include overriding port 6, BCM63xx also have some limitations. */ -#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + i) +#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i)) #define GMII_PO_LINK BIT(0) #define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ #define GMII_PO_SPEED_S 2 |