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author | Chuanhong Guo <gch981213@gmail.com> | 2019-01-10 18:55:27 +0800 |
---|---|---|
committer | Petr Štetiar <ynezz@true.cz> | 2019-03-24 01:44:25 +0100 |
commit | cb7d96499cfef4b6816a2e617ff858a556d64b5a (patch) | |
tree | 29a54e93d0214ad33e5415e97e5180e27d34fa03 /target/linux/generic/files/drivers/net/phy/ar8216.h | |
parent | 7d504f68a651f328ae78beccd2f647d6f62fe39b (diff) | |
download | upstream-cb7d96499cfef4b6816a2e617ff858a556d64b5a.tar.gz upstream-cb7d96499cfef4b6816a2e617ff858a556d64b5a.tar.bz2 upstream-cb7d96499cfef4b6816a2e617ff858a556d64b5a.zip |
generic: ar8216: add support for ar8229
ar8229 is the builtin switch in ar934x and later chips. There is
also a standalone version available and their registers/functions
are the same.
This commit added support for the builtin ar8229. The only thing
missing for standalone ar8229 should be phy modes. Since I don't
have a router using that, this commit doesn't add support for
other phy modes.
Only add its support for mdio-device probing method because the
current PHY probing can't return 1G speed when it's a FE switch.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Diffstat (limited to 'target/linux/generic/files/drivers/net/phy/ar8216.h')
-rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8216.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h index 140c217c7c..4d2d8b5dbd 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.h +++ b/target/linux/generic/files/drivers/net/phy/ar8216.h @@ -52,6 +52,8 @@ #define AR8216_REG_FLOOD_MASK 0x002C #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6) #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6) +#define AR8229_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p)) +#define AR8229_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p)) #define AR8236_FM_CPU_BROADCAST_EN BIT(26) #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25) @@ -127,6 +129,12 @@ #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) #define AR8216_ATU_CTRL_AGE_TIME_S 0 #define AR8236_ATU_CTRL_RES BIT(20) +#define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18) + +#define AR8216_REG_TAG_PRIORITY 0x0070 + +#define AR8216_REG_SERVICE_TAG 0x0074 +#define AR8216_SERVICE_TAG_M BITS(0, 16) #define AR8216_REG_MIB_FUNC 0x0080 #define AR8216_MIB_TIMER BITS(0, 16) @@ -142,6 +150,7 @@ #define AR8216_REG_GLOBAL_CPUPORT 0x0078 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4) #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4 +#define AR8216_GLOBAL_CPUPORT_EN BIT(8) #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1)) #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000) @@ -237,6 +246,16 @@ #define AR8216_STATS_TXDEFER 0x98 #define AR8216_STATS_TXLATECOL 0x9c +#define AR8229_REG_OPER_MODE0 0x04 +#define AR8229_OPER_MODE0_MAC_GMII_EN BIT(6) +#define AR8229_OPER_MODE0_PHY_MII_EN BIT(10) + +#define AR8229_REG_OPER_MODE1 0x08 +#define AR8229_REG_OPER_MODE1_PHY4_MII_EN BIT(28) + +#define AR8229_REG_QM_CTRL 0x3c +#define AR8229_QM_CTRL_ARP_EN BIT(15) + #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008) #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12) #define AR8236_PORT_VLAN_DEFAULT_ID_S 16 |