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| author | John Crispin <john@openwrt.org> | 2014-04-22 08:08:02 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2014-04-22 08:08:02 +0000 |
| commit | 1b96cf30a91d98f3e84aac12b19d2a2bbbe5d402 (patch) | |
| tree | d4081993ad170ba2cc0e20e375e05973a35b3803 /target/linux/generic/files/drivers/net/phy/adm6996.h | |
| parent | cdc53e2ec90b017e5a21e3a8b36536c523367de9 (diff) | |
| download | upstream-1b96cf30a91d98f3e84aac12b19d2a2bbbe5d402.tar.gz upstream-1b96cf30a91d98f3e84aac12b19d2a2bbbe5d402.tar.bz2 upstream-1b96cf30a91d98f3e84aac12b19d2a2bbbe5d402.zip | |
linux/generic: add MIB counters and port status to ADM6996 switch
This patch adds port status information and MIB counters to the ADM6996
switch driver.
The driver supports also the older ADM6996L-variant, but I'm not able to
test this patch on that chip. According to the datasheet the same
registers exist there as well, so I think it should work, but any
feedback is appreciated.
Signed-off-by: Matti Laakso <malaakso at elisanet.fi>
SVN-Revision: 40542
Diffstat (limited to 'target/linux/generic/files/drivers/net/phy/adm6996.h')
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/adm6996.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/adm6996.h b/target/linux/generic/files/drivers/net/phy/adm6996.h index b30eceafdd..66c77a0968 100644 --- a/target/linux/generic/files/drivers/net/phy/adm6996.h +++ b/target/linux/generic/files/drivers/net/phy/adm6996.h @@ -50,6 +50,16 @@ enum admreg { ADM_COUNTER_BASE = 0xa0, ADM_SIG0 = ADM_COUNTER_BASE + 0, ADM_SIG1 = ADM_COUNTER_BASE + 1, + ADM_PS0 = ADM_COUNTER_BASE + 2, + ADM_PS1 = ADM_COUNTER_BASE + 3, + ADM_PS2 = ADM_COUNTER_BASE + 4, + ADM_CL0 = ADM_COUNTER_BASE + 8, /* RxPacket */ + ADM_CL6 = ADM_COUNTER_BASE + 0x1a, /* RxByte */ + ADM_CL12 = ADM_COUNTER_BASE + 0x2c, /* TxPacket */ + ADM_CL18 = ADM_COUNTER_BASE + 0x3e, /* TxByte */ + ADM_CL24 = ADM_COUNTER_BASE + 0x50, /* Coll */ + ADM_CL30 = ADM_COUNTER_BASE + 0x62, /* Err */ +#define ADM_OFFSET_PORT(n) ((n * 4) - (n / 4) * 2 - (n / 5) * 2) ADM_PHY_BASE = 0x200, #define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n)) }; @@ -159,6 +169,14 @@ static const u8 adm_portcfg[] = { ((ports & 0x04) << 2) | ((ports & 0x08) << 3) | \ ((ports & 0x10) << 3) | ((ports & 0x20) << 3)) +/* Port status register */ +enum { + ADM_PS_LS = (1 << 0), /* Link status */ + ADM_PS_SS = (1 << 1), /* Speed status */ + ADM_PS_DS = (1 << 2), /* Duplex status */ + ADM_PS_FCS = (1 << 3) /* Flow control status */ +}; + /* * Split the register address in phy id and register * it will get combined again by the mdio bus op |