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author | Matthew Hagan <mnhagan88@gmail.com> | 2021-11-06 13:50:27 +0000 |
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committer | Adrian Schmutzler <freifunk@adrianschmutzler.de> | 2021-11-07 00:05:26 +0100 |
commit | f2f42a54e8defb110a3e8b2aab833d67f27e2fe3 (patch) | |
tree | 81283babeb90d64938f6c8630fd6897920dd456c /target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch | |
parent | 07543d00e5107c41f6ed6369e1511cfb89efa468 (diff) | |
download | upstream-f2f42a54e8defb110a3e8b2aab833d67f27e2fe3.tar.gz upstream-f2f42a54e8defb110a3e8b2aab833d67f27e2fe3.tar.bz2 upstream-f2f42a54e8defb110a3e8b2aab833d67f27e2fe3.zip |
kernel: 5.10: compress 7xx patch numbering
The qca8k patch series brings the numbering to 799. This patch renames
7xx patches to create space for more backports to be added.
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
[rename 729->719]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Diffstat (limited to 'target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch')
-rw-r--r-- | target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch b/target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch new file mode 100644 index 0000000000..bd768ec27d --- /dev/null +++ b/target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch @@ -0,0 +1,30 @@ +From fdbf35df9c091db9c46e57e9938e3f7a4f603a7c Mon Sep 17 00:00:00 2001 +From: Ansuel Smith <ansuelsmth@gmail.com> +Date: Thu, 14 Oct 2021 00:39:07 +0200 +Subject: dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties + +Add names and descriptions of additional PORT0_PAD_CTRL properties. +qca,sgmii-(rx|tx)clk-falling-edge are for setting the respective clock +phase to failling edge. + +Co-developed-by: Matthew Hagan <mnhagan88@gmail.com> +Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> +Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +--- + Documentation/devicetree/bindings/net/dsa/qca8k.txt | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt ++++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt +@@ -37,6 +37,10 @@ A CPU port node has the following option + managed entity. See + Documentation/devicetree/bindings/net/fixed-link.txt + for details. ++- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge. ++ Mostly used in qca8327 with CPU port 0 set to ++ sgmii. ++- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. + + For QCA8K the 'fixed-link' sub-node supports only the following properties: + |