kernel: backport GD25Q256 support from 4.15

Backport below changes for GigaDevice GD25Q256 support from v4.15:

  e27072851bf7 mtd: spi-nor: add a quad_enable callback in struct flash_info
  65153846b18c mtd: spi-nor: add support for GD25Q256

This chip is used on newer Quad-E4G boards.

Before:

[    2.366493] m25p80 spi0.0: unrecognized JEDEC id bytes: c8, 40, 19
[    2.372853] m25p80: probe of spi0.0 failed with error -2

After:

[    2.371722] m25p80 spi0.0: gd25q256 (32768 Kbytes)
[    2.376694] 5 fixed-partitions partitions found on MTD device spi0.0
[    2.383043] Creating 5 MTD partitions on "spi0.0":
[    2.387824] 0x000000000000-0x000000030000 : "u-boot"
[    2.394138] 0x000000030000-0x000000031000 : "u-boot-env"
[    2.400608] 0x000000031000-0x000000040000 : "config"
[    2.406830] 0x000000040000-0x000000050000 : "factory"
[    2.413169] 0x000000050000-0x000002000000 : "firmware"

Signed-off-by: Kuan-Yi Li <kyli@abysm.org>

2 files changed, 82 insertions, 0 deletions

diff --git a/target/linux/generic/backport-4.14/403-v4.15-0001-mtd-spi-nor-add-a-quad_enable-callback-in-struct-fla.patch b/target/linux/generic/backport-4.14/403-v4.15-0001-mtd-spi-nor-add-a-quad_enable-callback-in-struct-fla.patch
new file mode 100644
index 0000000000..6cc7b44c1f
--- /dev/null
+++ b/target/linux/generic/backport-4.14/403-v4.15-0001-mtd-spi-nor-add-a-quad_enable-callback-in-struct-fla.patch
@@ -0,0 +1,47 @@
+From e27072851bf7d706c592fc528549b52023b17a09 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Mon, 28 Aug 2017 09:58:29 +0800
+Subject: [PATCH 1/2] mtd: spi-nor: add a quad_enable callback in struct
+ flash_info
+
+Some manufacturers may use different bit to set QE on different
+memories.
+
+The GD25Q256 from GigaDevice is an example, which uses S6(bit 6
+of the Status Register-1) to set QE, which is different with
+other supported memories from GigaDevice that use S9(bit 1 of
+the Status Register-2). This makes it is impossible to select
+the quad enable method by distinguishing the MFR. This patch
+introduce a quad_enable function which can be set per memory
+in the flash_info list table.
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -89,6 +89,8 @@ struct flash_info {
+ #define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */
+ #define SPI_NOR_SKIP_SFDP	BIT(13)	/* Skip parsing of SFDP tables */
+ #define USE_CLSR		BIT(14)	/* use CLSR command */
++
++	int	(*quad_enable)(struct spi_nor *nor);
+ };
+ 
+ #define JEDEC_MFR(info)	((info)->id[0])
+@@ -2433,6 +2435,15 @@ static int spi_nor_init_params(struct sp
+ 			params->quad_enable = spansion_quad_enable;
+ 			break;
+ 		}
++
++		/*
++		 * Some manufacturer like GigaDevice may use different
++		 * bit to set QE on different memories, so the MFR can't
++		 * indicate the quad_enable method for this case, we need
++		 * set it in flash info list.
++		 */
++		if (info->quad_enable)
++			params->quad_enable = info->quad_enable;
+ 	}
+ 
+ 	/* Override the parameters with data read from SFDP tables. */
diff --git a/target/linux/generic/backport-4.14/403-v4.15-0002-mtd-spi-nor-add-support-for-GD25Q256.patch b/target/linux/generic/backport-4.14/403-v4.15-0002-mtd-spi-nor-add-support-for-GD25Q256.patch
new file mode 100644
index 0000000000..c19a82179b
--- /dev/null
+++ b/target/linux/generic/backport-4.14/403-v4.15-0002-mtd-spi-nor-add-support-for-GD25Q256.patch
@@ -0,0 +1,35 @@
+From 65153846b18c486ce3c90477c467d53915114e3f Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Mon, 28 Aug 2017 10:00:46 +0800
+Subject: [PATCH 2/2] mtd: spi-nor: add support for GD25Q256
+
+Add support for GD25Q256, a 32MiB SPI Nor flash
+from GigaDevice.
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
+
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -872,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_
+ 	return ret;
+ }
+ 
++static int macronix_quad_enable(struct spi_nor *nor);
++
+ /* Used when the "_ext_id" is two bytes at most */
+ #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)	\
+ 		.id = {							\
+@@ -999,6 +1001,12 @@ static const struct flash_info spi_nor_i
+ 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ 	},
++	{
++		"gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
++			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
++			SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
++			.quad_enable = macronix_quad_enable,
++	},
+ 
+ 	/* Intel/Numonyx -- xxxs33b */
+ 	{ "160s33b",  INFO(0x898911, 0, 64 * 1024,  32, 0) },