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| author | Felix Fietkau <nbd@openwrt.org> | 2007-10-13 02:21:24 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2007-10-13 02:21:24 +0000 |
| commit | ceb5350cd332fbd1dfab6a8fe578275152746361 (patch) | |
| tree | fb9935e74217e478077bab2215e26dbeb5e071e4 /target/linux/generic-2.6/files | |
| parent | e29b73435a5a7cafebaef27719d2516eaa787a7c (diff) | |
| download | upstream-ceb5350cd332fbd1dfab6a8fe578275152746361.tar.gz upstream-ceb5350cd332fbd1dfab6a8fe578275152746361.tar.bz2 upstream-ceb5350cd332fbd1dfab6a8fe578275152746361.zip | |
back out change to generic-2.6/files/ and update 310-ssb_pcicore_fixes.patch for 2.6.23
SVN-Revision: 9281
Diffstat (limited to 'target/linux/generic-2.6/files')
| -rw-r--r-- | target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c b/target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c index 4a5f48c901..a59dff083e 100644 --- a/target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c +++ b/target/linux/generic-2.6/files/drivers/ssb/driver_pcicore.c @@ -93,13 +93,10 @@ static void __init ssb_fixup_pcibridge(struct pci_dev *dev) /* Enable PCI bridge BAR1 prefetch and burst */ pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3); - - /* Make sure our latency is high enough to handle the devices behind us */ - pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8); } DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge); -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return ssb_mips_irq(extpci_core->dev) + 2; } @@ -113,7 +110,7 @@ static u32 get_cfgspace_addr(struct ssb_pcicore *pc, if (unlikely(pc->cardbusmode && dev > 1)) goto out; - if (bus == 0) {//FIXME busnumber ok? + if (bus == 0) { /* Type 0 transaction */ if (unlikely(dev >= SSB_PCI_SLOT_MAX)) goto out; @@ -227,7 +224,7 @@ static int ssb_extpci_write_config(struct ssb_pcicore *pc, val = *((const u32 *)buf); break; } - writel(val, mmio); + writel(*((const u32 *)buf), mmio); err = 0; unmap: @@ -310,8 +307,6 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) udelay(150); val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ pcicore_write32(pc, SSB_PCICORE_CTL, val); - val = SSB_PCICORE_ARBCTL_INTERN; - pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); udelay(1); //TODO cardbus mode @@ -341,7 +336,6 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) * The following needs change, if we want to port hostmode * to non-MIPS platform. */ set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000)); - mdelay(300); register_pci_controller(&ssb_pcicore_controller); } |