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| author | John Crispin <john@openwrt.org> | 2015-07-14 07:43:10 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-07-14 07:43:10 +0000 |
| commit | d5d3b5e49cf7f7ea8c46605236cbe06eaa850d42 (patch) | |
| tree | f9d68e440f707d5ee0cd3015f8bf542650735ee1 /target/linux/gemini/patches-4.1/060-cache-fa.diff | |
| parent | 023b0e0b38e9a6a9f30d04576ad665ac053b3661 (diff) | |
| download | upstream-d5d3b5e49cf7f7ea8c46605236cbe06eaa850d42.tar.gz upstream-d5d3b5e49cf7f7ea8c46605236cbe06eaa850d42.tar.bz2 upstream-d5d3b5e49cf7f7ea8c46605236cbe06eaa850d42.zip | |
gemini: add 4.1 support
Signed-off-by: Roman Yeryomin <roman@advem.lv>
SVN-Revision: 46353
Diffstat (limited to 'target/linux/gemini/patches-4.1/060-cache-fa.diff')
| -rw-r--r-- | target/linux/gemini/patches-4.1/060-cache-fa.diff | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/target/linux/gemini/patches-4.1/060-cache-fa.diff b/target/linux/gemini/patches-4.1/060-cache-fa.diff new file mode 100644 index 0000000000..fc74c0af88 --- /dev/null +++ b/target/linux/gemini/patches-4.1/060-cache-fa.diff @@ -0,0 +1,41 @@ +--- a/arch/arm/mm/cache-fa.S ++++ b/arch/arm/mm/cache-fa.S +@@ -24,7 +24,8 @@ + /* + * The size of one data cache line. + */ +-#define CACHE_DLINESIZE 16 ++#define CACHE_DLINESIZE 16 ++#define CACHE_DLINESHIFT 4 + + /* + * The total size of the data cache. +@@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area) + * - start - virtual start address + * - end - virtual end address + */ ++__flush_whole_dcache: ++ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer ++ mov pc, lr ++ + fa_dma_inv_range: ++ sub r3, r1, r0 @ calculate total size ++ cmp r3, #CACHE_DLIMIT @ total size >= limit? ++ bhs __flush_whole_dcache @ flush whole D cache ++ + tst r0, #CACHE_DLINESIZE - 1 + bic r0, r0, #CACHE_DLINESIZE - 1 + mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry +@@ -193,6 +204,10 @@ fa_dma_inv_range: + * - end - virtual end address + */ + fa_dma_clean_range: ++ sub r3, r1, r0 @ calculate total size ++ cmp r3, #CACHE_DLIMIT @ total size >= limit? ++ bhs __flush_whole_dcache @ flush whole D cache ++ + bic r0, r0, #CACHE_DLINESIZE - 1 + 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHE_DLINESIZE |