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| author | Felix Fietkau <nbd@openwrt.org> | 2016-01-18 22:38:03 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2016-01-18 22:38:03 +0000 |
| commit | 8ecfa0e773f3aec21ab793e4f5588a2c4347ebb9 (patch) | |
| tree | dffa5dd7d3c237096c68edaaa52b6ed0da17d3c9 /target/linux/cns3xxx/patches-3.18/090-timers.patch | |
| parent | f366dc25d3c63e0faea2f76f55aa8d2141cf9778 (diff) | |
| download | upstream-8ecfa0e773f3aec21ab793e4f5588a2c4347ebb9.tar.gz upstream-8ecfa0e773f3aec21ab793e4f5588a2c4347ebb9.tar.bz2 upstream-8ecfa0e773f3aec21ab793e4f5588a2c4347ebb9.zip | |
cns3xxx: fix adding twd local timers
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 48331
Diffstat (limited to 'target/linux/cns3xxx/patches-3.18/090-timers.patch')
| -rw-r--r-- | target/linux/cns3xxx/patches-3.18/090-timers.patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/cns3xxx/patches-3.18/090-timers.patch b/target/linux/cns3xxx/patches-3.18/090-timers.patch index a884021384..0bf686d22f 100644 --- a/target/linux/cns3xxx/patches-3.18/090-timers.patch +++ b/target/linux/cns3xxx/patches-3.18/090-timers.patch @@ -24,8 +24,8 @@ .cpumask = cpu_all_mask, }; -@@ -215,6 +216,35 @@ static void __init cns3xxx_init_twd(void - #endif +@@ -213,6 +214,35 @@ static void __init cns3xxx_init_twd(void + twd_local_timer_register(&cns3xx_twd_local_timer); } +static cycle_t cns3xxx_get_cycles(struct clocksource *cs) @@ -60,7 +60,7 @@ /* * Set up the clock source and clock events devices */ -@@ -232,13 +262,12 @@ static void __init __cns3xxx_timer_init( +@@ -230,13 +260,12 @@ static void __init __cns3xxx_timer_init( /* stop free running timer3 */ writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); @@ -77,7 +77,7 @@ /* mask irq, non-mask timer1 overflow */ irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); irq_mask &= ~(1 << 2); -@@ -250,23 +279,9 @@ static void __init __cns3xxx_timer_init( +@@ -248,23 +277,9 @@ static void __init __cns3xxx_timer_init( val |= (1 << 9); writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |