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authorFelix Fietkau <nbd@openwrt.org>2014-07-31 23:40:49 +0000
committerFelix Fietkau <nbd@openwrt.org>2014-07-31 23:40:49 +0000
commit3c7cd63b7208b559e1ffa37368e3917338c9f7cb (patch)
tree7e48408a207d4b00730938769a648c61334f4691 /target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch
parent6944689e96e00427aeb5bd67e4ecbcb85222705c (diff)
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cns3xxx: update to linux 3.10
Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 41917
Diffstat (limited to 'target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch')
-rw-r--r--target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch11
1 files changed, 11 insertions, 0 deletions
diff --git a/target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch b/target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch
new file mode 100644
index 0000000000..3734daf4c6
--- /dev/null
+++ b/target/linux/cns3xxx/patches-3.10/030-pcie_clock.patch
@@ -0,0 +1,11 @@
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -370,8 +370,6 @@ static int __init cns3xxx_pcie_init(void
+ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+ iotable_init(cns3xxx_pcie[i].cfg_bases,
+ ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+ cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+ pci_common_init(&cns3xxx_pcie[i].hw_pci);