cns3xxx: update to linux 3.10

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 41917

13 files changed, 337 insertions, 338 deletions

diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
index c02a382a9b..b1155ef570 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
@@ -20,77 +20,68 @@
  * R10 - DMA Direction
  * R11 - DMA type
  * R12 - fiq_buffer Address
- * R13 - DMA type Address
 */
 
 	.global	cns3xxx_fiq_end
 ENTRY(cns3xxx_fiq_start)
-	mov r8, #0
-	str r8, [r13]
+	str	r8, [r13]
 
-	ldr r9, [r12]
-	ldr r8, [r9]
-	add r8, r8, #1
-	str r8, [r9]
-
-	ldmib r12, {r8, r9, r10}
-	and r11, r10, #0x3000000
-	and r10, r10, #0xff
-
-	teq r11, #0x1000000
-	beq cns3xxx_dma_map_area
-	teq r11, #0x2000000
-	beq cns3xxx_dma_unmap_area
-	b cns3xxx_dma_flush_range
-
-cns3xxx_fiq_exit:
-	mov r8, #0
-	str r8, [r12, #12]
-	mcr p15, 0, r8, c7, c10, 4    @ drain write buffer
-	subs pc, lr, #4
-
-cns3xxx_dma_map_area:
-	add r9, r9, r8
-	teq r10, #DMA_FROM_DEVICE
-	beq cns3xxx_dma_inv_range
-	b cns3xxx_dma_clean_range
-
-cns3xxx_dma_unmap_area:
-	add r9, r9, r8
-	teq r10, #DMA_TO_DEVICE
-	bne cns3xxx_dma_inv_range
-	b cns3xxx_fiq_exit
+	ldmia	r12, {r8, r9, r10}
+	and	r11, r10, #0x3000000
+	and	r10, r10, #0xff
 
+	teq	r11, #0x1000000
+	beq	cns3xxx_dma_map_area
+	teq	r11, #0x2000000
+	beq	cns3xxx_dma_unmap_area
+	/* fall through */
 cns3xxx_dma_flush_range:
-	bic r8, r8, #D_CACHE_LINE_SIZE - 1
+	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
 1:
-	mcr p15, 0, r8, c7, c14, 1   @ clean & invalidate D line
-	add r8, r8, #D_CACHE_LINE_SIZE
-	cmp r8, r9
-	blo 1b
-	b cns3xxx_fiq_exit
+	mcr	p15, 0, r8, c7, c14, 1		@ clean & invalidate D line
+	add	r8, r8, #D_CACHE_LINE_SIZE
+	cmp	r8, r9
+	blo	1b
+	/* fall through */
+cns3xxx_fiq_exit:
+	mov	r8, #0
+	str	r8, [r12, #8]
+	mcr	p15, 0, r8, c7, c10, 4		@ drain write buffer
+	subs	pc, lr, #4
 
+cns3xxx_dma_map_area:
+	add	r9, r9, r8
+	teq	r10, #DMA_FROM_DEVICE
+	beq	cns3xxx_dma_inv_range
+	teq	r10, #DMA_TO_DEVICE
+	bne	cns3xxx_dma_flush_range
+	/* fall through */
 cns3xxx_dma_clean_range:
-	bic r8, r8, #D_CACHE_LINE_SIZE - 1
+	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
 1:
-	mcr p15, 0, r8, c7, c10, 1    @ clean D line
-	add r8, r8, #D_CACHE_LINE_SIZE
-	cmp r8, r9
-	blo 1b
-	b cns3xxx_fiq_exit
+	mcr	p15, 0, r8, c7, c10, 1		@ clean D line
+	add	r8, r8, #D_CACHE_LINE_SIZE
+	cmp	r8, r9
+	blo	1b
+	b	cns3xxx_fiq_exit
 
+cns3xxx_dma_unmap_area:
+	add	r9, r9, r8
+	teq	r10, #DMA_TO_DEVICE
+	beq	cns3xxx_fiq_exit
+	/* fall through */
 cns3xxx_dma_inv_range:
-	tst r8, #D_CACHE_LINE_SIZE - 1
-	bic r8, r8, #D_CACHE_LINE_SIZE - 1
-	mcrne p15, 0, r8, c7, c10, 1    @ clean D line
-	tst r9, #D_CACHE_LINE_SIZE - 1
-	bic r9, r9, #D_CACHE_LINE_SIZE - 1
-	mcrne p15, 0, r9, c7, c14, 1    @ clean & invalidate D line
+	tst	r8, #D_CACHE_LINE_SIZE - 1
+	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
+	mcrne	p15, 0, r8, c7, c10, 1		@ clean D line
+	tst	r9, #D_CACHE_LINE_SIZE - 1
+	bic	r9, r9, #D_CACHE_LINE_SIZE - 1
+	mcrne	p15, 0, r9, c7, c14, 1		@ clean & invalidate D line
 1:
-	mcr p15, 0, r8, c7, c6, 1   @ invalidate D line
-	add r8, r8, #D_CACHE_LINE_SIZE
-	cmp r8, r9
-	blo 1b
-	b cns3xxx_fiq_exit
+	mcr	p15, 0, r8, c7, c6, 1		@ invalidate D line
+	add	r8, r8, #D_CACHE_LINE_SIZE
+	cmp	r8, r9
+	blo	1b
+	b	cns3xxx_fiq_exit
 
 cns3xxx_fiq_end:
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
index 4f5d50054f..35434f8514 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
@@ -11,6 +11,7 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
@@ -141,8 +142,6 @@ static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
 	struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq);
 	struct irq_chip *chip = irq_get_chip(irq);
-	struct irq_chip_generic *gc = irq_desc_get_chip_data(desc);
-	struct irq_chip_type *ct = gc->chip_types;
 	u16 i;
 	u32 reg;
 
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
index 4903749c93..9021f3d65f 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c
@@ -39,19 +39,19 @@
 #include <linux/pps-gpio.h>
 #include <linux/usb/ehci_pdriver.h>
 #include <linux/usb/ohci_pdriver.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/platform_data/cns3xxx.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/cns3xxx.h>
-#include <mach/irqs.h>
-#include <mach/platform.h>
-#include <mach/pm.h>
 #include <mach/gpio.h>
-#include <asm/hardware/gic.h>
 #include "core.h"
 #include "devices.h"
+#include "cns3xxx.h"
+#include "pm.h"
 
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 
@@ -192,8 +192,16 @@ static struct spi_board_info __initdata laguna_spi_devices[] = {
 	},
 };
 
+static struct resource laguna_spi_resource = {
+	.start    = CNS3XXX_SSP_BASE + 0x40,
+	.end      = CNS3XXX_SSP_BASE + 0x6f,
+	.flags    = IORESOURCE_MEM,
+};
+
 static struct platform_device laguna_spi_controller = {
 	.name = "cns3xxx_spi",
+	.resource = &laguna_spi_resource,
+	.num_resources = 1,
 };
 
 /*
@@ -314,9 +322,30 @@ static struct cns3xxx_plat_info laguna_net_data = {
 	},
 };
 
+static struct resource laguna_net_resource[] = {
+	{
+		.name = "eth0_mem",
+		.start = CNS3XXX_SWITCH_BASE,
+		.end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
+		.flags = IORESOURCE_MEM
+	}, {
+		.name = "eth_rx",
+		.start = IRQ_CNS3XXX_SW_R0RXC,
+		.end = IRQ_CNS3XXX_SW_R0RXC,
+		.flags = IORESOURCE_IRQ
+	}, {
+		.name = "eth_stat",
+		.start = IRQ_CNS3XXX_SW_STATUS,
+		.end = IRQ_CNS3XXX_SW_STATUS,
+		.flags = IORESOURCE_IRQ
+	}
+};
+
 static struct platform_device laguna_net_device = {
 	.name = "cns3xxx_eth",
 	.id = 0,
+	.resource = laguna_net_resource,
+	.num_resources = ARRAY_SIZE(laguna_net_resource),
 	.dev.platform_data = &laguna_net_data,
 };
 
@@ -361,29 +390,26 @@ static struct resource laguna_uart_resources[] = {
 
 static struct plat_serial8250_port laguna_uart_data[] = {
 	{
-		.membase        = (char*) (CNS3XXX_UART0_BASE_VIRT),
 		.mapbase        = (CNS3XXX_UART0_BASE),
 		.irq            = IRQ_CNS3XXX_UART0,
 		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
 		.regshift       = 2,
 		.uartclk        = 24000000,
 		.type           = PORT_16550A,
 	},{
-		.membase        = (char*) (CNS3XXX_UART1_BASE_VIRT),
 		.mapbase        = (CNS3XXX_UART1_BASE),
 		.irq            = IRQ_CNS3XXX_UART1,
 		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
 		.regshift       = 2,
 		.uartclk        = 24000000,
 		.type           = PORT_16550A,
 	},{
-		.membase        = (char*) (CNS3XXX_UART2_BASE_VIRT),
 		.mapbase        = (CNS3XXX_UART2_BASE),
 		.irq            = IRQ_CNS3XXX_UART2,
 		.iotype         = UPIO_MEM,
-		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
+		.flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
 		.regshift       = 2,
 		.uartclk        = 24000000,
 		.type           = PORT_16550A,
@@ -526,7 +552,7 @@ static struct platform_device cns3xxx_usb_otg_device = {
 static struct resource laguna_i2c_resource[] = {
 	{
 		.start    = CNS3XXX_SSP_BASE + 0x20,
-		.end      = 0x7100003f,
+		.end      = CNS3XXX_SSP_BASE + 0x3f,
 		.flags    = IORESOURCE_MEM,
 	},{
 		.start    = IRQ_CNS3XXX_I2C,
@@ -771,10 +797,37 @@ static struct gpio laguna_gpio_gw2380[] = {
  */
 static void __init laguna_init(void)
 {
+	struct clk *clk;
+	u32 __iomem *reg;
+
+	clk = clk_register_fixed_rate(NULL, "cpu", NULL,
+				      CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+				      cns3xxx_cpu_clock() * (1000000 / 8));
+	clk_register_clkdev(clk, "cpu", NULL);
+
 	platform_device_register(&laguna_watchdog);
 
 	platform_device_register(&laguna_i2c_controller);
 
+	/* Set ext_int 0-3 drive strength to 21 mA */
+	reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
+	*reg |= 0x300;
+
+	/* Enable SCL/SDA for I2C */
+	reg = MISC_GPIOB_PIN_ENABLE_REG;
+	*reg |= BIT(12) | BIT(13);
+
+	/* Enable MMC/SD pins */
+	reg = MISC_GPIOA_PIN_ENABLE_REG;
+	*reg |= 0xf80;
+
+	cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+	cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+	cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+
+	cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
+	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
+
 	i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
 
 	pm_power_off = cns3xxx_power_off;
@@ -786,22 +839,12 @@ static struct map_desc laguna_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(CNS3XXX_UART0_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
-	},{
-		.virtual	= CNS3XXX_UART1_BASE_VIRT,
-		.pfn		= __phys_to_pfn(CNS3XXX_UART1_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE,
-	},{
-		.virtual	= CNS3XXX_UART2_BASE_VIRT,
-		.pfn		= __phys_to_pfn(CNS3XXX_UART2_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE,
 	},
 };
 
 static void __init laguna_map_io(void)
 {
-	cns3xxx_common_init();
+	cns3xxx_map_io();
 	cns3xxx_pcie_iotable_init();
 	iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
 	laguna_early_serial_setup();
@@ -1022,11 +1065,11 @@ static int __init laguna_model_setup(void)
 late_initcall(laguna_model_setup);
 
 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
+	.smp		= smp_ops(cns3xxx_smp_ops),
 	.atag_offset	= 0x100,
 	.map_io		= laguna_map_io,
 	.init_irq	= cns3xxx_init_irq,
-	.timer		= &cns3xxx_timer,
-	.handle_irq	= gic_handle_irq,
+	.init_time	= cns3xxx_timer_init,
 	.init_machine	= laguna_init,
 	.restart	= cns3xxx_restart,
 MACHINE_END
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
index 77ac97a20c..53598857fd 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c
@@ -21,46 +21,61 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <asm/unified.h>
 #include <asm/fiq.h>
 #include <mach/smp.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
 
 static struct fiq_handler fh = {
 	.name = "cns3xxx-fiq"
 };
 
-static unsigned int fiq_buffer[8];
+struct fiq_req {
+	union {
+		struct {
+			const void *addr;
+			size_t size;
+		} map;
+		struct {
+			const void *addr;
+			size_t size;
+		} unmap;
+		struct {
+			const void *start;
+			const void *end;
+		} flush;
+	};
+	volatile uint flags;
+	void __iomem *reg;
+} ____cacheline_aligned;
+
+extern unsigned int fiq_number[2];
+
+DEFINE_PER_CPU(struct fiq_req, fiq_data);
 
 #define FIQ_ENABLED         0x80000000
-#define FIQ_GENERATE				0x00010000
+#define FIQ_GENERATE        0x00010000
 #define CNS3XXX_MAP_AREA    0x01000000
 #define CNS3XXX_UNMAP_AREA  0x02000000
 #define CNS3XXX_FLUSH_RANGE 0x03000000
 
 extern void cns3xxx_secondary_startup(void);
 extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
-extern unsigned int fiq_number[2];
-extern struct cpu_cache_fns cpu_cache;
-struct cpu_cache_fns cpu_cache_save;
 
 #define SCU_CPU_STATUS 0x08
 static void __iomem *scu_base;
 
-static void __init cns3xxx_set_fiq_regs(void)
+static inline void __cpuinit cns3xxx_set_fiq_regs(unsigned int cpu)
 {
 	struct pt_regs FIQ_regs;
-	unsigned int cpu = smp_processor_id();
-
-	if (cpu) {
-		FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[4];
-		FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(0);
-	} else {
-		FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[0];
-		FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(1);
-	}
+	struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
+
+	FIQ_regs.ARM_r8 = 0;
+	FIQ_regs.ARM_ip = (unsigned int)fiq_req;
+	FIQ_regs.ARM_sp = (int) MISC_FIQ_CPU(!cpu);
+	fiq_req->reg = MISC_FIQ_CPU(!cpu);
+
 	set_fiq_regs(&FIQ_regs);
 }
 
@@ -74,16 +89,10 @@ static void __init cns3xxx_init_fiq(void)
 	fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
 
 	ret = claim_fiq(&fh);
-
-	if (ret) {
+	if (ret)
 		return;
-	}
 
 	set_fiq_handler(fiqhandler_start, fiqhandler_length);
-	fiq_buffer[0] = (unsigned int)&fiq_number[0];
-	fiq_buffer[3] = 0;
-	fiq_buffer[4] = (unsigned int)&fiq_number[1];
-	fiq_buffer[7] = 0;
 }
 
 
@@ -105,16 +114,9 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit cns3xxx_secondary_init(unsigned int cpu)
 {
 	/*
-	 * if any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * Setup Secondary Core FIQ regs
 	 */
-	cns3xxx_set_fiq_regs();
+	cns3xxx_set_fiq_regs(1);
 
 	/*
 	 * let the primary processor know we're out of the
@@ -123,14 +125,6 @@ static void __cpuinit cns3xxx_secondary_init(unsigned int cpu)
 	write_pen_release(-1);
 
 	/*
-	 * Fixup DMA Operations
-	 *
-	 */
-	cpu_cache.dma_map_area = (void *)smp_dma_map_area;
-	cpu_cache.dma_unmap_area = (void *)smp_dma_unmap_area;
-	cpu_cache.dma_flush_range = (void *)smp_dma_flush_range;
-
-	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
@@ -162,7 +156,7 @@ static int __cpuinit cns3xxx_boot_secondary(unsigned int cpu, struct task_struct
 	 * the boot monitor to read the system wide flags register,
 	 * and branch to the address found there.
 	 */
-	gic_raise_softirq(cpumask_of(cpu), 1);
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));;
 
 	timeout = jiffies + (1 * HZ);
 	while (time_before(jiffies, timeout)) {
@@ -204,8 +198,6 @@ static void __init cns3xxx_smp_init_cpus(void)
 			break;
 	}
 	ncores = i;
-
-	set_smp_cross_call(gic_raise_softirq);
 }
 
 static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
@@ -238,111 +230,105 @@ static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus)
 	 * Setup FIQ's for main cpu
 	 */
 	cns3xxx_init_fiq();
-	cns3xxx_set_fiq_regs();
-	memcpy((void *)&cpu_cache_save, (void *)&cpu_cache, sizeof(struct cpu_cache_fns));
+	cns3xxx_set_fiq_regs(0);
 }
 
+extern void v6_dma_map_area(const void *, size_t, int);
+extern void v6_dma_unmap_area(const void *, size_t, int);
+extern void v6_dma_flush_range(const void *, const void *);
+extern void v6_flush_kern_dcache_area(void *, size_t);
 
-static inline unsigned long cns3xxx_cpu_id(void)
+void fiq_dma_map_area(const void *addr, size_t size, int dir)
 {
-	unsigned long cpu;
-
-	asm volatile(
-		" mrc p15, 0, %0, c0, c0, 5  @ cns3xxx_cpu_id\n"
-		: "=r" (cpu) : : "memory", "cc");
-	return (cpu & 0xf);
-}
-
-void smp_dma_map_area(const void *addr, size_t size, int dir)
-{
-	unsigned int cpu;
 	unsigned long flags;
+	struct fiq_req *req;
+
 	raw_local_irq_save(flags);
-	cpu = cns3xxx_cpu_id();
-	if (cpu) {
-		fiq_buffer[1] = (unsigned int)addr;
-		fiq_buffer[2] = size;
-		fiq_buffer[3] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-
-		cpu_cache_save.dma_map_area(addr, size, dir);
-		while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-	} else {
-
-		fiq_buffer[5] = (unsigned int)addr;
-		fiq_buffer[6] = size;
-		fiq_buffer[7] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-
-		cpu_cache_save.dma_map_area(addr, size, dir);
-		while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+	/* currently, not possible to take cpu0 down, so only check cpu1 */
+	if (!cpu_online(1)) {
+		raw_local_irq_restore(flags);
+		v6_dma_map_area(addr, size, dir);
+		return;
 	}
+
+	req = this_cpu_ptr(&fiq_data);
+	req->map.addr = addr;
+	req->map.size = size;
+	req->flags = dir | CNS3XXX_MAP_AREA;
+	smp_mb();
+
+	writel_relaxed(FIQ_GENERATE, req->reg);
+
+	v6_dma_map_area(addr, size, dir);
+	while (req->flags)
+		barrier();
+
 	raw_local_irq_restore(flags);
 }
 
-void smp_dma_unmap_area(const void *addr, size_t size, int dir)
+void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
 {
-	unsigned int cpu;
 	unsigned long flags;
+	struct fiq_req *req;
 
 	raw_local_irq_save(flags);
-	cpu = cns3xxx_cpu_id();
-	if (cpu) {
-
-		fiq_buffer[1] = (unsigned int)addr;
-		fiq_buffer[2] = size;
-		fiq_buffer[3] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-
-		cpu_cache_save.dma_unmap_area(addr, size, dir);
-		while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-	} else {
-
-		fiq_buffer[5] = (unsigned int)addr;
-		fiq_buffer[6] = size;
-		fiq_buffer[7] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-
-		cpu_cache_save.dma_unmap_area(addr, size, dir);
-		while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+	/* currently, not possible to take cpu0 down, so only check cpu1 */
+	if (!cpu_online(1)) {
+		raw_local_irq_restore(flags);
+		v6_dma_unmap_area(addr, size, dir);
+		return;
 	}
+
+	req = this_cpu_ptr(&fiq_data);
+	req->unmap.addr = addr;
+	req->unmap.size = size;
+	req->flags = dir | CNS3XXX_UNMAP_AREA;
+	smp_mb();
+
+	writel_relaxed(FIQ_GENERATE, req->reg);
+
+	v6_dma_unmap_area(addr, size, dir);
+	while (req->flags)
+		barrier();
+
 	raw_local_irq_restore(flags);
 }
 
-void smp_dma_flush_range(const void *start, const void *end)
+void fiq_dma_flush_range(const void *start, const void *end)
 {
-	unsigned int cpu;
 	unsigned long flags;
+	struct fiq_req *req;
+
 	raw_local_irq_save(flags);
-	cpu = cns3xxx_cpu_id();
-	if (cpu) {
-
-		fiq_buffer[1] = (unsigned int)start;
-		fiq_buffer[2] = (unsigned int)end;
-		fiq_buffer[3] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
-
-		cpu_cache_save.dma_flush_range(start, end);
-		while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
-	} else {
-
-		fiq_buffer[5] = (unsigned int)start;
-		fiq_buffer[6] = (unsigned int)end;
-		fiq_buffer[7] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
-		smp_mb();
-		__raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
-
-		cpu_cache_save.dma_flush_range(start, end);
-		while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
+	/* currently, not possible to take cpu0 down, so only check cpu1 */
+	if (!cpu_online(1)) {
+		raw_local_irq_restore(flags);
+		v6_dma_flush_range(start, end);
+		return;
 	}
+
+	req = this_cpu_ptr(&fiq_data);
+
+	req->flush.start = start;
+	req->flush.end = end;
+	req->flags = CNS3XXX_FLUSH_RANGE;
+	smp_mb();
+
+	writel_relaxed(FIQ_GENERATE, req->reg);
+
+	v6_dma_flush_range(start, end);
+
+	while (req->flags)
+		barrier();
+
 	raw_local_irq_restore(flags);
 }
 
+void fiq_flush_kern_dcache_area(void *addr, size_t size)
+{
+	fiq_dma_flush_range(addr, addr + size);
+}
+
 struct smp_operations cns3xxx_smp_ops __initdata = {
 	.smp_init_cpus      = cns3xxx_smp_init_cpus,
 	.smp_prepare_cpus   = cns3xxx_smp_prepare_cpus,
diff --git a/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c b/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c
index c3fd7c8972..7acff37d26 100644
--- a/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c
+++ b/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c
@@ -21,28 +21,23 @@
 #include <linux/delay.h>
 #include <linux/i2c.h>
 #include <linux/slab.h>
-#include <mach/pm.h>
-#include <mach/cns3xxx.h>
+#include <linux/clk.h>
 
 /*
  * We need the memory map
  */
 
-
-#define MISC_MEM_MAP_VALUE(reg_offset)	(*((uint32_t volatile *)(CNS3XXX_MISC_BASE_VIRT + reg_offset)))
-#define MISC_IOCDB_CTRL				MISC_MEM_MAP_VALUE(0x020)
-
-#define I2C_MEM_MAP_ADDR(x)         (CNS3XXX_SSP_BASE_VIRT + x)
+#define I2C_MEM_MAP_ADDR(x)         (i2c->base + x)
 #define I2C_MEM_MAP_VALUE(x)        (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x)))
 
-#define I2C_CONTROLLER_REG                    I2C_MEM_MAP_VALUE(0x20)
-#define I2C_TIME_OUT_REG                      I2C_MEM_MAP_VALUE(0x24)
-#define I2C_SLAVE_ADDRESS_REG                 I2C_MEM_MAP_VALUE(0x28)
-#define I2C_WRITE_DATA_REG                    I2C_MEM_MAP_VALUE(0x2C)
-#define I2C_READ_DATA_REG                     I2C_MEM_MAP_VALUE(0x30)
-#define I2C_INTERRUPT_STATUS_REG              I2C_MEM_MAP_VALUE(0x34)
-#define I2C_INTERRUPT_ENABLE_REG              I2C_MEM_MAP_VALUE(0x38)
-#define I2C_TWI_OUT_DLY_REG			         			I2C_MEM_MAP_VALUE(0x3C)
+#define I2C_CONTROLLER_REG                    I2C_MEM_MAP_VALUE(0x00)
+#define I2C_TIME_OUT_REG                      I2C_MEM_MAP_VALUE(0x04)
+#define I2C_SLAVE_ADDRESS_REG                 I2C_MEM_MAP_VALUE(0x08)
+#define I2C_WRITE_DATA_REG                    I2C_MEM_MAP_VALUE(0x0C)
+#define I2C_READ_DATA_REG                     I2C_MEM_MAP_VALUE(0x10)
+#define I2C_INTERRUPT_STATUS_REG              I2C_MEM_MAP_VALUE(0x14)
+#define I2C_INTERRUPT_ENABLE_REG              I2C_MEM_MAP_VALUE(0x18)
+#define I2C_TWI_OUT_DLY_REG			         			I2C_MEM_MAP_VALUE(0x1C)
 
 #define I2C_BUS_ERROR_FLAG     (0x1)
 #define I2C_ACTION_DONE_FLAG   (0x2)
@@ -203,24 +198,18 @@ static struct i2c_adapter cns3xxx_i2c_adapter = {
 
 static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c)
 {
-        cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
-        cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
-        cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
+	struct clk *clk;
+
+	clk = devm_clk_get(i2c->dev, "cpu");
+	if (WARN_ON(!clk))
+		return;
 
 	/* Disable the I2C */
 	I2C_CONTROLLER_REG = 0;	/* Disabled the I2C */
 
-	//enable SCL and SDA which share pin with GPIOB_PIN_EN(0x18)
-	//GPIOB[12]: SCL
-	//GPIOB[13]: SDA
-	(*(u32*)(CNS3XXX_MISC_BASE_VIRT+0x18)) |= ((1<<12)|(1<<13));
-
-	MISC_IOCDB_CTRL &= ~0x300;
-	MISC_IOCDB_CTRL |= 0x300; //21mA...
-
 	/* Check the Reg Dump when testing */
 	I2C_TIME_OUT_REG =
-	    ((((((cns3xxx_cpu_clock()*(1000000/8)) / (2 * CNS3xxx_I2C_CLK)) -
+	    (((((clk_get_rate(clk) / (2 * CNS3xxx_I2C_CLK)) -
 		1) & 0x3FF) << 8) | (1 << 7) | 0x7F);
 	I2C_TWI_OUT_DLY_REG |= 0x3;
 
@@ -358,20 +347,9 @@ static int cns3xxx_i2c_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#ifdef CONFIG_PM
-#warning "CONFIG_PM defined: suspend and resume not implemented"
-#define cns3xxx_i2c_suspend	NULL
-#define cns3xxx_i2c_resume	NULL
-#else
-#define cns3xxx_i2c_suspend	NULL
-#define cns3xxx_i2c_resume	NULL
-#endif
-
 static struct platform_driver cns3xxx_i2c_driver = {
 	.probe = cns3xxx_i2c_probe,
 	.remove = cns3xxx_i2c_remove,
-	.suspend = cns3xxx_i2c_suspend,
-	.resume = cns3xxx_i2c_resume,
 	.driver = {
 		.owner = THIS_MODULE,
 		.name = "cns3xxx-i2c",
diff --git a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c
index bbbbf5c091..b7e3758ba6 100644
--- a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c
+++ b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c
@@ -20,9 +20,8 @@
 #include <linux/kernel.h>
 #include <linux/phy.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/cns3xxx.h>
 #include <linux/skbuff.h>
-#include <mach/irqs.h>
-#include <mach/platform.h>
 
 #define DRV_NAME "cns3xxx_eth"
 
@@ -282,7 +281,6 @@ struct _rx_ring {
 };
 
 struct sw {
-	struct resource *mem_res;
 	struct switch_regs __iomem *regs;
 	struct napi_struct napi;
 	struct cns3xxx_plat_info *plat;
@@ -290,6 +288,8 @@ struct sw {
 	struct _rx_ring rx_ring;
 	struct sk_buff *frag_first;
 	struct sk_buff *frag_last;
+	int rx_irq;
+	int stat_irq;
 };
 
 struct port {
@@ -377,14 +377,14 @@ static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location,
 	return ret;
 }
 
-static int cns3xxx_mdio_register(void)
+static int cns3xxx_mdio_register(void __iomem *base)
 {
 	int err;
 
 	if (!(mdio_bus = mdiobus_alloc()))
 		return -ENOMEM;
 
-	mdio_regs = (struct switch_regs __iomem *)CNS3XXX_SWITCH_BASE_VIRT;
+	mdio_regs = base;
 
 	spin_lock_init(&mdio_lock);
 	mdio_bus->name = "CNS3xxx MII Bus";
@@ -441,7 +441,7 @@ static void eth_schedule_poll(struct sw *sw)
 	if (unlikely(!napi_schedule_prep(&sw->napi)))
 		return;
 
-	disable_irq_nosync(IRQ_CNS3XXX_SW_R0RXC);
+	disable_irq_nosync(sw->rx_irq);
 	__napi_schedule(&sw->napi);
 }
 
@@ -716,7 +716,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
 	rx_ring->cur_index = i;
 	if (!received) {
 		napi_complete(napi);
-		enable_irq(IRQ_CNS3XXX_SW_R0RXC);
+		enable_irq(sw->rx_irq);
 
 		/* if rx descriptors are full schedule another poll */
 		if (rx_ring->desc[(i-1) & (RX_DESCS-1)].cown)
@@ -1007,8 +1007,8 @@ static int eth_open(struct net_device *dev)
 	netif_start_queue(dev);
 
 	if (!ports_open) {
-		request_irq(IRQ_CNS3XXX_SW_R0RXC, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
-		request_irq(IRQ_CNS3XXX_SW_STATUS, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
+		request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev);
+		request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev);
 		napi_enable(&sw->napi);
 		netif_start_queue(napi_dev);
 
@@ -1052,10 +1052,10 @@ static int eth_close(struct net_device *dev)
 	phy_stop(port->phydev);
 
 	if (!ports_open) {
-		disable_irq(IRQ_CNS3XXX_SW_R0RXC);
-		free_irq(IRQ_CNS3XXX_SW_R0RXC, napi_dev);
-		disable_irq(IRQ_CNS3XXX_SW_STATUS);
-		free_irq(IRQ_CNS3XXX_SW_STATUS, napi_dev);
+		disable_irq(sw->rx_irq);
+		free_irq(sw->rx_irq, napi_dev);
+		disable_irq(sw->stat_irq);
+		free_irq(sw->stat_irq, napi_dev);
 		napi_disable(&sw->napi);
 		netif_stop_queue(napi_dev);
 		temp = __raw_readl(&sw->regs->mac_cfg[2]);
@@ -1172,26 +1172,36 @@ static int eth_init_one(struct platform_device *pdev)
 	struct sw *sw;
 	struct net_device *dev;
 	struct cns3xxx_plat_info *plat = pdev->dev.platform_data;
-	u32 regs_phys;
 	char phy_id[MII_BUS_ID_SIZE + 3];
 	int err;
 	u32 temp;
+	struct resource *res;
+	void __iomem *regs;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	err = cns3xxx_mdio_register(regs);
+	if (err)
+		return err;
+
+	if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) {
+		err = -ENOMEM;
+		goto err_remove_mdio;
+	}
 
-	if (!(napi_dev = alloc_etherdev(sizeof(struct sw))))
-		return -ENOMEM;
 	strcpy(napi_dev->name, "switch%d");
 	napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST;
 
 	SET_NETDEV_DEV(napi_dev, &pdev->dev);
 	sw = netdev_priv(napi_dev);
 	memset(sw, 0, sizeof(struct sw));
-	sw->regs = (struct switch_regs __iomem *)CNS3XXX_SWITCH_BASE_VIRT;
-	regs_phys = CNS3XXX_SWITCH_BASE;
-	sw->mem_res = request_mem_region(regs_phys, REGS_SIZE, napi_dev->name);
-	if (!sw->mem_res) {
-		err = -EBUSY;
-		goto err_free;
-	}
+	sw->regs = regs;
+
+	sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx");
+	sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat");
 
 	temp = __raw_readl(&sw->regs->phy_auto_addr);
 	temp |= (3 << 30); /* maximum frame length: 9600 bytes */
@@ -1252,7 +1262,7 @@ static int eth_init_one(struct platform_device *pdev)
 		memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN);
 
 		snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]);
-		port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link, 0,
+		port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link,
 			PHY_INTERFACE_MODE_RGMII);
 		if ((err = IS_ERR(port->phydev))) {
 			switch_port_tab[port->id] = 0;
@@ -1290,6 +1300,8 @@ free_ports:
 	}
 err_free:
 	free_netdev(napi_dev);
+err_remove_mdio:
+	cns3xxx_mdio_remove();
 	return err;
 }
 
@@ -1311,8 +1323,9 @@ static int eth_remove_one(struct platform_device *pdev)
 		}
 	}
 
-	release_resource(sw->mem_res);
 	free_netdev(napi_dev);
+	cns3xxx_mdio_remove();
+
 	return 0;
 }
 
@@ -1324,16 +1337,12 @@ static struct platform_driver cns3xxx_eth_driver = {
 
 static int __init eth_init_module(void)
 {
-	int err;
-	if ((err = cns3xxx_mdio_register()))
-		return err;
 	return platform_driver_register(&cns3xxx_eth_driver);
 }
 
 static void __exit eth_cleanup_module(void)
 {
 	platform_driver_unregister(&cns3xxx_eth_driver);
-	cns3xxx_mdio_remove();
 }
 
 module_init(eth_init_module);
diff --git a/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c b/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c
index 2642639867..63019862ee 100644
--- a/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c
+++ b/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c
@@ -45,30 +45,28 @@
 #include <asm/memory.h>
 #include <asm/dma.h>
 #include <asm/delay.h>
-#include <mach/cns3xxx.h>
 #include <linux/module.h>
-#include <mach/pm.h>
 
 /*
  * define access macros
  */
-#define SPI_MEM_MAP_VALUE(reg_offset)		(*((u32 volatile *)(CNS3XXX_SSP_BASE_VIRT + reg_offset)))
-
-#define SPI_CONFIGURATION_REG			SPI_MEM_MAP_VALUE(0x40)
-#define SPI_SERVICE_STATUS_REG			SPI_MEM_MAP_VALUE(0x44)
-#define SPI_BIT_RATE_CONTROL_REG		SPI_MEM_MAP_VALUE(0x48)
-#define SPI_TRANSMIT_CONTROL_REG		SPI_MEM_MAP_VALUE(0x4C)
-#define SPI_TRANSMIT_BUFFER_REG			SPI_MEM_MAP_VALUE(0x50)
-#define SPI_RECEIVE_CONTROL_REG			SPI_MEM_MAP_VALUE(0x54)
-#define SPI_RECEIVE_BUFFER_REG			SPI_MEM_MAP_VALUE(0x58)
-#define SPI_FIFO_TRANSMIT_CONFIG_REG		SPI_MEM_MAP_VALUE(0x5C)
-#define SPI_FIFO_TRANSMIT_CONTROL_REG		SPI_MEM_MAP_VALUE(0x60)
-#define SPI_FIFO_RECEIVE_CONFIG_REG		SPI_MEM_MAP_VALUE(0x64)
-#define SPI_INTERRUPT_STATUS_REG		SPI_MEM_MAP_VALUE(0x68)
-#define SPI_INTERRUPT_ENABLE_REG		SPI_MEM_MAP_VALUE(0x6C)
-
-#define SPI_TRANSMIT_BUFFER_REG_ADDR		(CNS3XXX_SSP_BASE +0x50)
-#define SPI_RECEIVE_BUFFER_REG_ADDR		(CNS3XXX_SSP_BASE +0x58)
+#define SPI_MEM_MAP_VALUE(reg_offset)		(*((u32 volatile *)(hw->base + reg_offset)))
+
+#define SPI_CONFIGURATION_REG			SPI_MEM_MAP_VALUE(0x00)
+#define SPI_SERVICE_STATUS_REG			SPI_MEM_MAP_VALUE(0x04)
+#define SPI_BIT_RATE_CONTROL_REG		SPI_MEM_MAP_VALUE(0x08)
+#define SPI_TRANSMIT_CONTROL_REG		SPI_MEM_MAP_VALUE(0x0C)
+#define SPI_TRANSMIT_BUFFER_REG			SPI_MEM_MAP_VALUE(0x10)
+#define SPI_RECEIVE_CONTROL_REG			SPI_MEM_MAP_VALUE(0x14)
+#define SPI_RECEIVE_BUFFER_REG			SPI_MEM_MAP_VALUE(0x18)
+#define SPI_FIFO_TRANSMIT_CONFIG_REG		SPI_MEM_MAP_VALUE(0x1C)
+#define SPI_FIFO_TRANSMIT_CONTROL_REG		SPI_MEM_MAP_VALUE(0x20)
+#define SPI_FIFO_RECEIVE_CONFIG_REG		SPI_MEM_MAP_VALUE(0x24)
+#define SPI_INTERRUPT_STATUS_REG		SPI_MEM_MAP_VALUE(0x28)
+#define SPI_INTERRUPT_ENABLE_REG		SPI_MEM_MAP_VALUE(0x2C)
+
+#define SPI_TRANSMIT_BUFFER_REG_ADDR		(CNS3XXX_SSP_BASE +0x10)
+#define SPI_RECEIVE_BUFFER_REG_ADDR		(CNS3XXX_SSP_BASE +0x18)
 
 /* Structure for SPI controller of CNS3XXX SOCs */
 struct cns3xxx_spi {
@@ -85,42 +83,43 @@ struct cns3xxx_spi {
 	const unsigned char *tx;
 	unsigned char *rx;
 
+	void __iomem *base;
 	struct spi_master *master;
 	struct platform_device *pdev;
 	struct device *dev;
 };
 
-static inline u8 cns3xxx_spi_bus_idle(void)
+static inline u8 cns3xxx_spi_bus_idle(struct cns3xxx_spi *hw)
 {
 	return ((SPI_SERVICE_STATUS_REG & 0x1) ? 0 : 1);
 }
 
-static inline u8 cns3xxx_spi_tx_buffer_empty(void)
+static inline u8 cns3xxx_spi_tx_buffer_empty(struct cns3xxx_spi *hw)
 {
 	return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 3)) ? 1 : 0);
 }
 
-static inline u8 cns3xxx_spi_rx_buffer_full(void)
+static inline u8 cns3xxx_spi_rx_buffer_full(struct cns3xxx_spi *hw)
 {
 	return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 2)) ? 1 : 0);
 }
 
-u8 cns3xxx_spi_tx_rx(u8 tx_channel, u8 tx_eof, u32 tx_data,
-			    u32 * rx_data)
+u8 cns3xxx_spi_tx_rx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof,
+		     u32 tx_data, u32 * rx_data)
 {
 	u8 rx_channel;
 	u8 rx_eof;
 
-	while (!cns3xxx_spi_bus_idle()) ;	// do nothing
+	while (!cns3xxx_spi_bus_idle(hw)) ;	// do nothing
 
-	while (!cns3xxx_spi_tx_buffer_empty()) ;	// do nothing
+	while (!cns3xxx_spi_tx_buffer_empty(hw)) ;	// do nothing
 
 	SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
 	SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
 
 	SPI_TRANSMIT_BUFFER_REG = tx_data;
 
-	while (!cns3xxx_spi_rx_buffer_full()) ;	// do nothing
+	while (!cns3xxx_spi_rx_buffer_full(hw)) ;	// do nothing
 
 	rx_channel = SPI_RECEIVE_CONTROL_REG & 0x3;
 	rx_eof = (SPI_RECEIVE_CONTROL_REG & (0x1 << 2)) ? 1 : 0;
@@ -134,12 +133,12 @@ u8 cns3xxx_spi_tx_rx(u8 tx_channel, u8 tx_eof, u32 tx_data,
 	}
 }
 
-u8 cns3xxx_spi_tx(u8 tx_channel, u8 tx_eof, u32 tx_data)
+u8 cns3xxx_spi_tx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof, u32 tx_data)
 {
 
-        while (!cns3xxx_spi_bus_idle()) ;       // do nothing
+        while (!cns3xxx_spi_bus_idle(hw)) ;       // do nothing
 
-        while (!cns3xxx_spi_tx_buffer_empty()) ;        // do nothing
+        while (!cns3xxx_spi_tx_buffer_empty(hw)) ;        // do nothing
 
         SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
         SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
@@ -162,6 +161,7 @@ static int cns3xxx_spi_setup_transfer(struct spi_device *spi,
 
 static void cns3xxx_spi_chipselect(struct spi_device *spi, int value)
 {
+	struct cns3xxx_spi *hw = to_hw(spi);
 	unsigned int spi_config;
 
 	switch (value) {
@@ -221,7 +221,7 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
 			dev_dbg(&spi->dev,
 				"[SPI_CNS3XXX_DEBUG] hw->tx[%02d]: 0x%02x\n", i,
 				hw->tx[i]);
-			cns3xxx_spi_tx_rx(spi->chip_select, 0, hw->tx[i],
+			cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i],
 					  &rx_data);
 			if (hw->rx) {
 				hw->rx[i] = rx_data;
@@ -232,7 +232,7 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
 		}
 
 		if (t->last_in_message_list) {
-			cns3xxx_spi_tx_rx(spi->chip_select, 1, hw->tx[i],
+			cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, hw->tx[i],
 					  &rx_data);
 			if (hw->rx) {
 				hw->rx[i] = rx_data;
@@ -241,7 +241,7 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
 					i, hw->rx[i]);
 			}
 		} else {
-			cns3xxx_spi_tx_rx(spi->chip_select, 0, hw->tx[i],
+			cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i],
 					  &rx_data);
 		}
 		goto done;
@@ -251,7 +251,7 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
 		int i;
 		u32 rx_data;
 		for (i = 0; i < (hw->len - 1); i++) {
-			cns3xxx_spi_tx_rx(spi->chip_select, 0, 0xff, &rx_data);
+			cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data);
 			hw->rx[i] = rx_data;
 			dev_dbg(&spi->dev,
 				"[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", i,
@@ -259,9 +259,9 @@ static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
 		}
 
 		if (t->last_in_message_list) {
-			cns3xxx_spi_tx_rx(spi->chip_select, 1, 0xff, &rx_data);
+			cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, 0xff, &rx_data);
 		} else {
-			cns3xxx_spi_tx_rx(spi->chip_select, 0, 0xff, &rx_data);
+			cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data);
 		}
 		hw->rx[i] = rx_data;
 		dev_dbg(&spi->dev, "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
@@ -271,21 +271,8 @@ done:
 	return hw->len;
 }
 
-static void __init cns3xxx_spi_initial(void)
+static void __init cns3xxx_spi_initial(struct cns3xxx_spi *hw)
 {
-	u32 __iomem *gpiob = (void __iomem *) (CNS3XXX_MISC_BASE_VIRT + 0x0018);
-	u32 gpiob_pins = __raw_readl(gpiob);
-
-	/* MMC/SD pins share with GPIOA */
-	gpiob_pins |= 0xf80;
-	__raw_writel(gpiob_pins, gpiob);
-
-	/* share pin config. */
-	//PM_PLL_HM_PD_CTRL_REG &= ~(0x1 << 5);
-	//HAL_MISC_ENABLE_SPI_PINS();
-	cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
-	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
-
 	SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) |	/* 8bits shift length */
 				 (0x0 << 9) |	/* SPI mode */
 				 (0x0 << 10) |	/* disable FIFO */
@@ -328,10 +315,15 @@ static int cns3xxx_spi_probe(struct platform_device *pdev)
 {
 	struct spi_master *master;
 	struct cns3xxx_spi *hw;
+	struct resource *res;
 	int err = 0;
 
 	printk("%s: setup CNS3XXX SPI Controller\n", __FUNCTION__);
 
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
 	/* Allocate master with space for cns3xxx_spi */
 	master = spi_alloc_master(&pdev->dev, sizeof(struct cns3xxx_spi));
 	if (master == NULL) {
@@ -346,6 +338,13 @@ static int cns3xxx_spi_probe(struct platform_device *pdev)
 	hw->master = spi_master_get(master);
 	hw->dev = &pdev->dev;
 
+	hw->base = devm_ioremap_resource(hw->dev, res);
+	if (IS_ERR(hw->base)) {
+		dev_err(hw->dev, "Unable to map registers\n");
+		err = PTR_ERR(hw->base);
+		goto err_register;
+	}
+
 	platform_set_drvdata(pdev, hw);
 	init_completion(&hw->done);
 
@@ -365,7 +364,7 @@ static int cns3xxx_spi_probe(struct platform_device *pdev)
 	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
 
 	/* SPI controller initializations */
-	cns3xxx_spi_initial();
+	cns3xxx_spi_initial(hw);
 
 	/* register SPI controller */
 
diff --git a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_attr.c b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_attr.c
index 45d06788a2..3fb67b9347 100644
--- a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_attr.c
+++ b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_attr.c
@@ -694,7 +694,7 @@ static ssize_t regdump_show( struct device *_dev,
    	return sprintf( buf, "Register Dump\n" );
 }
 
-DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0);
+DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
 
 /**
  * Dump global registers and either host or device registers (depending on the
@@ -711,7 +711,7 @@ static ssize_t spramdump_show( struct device *_dev,
         return sprintf( buf, "SPRAM Dump\n" );
 }
 
-DEVICE_ATTR(spramdump, S_IRUGO|S_IWUSR, spramdump_show, 0);
+DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);
 
 /**
  * Dump the current hcd state.
@@ -729,7 +729,7 @@ static ssize_t hcddump_show( struct device *_dev,
    	return sprintf( buf, "HCD Dump\n" );
 }
 
-DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0);
+DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);
 
 /**
  * Dump the average frame remaining at SOF. This can be used to
@@ -748,7 +748,7 @@ static ssize_t hcd_frrem_show( struct device *_dev,
    	return sprintf( buf, "HCD Dump Frame Remaining\n" );
 }
 
-DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0);
+DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);
 
 /**
  * Displays the time required to read the GNPTXFSIZ register many times (the
@@ -777,7 +777,7 @@ static ssize_t rd_reg_test_show( struct device *_dev,
 			RW_REG_COUNT, time * MSEC_PER_JIFFIE, time );
 }
 
-DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0);
+DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);
 
 /**
  * Displays the time required to write the GNPTXFSIZ register many times (the
@@ -806,7 +806,7 @@ static ssize_t wr_reg_test_show( struct device *_dev,
 			RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
 }
 
-DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
+DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);
 /**@}*/
 
 /**
diff --git a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c
index f1fece8bf8..549c6ebdbd 100644
--- a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c
+++ b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c
@@ -63,7 +63,6 @@
 #include <asm/io.h>
 
 #include <asm/sizes.h>
-#include <mach/pm.h>
 
 #include "otg_plat.h"
 #include "otg_attr.h"
diff --git a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd.c b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd.c
index 5f33fa530a..9c1d04f5f4 100644
--- a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd.c
+++ b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd.c
@@ -51,8 +51,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/version.h>
 
-#include <mach/irqs.h>
-
 #include "otg_driver.h"
 #include "otg_hcd.h"
 #include "otg_regs.h"
diff --git a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd_queue.c b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd_queue.c
index 6e7b53c392..aaed49dcd6 100644
--- a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd_queue.c
+++ b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_hcd_queue.c
@@ -49,8 +49,6 @@
 #include <linux/string.h>
 #include <linux/version.h>
 
-#include <mach/irqs.h>
-
 #include "otg_driver.h"
 #include "otg_hcd.h"
 #include "otg_regs.h"
diff --git a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_pcd.c b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_pcd.c
index 823989a6f5..967997c88d 100644
--- a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_pcd.c
+++ b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_pcd.c
@@ -75,7 +75,6 @@
 #include <linux/dma-mapping.h>
 #include <linux/version.h>
 
-#include <mach/irqs.h>
 #include <linux/usb/ch9.h>
 
 //#include <linux/usb_gadget.h>
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/platform.h b/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h
index f286d0dfe9..f286d0dfe9 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/platform.h
+++ b/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h