brcm63xx: add initial support for BCM63268

Add initial support for the BCM63268 family of SoCs, but keep it
disabled for now as most things don't work yet.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>

SVN-Revision: 39271

14 files changed, 978 insertions, 15 deletions

diff --git a/target/linux/brcm63xx/config-3.10 b/target/linux/brcm63xx/config-3.10
index 7234bc465a..593513637a 100644
--- a/target/linux/brcm63xx/config-3.10
+++ b/target/linux/brcm63xx/config-3.10
@@ -16,6 +16,7 @@ CONFIG_B53_SPI_DRIVER=y
 # CONFIG_B53_SRAB_DRIVER is not set
 CONFIG_BCM63XX=y
 CONFIG_BCM63XX_CPU_3368=y
+# CONFIG_BCM63XX_CPU_63268 is not set
 CONFIG_BCM63XX_CPU_6328=y
 CONFIG_BCM63XX_CPU_6338=y
 CONFIG_BCM63XX_CPU_6345=y
diff --git a/target/linux/brcm63xx/patches-3.10/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch b/target/linux/brcm63xx/patches-3.10/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch
new file mode 100644
index 0000000000..d6eb54d2e8
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.10/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch
@@ -0,0 +1,70 @@
+From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 8 Dec 2013 03:13:06 +0100
+Subject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows
+
+Different SoCs use different memory windows (and sizes), so don't
+hardcode it.
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h |  8 ++++----
+ arch/mips/pci/pci-bcm63xx.c                     | 15 ++++++++++-----
+ 2 files changed, 14 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -40,10 +40,10 @@
+ #define BCM_CB_MEM_END_PA		(BCM_CB_MEM_BASE_PA +		\
+ 					BCM_CB_MEM_SIZE - 1)
+ 
+-#define BCM_PCIE_MEM_BASE_PA		0x10f00000
+-#define BCM_PCIE_MEM_SIZE		(1 * 1024 * 1024)
+-#define BCM_PCIE_MEM_END_PA		(BCM_PCIE_MEM_BASE_PA +		\
+-					BCM_PCIE_MEM_SIZE - 1)
++#define BCM_PCIE_MEM_BASE_PA_6328	0x10f00000
++#define BCM_PCIE_MEM_SIZE_6328		(1 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA_6328	(BCM_PCIE_MEM_BASE_PA_6328 +	\
++					BCM_PCIE_MEM_SIZE_6328 - 1)
+ 
+ /*
+  * Internal registers are accessed through KSEG3
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control
+ 
+ static struct resource bcm_pcie_mem_resource = {
+ 	.name	= "bcm63xx PCIe memory space",
+-	.start	= BCM_PCIE_MEM_BASE_PA,
+-	.end	= BCM_PCIE_MEM_END_PA,
++	.start	= 0,
++	.end	= 0,
+ 	.flags	= IORESOURCE_MEM,
+ };
+ 
+@@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie(
+ 	bcm_pcie_writel(val, PCIE_CONFIG2_REG);
+ 
+ 	/* set bar0 to little endian */
+-	val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
+-	val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
++	val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
++	val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
+ 	val |= BASEMASK_REMAP_EN;
+ 	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
+ 
+-	val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
++	val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
+ 	bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
+ 
+ 	register_pci_controller(&bcm63xx_pcie_controller);
+@@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void)
+ 	if (!bcm63xx_pci_enabled)
+ 		return -ENODEV;
+ 
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
++		bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
++		bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
++	}
++
+ 	switch (bcm63xx_get_cpu_id()) {
+ 	case BCM6328_CPU_ID:
+ 	case BCM6362_CPU_ID:
diff --git a/target/linux/brcm63xx/patches-3.10/337-MIPS-BCM63XX-widen-cpuid-field.patch b/target/linux/brcm63xx/patches-3.10/337-MIPS-BCM63XX-widen-cpuid-field.patch
new file mode 100644
index 0000000000..5b641a0026
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.10/337-MIPS-BCM63XX-widen-cpuid-field.patch
@@ -0,0 +1,47 @@
+From f1477f6e3551fd6beecfee5368fed1325dcd421f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sat, 7 Dec 2013 14:54:51 +0100
+Subject: [PATCH 47/53] MIPS: BCM63XX: widen cpuid field
+
+---
+ arch/mips/bcm63xx/cpu.c                          | 2 +-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++----
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -24,7 +24,7 @@ EXPORT_SYMBOL(bcm63xx_regs_base);
+ const int *bcm63xx_irqs;
+ EXPORT_SYMBOL(bcm63xx_irqs);
+ 
+-u16 bcm63xx_cpu_id __read_mostly;
++u32 bcm63xx_cpu_id __read_mostly;
+ EXPORT_SYMBOL(bcm63xx_cpu_id);
+ 
+ static u32 bcm63xx_cpu_variant __read_mostly;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -27,7 +27,7 @@ u32 bcm63xx_get_cpu_variant(void);
+ u8 bcm63xx_get_cpu_rev(void);
+ unsigned int bcm63xx_get_cpu_freq(void);
+ 
+-static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)
++static inline u32 __pure __bcm63xx_get_cpu_id(const u32 cpu_id)
+ {
+ 	switch (cpu_id) {
+ #ifdef CONFIG_BCM63XX_CPU_3368
+@@ -69,11 +69,11 @@ static inline u16 __pure __bcm63xx_get_c
+ 	return cpu_id;
+ }
+ 
+-extern u16 bcm63xx_cpu_id;
++extern u32 bcm63xx_cpu_id;
+ 
+-static inline u16 __pure bcm63xx_get_cpu_id(void)
++static inline u32 __pure bcm63xx_get_cpu_id(void)
+ {
+-	const u16 cpu_id = bcm63xx_cpu_id;
++	const u32 cpu_id = bcm63xx_cpu_id;
+ 
+ 	return __bcm63xx_get_cpu_id(cpu_id);
+ }
diff --git a/target/linux/brcm63xx/patches-3.10/338-MIPS-BCM63XX-increase-number-of-IRQs.patch b/target/linux/brcm63xx/patches-3.10/338-MIPS-BCM63XX-increase-number-of-IRQs.patch
new file mode 100644
index 0000000000..9132e42312
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.10/338-MIPS-BCM63XX-increase-number-of-IRQs.patch
@@ -0,0 +1,39 @@
+From 6f5658c845cf1f79213b1d20423a04967259fdaa Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 15 Dec 2013 20:46:26 +0100
+Subject: [PATCH 48/53] MIPS: BCM63XX: increase number of IRQs
+
+Newer SoCs have 128 bit wide irq registers, thus 128 available internal
+interupts.
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h | 4 +++-
+ arch/mips/include/asm/mach-bcm63xx/irq.h         | 2 +-
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+@@ -1,10 +1,12 @@
+ #ifndef BCM63XX_IRQ_H_
+ #define BCM63XX_IRQ_H_
+ 
++#include <irq.h>
+ #include <bcm63xx_cpu.h>
+ 
+ #define IRQ_INTERNAL_BASE		8
+-#define IRQ_EXTERNAL_BASE		100
++#define NR_INTERNAL_IRQS		128
++#define IRQ_EXTERNAL_BASE		(IRQ_INTERNAL_BASE + NR_INTERNAL_IRQS)
+ #define IRQ_EXT_0			(IRQ_EXTERNAL_BASE + 0)
+ #define IRQ_EXT_1			(IRQ_EXTERNAL_BASE + 1)
+ #define IRQ_EXT_2			(IRQ_EXTERNAL_BASE + 2)
+--- a/arch/mips/include/asm/mach-bcm63xx/irq.h
++++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
+@@ -1,7 +1,7 @@
+ #ifndef __ASM_MACH_BCM63XX_IRQ_H
+ #define __ASM_MACH_BCM63XX_IRQ_H
+ 
+-#define NR_IRQS 128
++#define NR_IRQS 256
+ #define MIPS_CPU_IRQ_BASE 0
+ 
+ #endif
diff --git a/target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch
new file mode 100644
index 0000000000..ca642db5c5
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch
@@ -0,0 +1,713 @@
+From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sat, 7 Dec 2013 17:14:17 +0100
+Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/Kconfig                         |   5 +
+ arch/mips/bcm63xx/boards/board_bcm963xx.c         |   2 +-
+ arch/mips/bcm63xx/clk.c                           |  25 ++++-
+ arch/mips/bcm63xx/cpu.c                           |  59 +++++++++-
+ arch/mips/bcm63xx/dev-flash.c                     |   6 +
+ arch/mips/bcm63xx/dev-spi.c                       |   4 +-
+ arch/mips/bcm63xx/irq.c                           |  20 +++-
+ arch/mips/bcm63xx/reset.c                         |  21 ++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  | 130 ++++++++++++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |   2 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  79 +++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/ioremap.h      |   1 +
+ 12 files changed, 342 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -60,6 +60,11 @@ config BCM63XX_CPU_6368
+ 	select HW_HAS_PCI
+ 	select BCM63XX_OHCI
+ 	select BCM63XX_EHCI
++
++config BCM63XX_CPU_63268
++	bool "support 63268 CPU"
++	select SYS_HAS_CPU_BMIPS4350
++	select HW_HAS_PCI
+ endmenu
+ 
+ source "arch/mips/bcm63xx/boards/Kconfig"
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -825,7 +825,7 @@ void __init board_prom_init(void)
+ 	/* read base address of boot chip select (0)
+ 	 * 6328/6362 do not have MPI but boot from a fixed address
+ 	 */
+-	if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
+ 		val = 0x18000000;
+ 	} else {
+ 		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -133,6 +133,8 @@ static void enetsw_set(struct clk *clk,
+ 				CKCTL_6368_SWPKT_USB_EN |
+ 				CKCTL_6368_SWPKT_SAR_EN,
+ 				enable);
++	else if (BCMCPU_IS_63268())
++		bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable);
+ 	else
+ 		return;
+ 
+@@ -177,6 +179,8 @@ static void usbh_set(struct clk *clk, in
+ 		bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
+ 	else if (BCMCPU_IS_6368())
+ 		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
++	else if (BCMCPU_IS_63268())
++		bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
+ 	else
+ 		return;
+ 
+@@ -199,6 +203,8 @@ static void usbd_set(struct clk *clk, in
+ 		bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
+ 	else if (BCMCPU_IS_6368())
+ 		bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
++	else if (BCMCPU_IS_63268())
++		bcm_hwclock_set(CKCTL_63268_USBD_EN, enable);
+ 	else
+ 		return;
+ 
+@@ -225,9 +231,13 @@ static void spi_set(struct clk *clk, int
+ 		mask = CKCTL_6358_SPI_EN;
+ 	else if (BCMCPU_IS_6362())
+ 		mask = CKCTL_6362_SPI_EN;
+-	else
+-		/* BCMCPU_IS_6368 */
++	else if (BCMCPU_IS_6368())
+ 		mask = CKCTL_6368_SPI_EN;
++	else if (BCMCPU_IS_63268())
++		mask = CKCTL_63268_SPI_EN;
++	else
++		return;
++
+ 	bcm_hwclock_set(mask, enable);
+ }
+ 
+@@ -246,6 +256,8 @@ static void hsspi_set(struct clk *clk, i
+ 		mask = CKCTL_6328_HSSPI_EN;
+ 	else if (BCMCPU_IS_6362())
+ 		mask = CKCTL_6362_HSSPI_EN;
++	else if (BCMCPU_IS_63268())
++		mask = CKCTL_63268_HSSPI_EN;
+ 	else
+ 		return;
+ 
+@@ -307,6 +319,8 @@ static void pcie_set(struct clk *clk, in
+ 		bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
+ 	else if (BCMCPU_IS_6362())
+ 		bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
++	else if (BCMCPU_IS_63268())
++		bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);
+ }
+ 
+ static struct clk clk_pcie = {
+@@ -374,9 +388,11 @@ struct clk *clk_get(struct device *dev,
+ 		return &clk_periph;
+ 	if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
+ 		return &clk_pcm;
+-	if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
++	if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) &&
++	    !strcmp(id, "ipsec"))
+ 		return &clk_ipsec;
+-	if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
++	if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) &&
++	    !strcmp(id, "pcie"))
+ 		return &clk_pcie;
+ 	return ERR_PTR(-ENOENT);
+ }
+@@ -399,6 +415,7 @@ static int __init bcm63xx_clk_init(void)
+ 		clk_hsspi.rate = HSSPI_PLL_HZ_6328;
+ 		break;
+ 	case BCM6362_CPU_ID:
++	case BCM63268_CPU_ID:
+ 		clk_hsspi.rate = HSSPI_PLL_HZ_6362;
+ 		break;
+ 	}
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = {
+ 
+ };
+ 
++static const unsigned long bcm63268_regs_base[] = {
++	__GEN_CPU_REGS_TABLE(63268)
++};
++
++static const int bcm63268_irqs[] = {
++	__GEN_CPU_IRQ_TABLE(63268)
++
++};
++
+ u32 bcm63xx_get_cpu_variant(void)
+ {
+ 	return bcm63xx_cpu_variant;
+@@ -251,6 +260,27 @@ static unsigned int detect_cpu_clock(voi
+ 
+ 		return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
+ 	}
++	case BCM63268_CPU_ID:
++	{
++		unsigned int tmp, mips_pll_fcvo;
++
++		tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
++		mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >>
++				STRAPBUS_63268_FCVO_SHIFT;
++		switch (mips_pll_fcvo) {
++		case 0x3:
++		case 0xe:
++			return 320000000;
++		case 0xa:
++			return 333000000;
++		case 0x2:
++		case 0xb:
++		case 0xf:
++			return 400000000;
++		default:
++			return 0;
++		}
++	}
+ 
+ 	default:
+ 		BUG();
+@@ -265,7 +295,7 @@ static unsigned int detect_memory_size(v
+ 	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+ 	u32 val;
+ 
+-	if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
++	if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
+ 		return bcm_ddr_readl(DDR_CSEND_REG) << 24;
+ 
+ 	if (BCMCPU_IS_6345()) {
+@@ -304,6 +334,7 @@ void __init bcm63xx_cpu_init(void)
+ 	struct cpuinfo_mips *c = &current_cpu_data;
+ 	unsigned int cpu = smp_processor_id();
+ 	u32 chipid_reg;
++	bool long_chipid = false;
+ 	u8 varid;
+ 
+ 	/* soc registers location depends on cpu type */
+@@ -325,6 +356,9 @@ void __init bcm63xx_cpu_init(void)
+ 		case 0x10:
+ 			chipid_reg = BCM_6345_PERF_BASE;
+ 			break;
++		case 0x80:
++			long_chipid = true;
++			/* fall-through */
+ 		default:
+ 			chipid_reg = BCM_6368_PERF_BASE;
+ 			break;
+@@ -332,6 +366,7 @@ void __init bcm63xx_cpu_init(void)
+ 		break;
+ 	}
+ 
++
+ 	/*
+ 	 * really early to panic, but delaying panic would not help since we
+ 	 * will never get any working console
+@@ -341,10 +376,17 @@ void __init bcm63xx_cpu_init(void)
+ 
+ 	/* read out CPU type */
+ 	tmp = bcm_readl(chipid_reg);
+-	bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
+-	bcm63xx_cpu_variant = bcm63xx_cpu_id;
++
++	if (long_chipid) {
++		bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK;
++		bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT;
++	} else {
++		bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
++		varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
++	}
++
+ 	bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
+-	varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
++	bcm63xx_cpu_variant = bcm63xx_cpu_id;
+ 
+ 	switch (bcm63xx_cpu_id) {
+ 	case BCM3368_CPU_ID:
+@@ -399,6 +441,15 @@ void __init bcm63xx_cpu_init(void)
+ 		/* BCM6369 is a BCM6368 without xDSL, so treat it the same */
+ 		bcm63xx_cpu_id = BCM6368_CPU_ID;
+ 		break;
++	case BCM63168_CPU_ID:
++	case BCM63169_CPU_ID:
++	case BCM63268_CPU_ID:
++	case BCM63269_CPU_ID:
++		bcm63xx_regs_base = bcm63268_regs_base;
++		bcm63xx_irqs = bcm63268_irqs;
++
++		bcm63xx_cpu_id = BCM63268_CPU_ID;
++		break;
+ 	default:
+ 		panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
+ 		break;
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -94,6 +94,12 @@ static int __init bcm63xx_detect_flash_t
+ 		case STRAPBUS_6368_BOOT_SEL_PARALLEL:
+ 			return BCM63XX_FLASH_TYPE_PARALLEL;
+ 		}
++	case BCM63268_CPU_ID:
++		val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
++		if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
++			return BCM63XX_FLASH_TYPE_SERIAL;
++		else
++			return BCM63XX_FLASH_TYPE_NAND;
+ 	default:
+ 		return -EINVAL;
+ 	}
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init
+ 	if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
+ 		bcm63xx_regs_spi = bcm6348_regs_spi;
+ 	if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||
+-		BCMCPU_IS_6362() || BCMCPU_IS_6368())
++		BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268())
+ 		bcm63xx_regs_spi = bcm6358_regs_spi;
+ }
+ 
+@@ -85,7 +85,7 @@ int __init bcm63xx_spi_register(void)
+ 	}
+ 
+ 	if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
+-		BCMCPU_IS_6368()) {
++		BCMCPU_IS_6368() || BCMCPU_IS_63268()) {
+ 		spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
+ 		spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
+ 		spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -158,6 +158,7 @@ static void __internal_irq_unmask_##widt
+ 
+ BUILD_IPIC_INTERNAL(32);
+ BUILD_IPIC_INTERNAL(64);
++BUILD_IPIC_INTERNAL(128);
+ 
+ asmlinkage void plat_irq_dispatch(void)
+ {
+@@ -343,6 +344,7 @@ static int bcm63xx_external_irq_set_type
+ 	case BCM6358_CPU_ID:
+ 	case BCM6362_CPU_ID:
+ 	case BCM6368_CPU_ID:
++	case BCM63268_CPU_ID:
+ 		if (levelsense)
+ 			reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+ 		else
+@@ -515,6 +517,18 @@ static void bcm63xx_init_irq(void)
+ 		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
+ 		ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
+ 		break;
++	case BCM63268_CPU_ID:
++		irq_stat_addr[0] += PERF_IRQSTAT_63268_REG(0);
++		irq_mask_addr[0] += PERF_IRQMASK_63268_REG(0);
++		irq_stat_addr[1] += PERF_IRQSTAT_63268_REG(1);
++		irq_mask_addr[1] += PERF_IRQMASK_63268_REG(1);
++		irq_bits = 128;
++		ext_irq_count = 4;
++		is_ext_irq_cascaded = 1;
++		ext_irq_start = BCM_63268_EXT_IRQ0 - IRQ_INTERNAL_BASE;
++		ext_irq_end = BCM_63268_EXT_IRQ3 - IRQ_INTERNAL_BASE;
++		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_63268;
++		break;
+ 	default:
+ 		BUG();
+ 	}
+@@ -523,10 +537,14 @@ static void bcm63xx_init_irq(void)
+ 		dispatch_internal = __dispatch_internal_32;
+ 		internal_irq_mask = __internal_irq_mask_32;
+ 		internal_irq_unmask = __internal_irq_unmask_32;
+-	} else {
++	} else if (irq_bits == 64) {
+ 		dispatch_internal = __dispatch_internal_64;
+ 		internal_irq_mask = __internal_irq_mask_64;
+ 		internal_irq_unmask = __internal_irq_unmask_64;
++	} else {
++		dispatch_internal = __dispatch_internal_128;
++		internal_irq_mask = __internal_irq_mask_128;
++		internal_irq_unmask = __internal_irq_unmask_128;
+ 	}
+ }
+ 
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -125,6 +125,20 @@
+ #define BCM6368_RESET_PCIE	0
+ #define BCM6368_RESET_PCIE_EXT	0
+ 
++#define BCM63268_RESET_SPI	SOFTRESET_63268_SPI_MASK
++#define BCM63268_RESET_ENET	0
++#define BCM63268_RESET_USBH	SOFTRESET_63268_USBH_MASK
++#define BCM63268_RESET_USBD	SOFTRESET_63268_USBS_MASK
++#define BCM63268_RESET_DSL	0
++#define BCM63268_RESET_SAR	SOFTRESET_63268_SAR_MASK
++#define BCM63268_RESET_EPHY	0
++#define BCM63268_RESET_ENETSW	SOFTRESET_63268_ENETSW_MASK
++#define BCM63268_RESET_PCM	SOFTRESET_63268_PCM_MASK
++#define BCM63268_RESET_MPI	0
++#define BCM63268_RESET_PCIE	(SOFTRESET_63268_PCIE_MASK | \
++				 SOFTRESET_63268_PCIE_CORE_MASK)
++#define BCM63268_RESET_PCIE_EXT	SOFTRESET_63268_PCIE_EXT_MASK
++
+ /*
+  * core reset bits
+  */
+@@ -156,6 +170,10 @@ static const u32 bcm6368_reset_bits[] =
+ 	__GEN_RESET_BITS_TABLE(6368)
+ };
+ 
++static const u32 bcm63268_reset_bits[] = {
++	__GEN_RESET_BITS_TABLE(63268)
++};
++
+ const u32 *bcm63xx_reset_bits;
+ static int reset_reg;
+ 
+@@ -182,6 +200,9 @@ static int __init bcm63xx_reset_bits_ini
+ 	} else if (BCMCPU_IS_6368()) {
+ 		reset_reg = PERF_SOFTRESET_6368_REG;
+ 		bcm63xx_reset_bits = bcm6368_reset_bits;
++	} else if (BCMCPU_IS_63268()) {
++		reset_reg = PERF_SOFTRESET_63268_REG;
++		bcm63xx_reset_bits = bcm63268_reset_bits;
+ 	}
+ 
+ 	return 0;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -21,6 +21,10 @@
+ #define BCM6362_CPU_ID		0x6362
+ #define BCM6368_CPU_ID		0x6368
+ #define BCM6369_CPU_ID		0x6369
++#define BCM63168_CPU_ID		0x63168
++#define BCM63169_CPU_ID		0x63169
++#define BCM63268_CPU_ID		0x63268
++#define BCM63269_CPU_ID		0x63269
+ 
+ void __init bcm63xx_cpu_init(void);
+ u32 bcm63xx_get_cpu_variant(void);
+@@ -61,6 +65,10 @@ static inline u32 __pure __bcm63xx_get_c
+ #ifdef CONFIG_BCM63XX_CPU_6368
+ 		case BCM6368_CPU_ID:
+ #endif
++
++#ifdef CONFIG_BCM63XX_CPU_63268
++		case BCM63268_CPU_ID:
++#endif
+ 		break;
+ 	default:
+ 		unreachable();
+@@ -86,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu
+ #define BCMCPU_IS_6358()	(bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
+ #define BCMCPU_IS_6362()	(bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
+ #define BCMCPU_IS_6368()	(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
++#define BCMCPU_IS_63268()	(bcm63xx_get_cpu_id() == BCM63268_CPU_ID)
+ 
+ #define BCMCPU_VARIANT_IS_3368() \
+ 	(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
+@@ -109,6 +118,14 @@ static inline u32 __pure bcm63xx_get_cpu
+ 	(bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
+ #define BCMCPU_VARIANT_IS_6369() \
+ 	(bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
++#define BCMCPU_VARIANT_IS_63168() \
++	(bcm63xx_get_cpu_variant() == BCM63168_CPU_ID)
++#define BCMCPU_VARIANT_IS_63169() \
++	(bcm63xx_get_cpu_variant() == BCM63169_CPU_ID)
++#define BCMCPU_VARIANT_IS_63268() \
++	(bcm63xx_get_cpu_variant() == BCM63268_CPU_ID)
++#define BCMCPU_VARIANT_IS_63269() \
++	(bcm63xx_get_cpu_variant() == BCM63269_CPU_ID)
+ 
+ /*
+  * While registers sets are (mostly) the same across 63xx CPU, base
+@@ -573,6 +590,52 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_RNG_BASE		(0xb0004180)
+ #define BCM_6368_MISC_BASE		(0xdeadbeef)
+ 
++/*
++ * 63268 register sets base address
++ */
++#define BCM_63268_DSL_LMEM_BASE		(0xdeadbeef)
++#define BCM_63268_PERF_BASE		(0xb0000000)
++#define BCM_63268_TIMER_BASE		(0xb0000080)
++#define BCM_63268_WDT_BASE		(0xb000009c)
++#define BCM_63268_UART0_BASE		(0xb0000180)
++#define BCM_63268_UART1_BASE		(0xb00001a0)
++#define BCM_63268_GPIO_BASE		(0xb00000c0)
++#define BCM_63268_SPI_BASE		(0xb0000800)
++#define BCM_63268_HSSPI_BASE		(0xb0001000)
++#define BCM_63268_UDC0_BASE		(0xdeadbeef)
++#define BCM_63268_USBDMA_BASE		(0xb000c800)
++#define BCM_63268_OHCI0_BASE		(0xb0002600)
++#define BCM_63268_OHCI_PRIV_BASE	(0xdeadbeef)
++#define BCM_63268_USBH_PRIV_BASE	(0xb0002700)
++#define BCM_63268_USBD_BASE		(0xb0002400)
++#define BCM_63268_MPI_BASE		(0xdeadbeef)
++#define BCM_63268_PCMCIA_BASE		(0xdeadbeef)
++#define BCM_63268_PCIE_BASE		(0xb06e0000)
++#define BCM_63268_SDRAM_REGS_BASE	(0xdeadbeef)
++#define BCM_63268_DSL_BASE		(0xdeadbeef)
++#define BCM_63268_UBUS_BASE		(0xdeadbeef)
++#define BCM_63268_ENET0_BASE		(0xdeadbeef)
++#define BCM_63268_ENET1_BASE		(0xdeadbeef)
++#define BCM_63268_ENETDMA_BASE		(0xb000d800)
++#define BCM_63268_ENETDMAC_BASE		(0xb000da00)
++#define BCM_63268_ENETDMAS_BASE		(0xb000dc00)
++#define BCM_63268_ENETSW_BASE		(0xb0700000)
++#define BCM_63268_EHCI0_BASE		(0xb0002500)
++#define BCM_63268_SDRAM_BASE		(0xdeadbeef)
++#define BCM_63268_MEMC_BASE		(0xdeadbeef)
++#define BCM_63268_DDR_BASE		(0xb0003000)
++#define BCM_63268_M2M_BASE		(0xdeadbeef)
++#define BCM_63268_ATM_BASE		(0xdeadbeef)
++#define BCM_63268_XTM_BASE		(0xb0007000)
++#define BCM_63268_XTMDMA_BASE		(0xb000b800)
++#define BCM_63268_XTMDMAC_BASE		(0xdeadbeef)
++#define BCM_63268_XTMDMAS_BASE		(0xdeadbeef)
++#define BCM_63268_PCM_BASE		(0xb000b000)
++#define BCM_63268_PCMDMA_BASE		(0xb000b800)
++#define BCM_63268_PCMDMAC_BASE		(0xdeadbeef)
++#define BCM_63268_PCMDMAS_BASE		(0xdeadbeef)
++#define BCM_63268_RNG_BASE		(0xdeadbeef)
++#define BCM_63268_MISC_BASE		(0xb0001800)
+ 
+ extern const unsigned long *bcm63xx_regs_base;
+ 
+@@ -1084,6 +1147,73 @@ enum bcm63xx_irq {
+ #define BCM_6368_EXT_IRQ4		(IRQ_INTERNAL_BASE + 24)
+ #define BCM_6368_EXT_IRQ5		(IRQ_INTERNAL_BASE + 25)
+ 
++/*
++ * 63268 irqs
++ */
++#define BCM_63268_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)
++#define BCM_63268_VERY_HIGH_IRQ_BASE	(BCM_63268_HIGH_IRQ_BASE + 32)
++
++#define BCM_63268_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
++#define BCM_63268_SPI_IRQ		(BCM_63268_VERY_HIGH_IRQ_BASE + 16)
++#define BCM_63268_UART0_IRQ		(IRQ_INTERNAL_BASE + 5)
++#define BCM_63268_UART1_IRQ		(BCM_63268_HIGH_IRQ_BASE + 2)
++#define BCM_63268_DSL_IRQ		(IRQ_INTERNAL_BASE + 23)
++#define BCM_63268_UDC0_IRQ		0
++#define BCM_63268_ENET0_IRQ		0
++#define BCM_63268_ENET1_IRQ		0
++#define BCM_63268_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 13)
++#define BCM_63268_HSSPI_IRQ		(IRQ_INTERNAL_BASE + 6)
++#define BCM_63268_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 9)
++#define BCM_63268_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
++#define BCM_63268_USBD_IRQ		(IRQ_INTERNAL_BASE + 11)
++#define BCM_63268_USBD_RXDMA0_IRQ	(IRQ_INTERNAL_BASE + 19)
++#define BCM_63268_USBD_TXDMA0_IRQ	(BCM_63268_HIGH_IRQ_BASE + 4)
++#define BCM_63268_USBD_RXDMA1_IRQ	(IRQ_INTERNAL_BASE + 20)
++#define BCM_63268_USBD_TXDMA1_IRQ	(BCM_63268_HIGH_IRQ_BASE + 5)
++#define BCM_63268_USBD_RXDMA2_IRQ	(IRQ_INTERNAL_BASE + 21)
++#define BCM_63268_USBD_TXDMA2_IRQ	(BCM_63268_HIGH_IRQ_BASE + 6)
++#define BCM_63268_PCMCIA_IRQ		0
++#define BCM_63268_ENET0_RXDMA_IRQ	0
++#define BCM_63268_ENET0_TXDMA_IRQ	0
++#define BCM_63268_ENET1_RXDMA_IRQ	0
++#define BCM_63268_ENET1_TXDMA_IRQ	0
++#define BCM_63268_PCI_IRQ		(BCM_63268_HIGH_IRQ_BASE + 8)
++#define BCM_63268_ATM_IRQ		0
++#define BCM_63268_ENETSW_RXDMA0_IRQ	(IRQ_INTERNAL_BASE + 1)
++#define BCM_63268_ENETSW_RXDMA1_IRQ	(IRQ_INTERNAL_BASE + 2)
++#define BCM_63268_ENETSW_RXDMA2_IRQ	(IRQ_INTERNAL_BASE + 3)
++#define BCM_63268_ENETSW_RXDMA3_IRQ	(IRQ_INTERNAL_BASE + 4)
++#define BCM_63268_ENETSW_TXDMA0_IRQ	(BCM_63268_VERY_HIGH_IRQ_BASE + 0)
++#define BCM_63268_ENETSW_TXDMA1_IRQ	(BCM_63268_VERY_HIGH_IRQ_BASE + 1)
++#define BCM_63268_ENETSW_TXDMA2_IRQ	(BCM_63268_VERY_HIGH_IRQ_BASE + 2)
++#define BCM_63268_ENETSW_TXDMA3_IRQ	(BCM_63268_VERY_HIGH_IRQ_BASE + 3)
++#define BCM_63268_XTM_IRQ		(BCM_63268_HIGH_IRQ_BASE + 17)
++#define BCM_63268_XTM_DMA0_IRQ		(IRQ_INTERNAL_BASE + 26)
++
++#define BCM_63268_RING_OSC_IRQ		(BCM_63268_HIGH_IRQ_BASE + 20)
++#define BCM_63268_WLAN_GPIO_IRQ		(BCM_63268_HIGH_IRQ_BASE + 3)
++#define BCM_63268_WLAN_IRQ		(IRQ_INTERNAL_BASE + 7)
++#define BCM_63268_IPSEC_IRQ		(IRQ_INTERNAL_BASE + 8)
++#define BCM_63268_NAND_IRQ		(BCM_63268_HIGH_IRQ_BASE + 18)
++#define BCM_63268_PCM_IRQ		(IRQ_INTERNAL_BASE + 13)
++#define BCM_63268_DG_IRQ		(IRQ_INTERNAL_BASE + 15)
++#define BCM_63268_EPHY_ENERGY0_IRQ	(IRQ_INTERNAL_BASE + 16)
++#define BCM_63268_EPHY_ENERGY1_IRQ	(IRQ_INTERNAL_BASE + 17)
++#define BCM_63268_EPHY_ENERGY2_IRQ	(IRQ_INTERNAL_BASE + 18)
++#define BCM_63268_EPHY_ENERGY3_IRQ	(IRQ_INTERNAL_BASE + 19)
++#define BCM_63268_IPSEC_DMA0_IRQ	(IRQ_INTERNAL_BASE + 22)
++#define BCM_63268_IPSEC_DMA1_IRQ	(BCM_63268_HIGH_IRQ_BASE + 7)
++#define BCM_63268_FAP0_IRQ		(IRQ_INTERNAL_BASE + 24)
++#define BCM_63268_FAP1_IRQ		(IRQ_INTERNAL_BASE + 25)
++#define BCM_63268_PCM_DMA0_IRQ		(BCM_63268_HIGH_IRQ_BASE + 10)
++#define BCM_63268_PCM_DMA1_IRQ		(BCM_63268_HIGH_IRQ_BASE + 11)
++#define BCM_63268_DECT0_IRQ		(BCM_63268_HIGH_IRQ_BASE + 0)
++#define BCM_63268_DECT1_IRQ		(BCM_63268_HIGH_IRQ_BASE + 1)
++#define BCM_63268_EXT_IRQ0		(BCM_63268_HIGH_IRQ_BASE + 12)
++#define BCM_63268_EXT_IRQ1		(BCM_63268_HIGH_IRQ_BASE + 13)
++#define BCM_63268_EXT_IRQ2		(BCM_63268_HIGH_IRQ_BASE + 14)
++#define BCM_63268_EXT_IRQ3		(BCM_63268_HIGH_IRQ_BASE + 15)
++
+ extern const int *bcm63xx_irqs;
+ 
+ #define __GEN_CPU_IRQ_TABLE(__cpu)					\
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+@@ -22,6 +22,8 @@ static inline unsigned long bcm63xx_gpio
+ 		return 48;
+ 	case BCM6368_CPU_ID:
+ 		return 38;
++	case BCM63268_CPU_ID:
++		return 52;
+ 	case BCM6348_CPU_ID:
+ 	default:
+ 		return 37;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -9,6 +9,8 @@
+ #define PERF_REV_REG			0x0
+ #define REV_CHIPID_SHIFT		16
+ #define REV_CHIPID_MASK			(0xffff << REV_CHIPID_SHIFT)
++#define REV_LONG_CHIPID_SHIFT		12
++#define REV_LONG_CHIPID_MASK		(0xfffff << REV_LONG_CHIPID_SHIFT)
+ #define REV_VARID_SHIFT			8
+ #define REV_VARID_MASK			(0xf << REV_VARID_SHIFT)
+ #define REV_REVID_SHIFT			0
+@@ -211,6 +213,52 @@
+ 					CKCTL_6368_NAND_EN |		\
+ 					CKCTL_6368_IPSEC_EN)
+ 
++#define CKCTL_63268_DISABLE_GLESS	(1 << 0)
++#define CKCTL_63268_VDSL_QPROC_EN	(1 << 1)
++#define CKCTL_63268_VDSL_AFE_EN		(1 << 2)
++#define CKCTL_63268_VDSL_EN		(1 << 3)
++#define CKCTL_63268_MIPS_EN		(1 << 4)
++#define CKCTL_63268_WLAN_OCP_EN		(1 << 5)
++#define CKCTL_63268_DECT_EN		(1 << 6)
++#define CKCTL_63268_FAP0_EN		(1 << 7)
++#define CKCTL_63268_FAP1_EN		(1 << 8)
++#define CKCTL_63268_SAR_EN		(1 << 9)
++#define CKCTL_63268_ROBOSW_EN		(1 << 10)
++#define CKCTL_63268_PCM_EN		(1 << 11)
++#define CKCTL_63268_USBD_EN		(1 << 12)
++#define CKCTL_63268_USBH_EN		(1 << 13)
++#define CKCTL_63268_IPSEC_EN		(1 << 14)
++#define CKCTL_63268_SPI_EN		(1 << 15)
++#define CKCTL_63268_HSSPI_EN		(1 << 16)
++#define CKCTL_63268_PCIE_EN		(1 << 17)
++#define CKCTL_63268_PHYMIPS_EN		(1 << 18)
++#define CKCTL_63268_GMAC_EN		(1 << 19)
++#define CKCTL_63268_NAND_EN		(1 << 20)
++#define CKCTL_63268_TBUS_EN		(1 << 27)
++#define CKCTL_63268_ROBOSW250_EN	(1 << 31)
++
++#define CKCTL_63268_ALL_SAFE_EN		(CKCTL_63268_VDSL_QPROC_EN |	\
++					CKCTL_63268_VDSL_AFE_EN |	\
++					CKCTL_63268_VDSL_EN |		\
++					CKCTL_63268_WLAN_OCP_EN |	\
++					CKCTL_63268_DECT_EN |		\
++					CKCTL_63268_FAP0_EN |		\
++					CKCTL_63268_FAP1_EN |		\
++					CKCTL_63268_SAR_EN |		\
++					CKCTL_63268_ROBOSW_EN |		\
++					CKCTL_63268_PCM_EN |		\
++					CKCTL_63268_USBD_EN |		\
++					CKCTL_63268_USBH_EN |		\
++					CKCTL_63268_IPSEC_EN |		\
++					CKCTL_63268_SPI_EN |		\
++					CKCTL_63268_HSSPI_EN |		\
++					CKCTL_63268_PCIE_EN |		\
++					CKCTL_63268_PHYMIPS_EN |	\
++					CKCTL_63268_GMAC_EN |		\
++					CKCTL_63268_NAND_EN |		\
++					CKCTL_63268_TBUS_EN |		\
++					CKCTL_63268_ROBOSW250_EN)
++
+ /* System PLL Control register	*/
+ #define PERF_SYS_PLL_CTL_REG		0x8
+ #define SYS_PLL_SOFT_RESET		0x1
+@@ -224,6 +272,7 @@
+ #define PERF_IRQMASK_6358_REG(x)	(0xc + (x) * 0x2c)
+ #define PERF_IRQMASK_6362_REG(x)	(0x20 + (x) * 0x10)
+ #define PERF_IRQMASK_6368_REG(x)	(0x20 + (x) * 0x10)
++#define PERF_IRQMASK_63268_REG(x)	(0x20 + (x) * 0x20)
+ 
+ /* Interrupt Status register */
+ #define PERF_IRQSTAT_3368_REG		0x10
+@@ -234,6 +283,7 @@
+ #define PERF_IRQSTAT_6358_REG(x)	(0x10 + (x) * 0x2c)
+ #define PERF_IRQSTAT_6362_REG(x)	(0x28 + (x) * 0x10)
+ #define PERF_IRQSTAT_6368_REG(x)	(0x28 + (x) * 0x10)
++#define PERF_IRQSTAT_63268_REG(x)	(0x30 + (x) * 0x20)
+ 
+ /* External Interrupt Configuration register */
+ #define PERF_EXTIRQ_CFG_REG_3368	0x14
+@@ -244,6 +294,7 @@
+ #define PERF_EXTIRQ_CFG_REG_6358	0x14
+ #define PERF_EXTIRQ_CFG_REG_6362	0x18
+ #define PERF_EXTIRQ_CFG_REG_6368	0x18
++#define PERF_EXTIRQ_CFG_REG_63268	0x18
+ 
+ #define PERF_EXTIRQ_CFG_REG2_6368	0x1c
+ 
+@@ -273,6 +324,7 @@
+ #define PERF_SOFTRESET_6358_REG		0x34
+ #define PERF_SOFTRESET_6362_REG		0x10
+ #define PERF_SOFTRESET_6368_REG		0x10
++#define PERF_SOFTRESET_63268_REG	0x10
+ 
+ #define SOFTRESET_3368_SPI_MASK		(1 << 0)
+ #define SOFTRESET_3368_ENET_MASK	(1 << 2)
+@@ -366,6 +418,26 @@
+ #define SOFTRESET_6368_USBH_MASK	(1 << 12)
+ #define SOFTRESET_6368_PCM_MASK		(1 << 13)
+ 
++#define SOFTRESET_63268_SPI_MASK	(1 << 0)
++#define SOFTRESET_63268_IPSEC_MASK	(1 << 1)
++#define SOFTRESET_63268_EPHY_MASK	(1 << 2)
++#define SOFTRESET_63268_SAR_MASK	(1 << 3)
++#define SOFTRESET_63268_ENETSW_MASK	(1 << 4)
++#define SOFTRESET_63268_USBS_MASK	(1 << 5)
++#define SOFTRESET_63268_USBH_MASK	(1 << 6)
++#define SOFTRESET_63268_PCM_MASK	(1 << 7)
++#define SOFTRESET_63268_PCIE_CORE_MASK	(1 << 8)
++#define SOFTRESET_63268_PCIE_MASK	(1 << 9)
++#define SOFTRESET_63268_PCIE_EXT_MASK	(1 << 10)
++#define SOFTRESET_63268_WLAN_SHIM_MASK	(1 << 11)
++#define SOFTRESET_63268_DDR_PHY_MASK	(1 << 12)
++#define SOFTRESET_63268_FAP0_MASK	(1 << 13)
++#define SOFTRESET_63268_WLAN_UBUS_MASK	(1 << 14)
++#define SOFTRESET_63268_DECT_MASK	(1 << 15)
++#define SOFTRESET_63268_FAP1_MASK	(1 << 16)
++#define SOFTRESET_63268_PCIE_HARD_MASK	(1 << 17)
++#define SOFTRESET_63268_GPHY_MASK	(1 << 18)
++
+ /* MIPS PLL control register */
+ #define PERF_MIPSPLLCTL_REG		0x34
+ #define MIPSPLLCTL_N1_SHIFT		20
+@@ -1499,6 +1571,13 @@
+ #define STRAPBUS_6362_BOOT_SEL_SERIAL	(1 << 15)
+ #define STRAPBUS_6362_BOOT_SEL_NAND	(0 << 15)
+ 
++#define MISC_STRAPBUS_63268_REG		0x14
++#define STRAPBUS_63268_HSSPI_CLK_FAST	(1 << 9)
++#define STRAPBUS_63268_BOOT_SEL_SERIAL	(1 << 11)
++#define STRAPBUS_63268_BOOT_SEL_NAND	(0 << 11)
++#define STRAPBUS_63268_FCVO_SHIFT	21
++#define STRAPBUS_63268_FCVO_MASK	(0xf << STRAPBUS_63268_FCVO_SHIFT)
++
+ #define MISC_STRAPBUS_6328_REG		0x240
+ #define STRAPBUS_6328_FCVO_SHIFT	7
+ #define STRAPBUS_6328_FCVO_MASK		(0x1f << STRAPBUS_6328_FCVO_SHIFT)
+--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+@@ -25,6 +25,7 @@ static inline int is_bcm63xx_internal_re
+ 	case BCM6328_CPU_ID:
+ 	case BCM6362_CPU_ID:
+ 	case BCM6368_CPU_ID:
++	case BCM63268_CPU_ID:
+ 		if (offset >= 0xb0000000 && offset < 0xb1000000)
+ 			return 1;
+ 		break;
diff --git a/target/linux/brcm63xx/patches-3.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch
new file mode 100644
index 0000000000..4e8a090791
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch
@@ -0,0 +1,55 @@
+From 5c290c81dbdb4433600593fe80c88eb4af86e791 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 8 Dec 2013 03:22:40 +0100
+Subject: [PATCH 50/53] MIPS: BCM63XX: add pcie support for BCM63268
+
+---
+ arch/mips/bcm63xx/reset.c                       | 3 ++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 5 +++++
+ arch/mips/pci/pci-bcm63xx.c                     | 4 ++++
+ 3 files changed, 11 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -136,7 +136,8 @@
+ #define BCM63268_RESET_PCM	SOFTRESET_63268_PCM_MASK
+ #define BCM63268_RESET_MPI	0
+ #define BCM63268_RESET_PCIE	(SOFTRESET_63268_PCIE_MASK | \
+-				 SOFTRESET_63268_PCIE_CORE_MASK)
++				 SOFTRESET_63268_PCIE_CORE_MASK | \
++				 SOFTRESET_63268_PCIE_HARD_MASK)
+ #define BCM63268_RESET_PCIE_EXT	SOFTRESET_63268_PCIE_EXT_MASK
+ 
+ /*
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -45,6 +45,11 @@
+ #define BCM_PCIE_MEM_END_PA_6328	(BCM_PCIE_MEM_BASE_PA_6328 +	\
+ 					BCM_PCIE_MEM_SIZE_6328 - 1)
+ 
++#define BCM_PCIE_MEM_BASE_PA_63268	0x11000000
++#define BCM_PCIE_MEM_SIZE_63268		(15 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA_63268	(BCM_PCIE_MEM_BASE_PA_63268 +	\
++					BCM_PCIE_MEM_SIZE_63268 - 1)
++
+ /*
+  * Internal registers are accessed through KSEG3
+  */
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -337,11 +337,15 @@ static int __init bcm63xx_pci_init(void)
+ 	if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
+ 		bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
+ 		bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
++	} else if (BCMCPU_IS_63268()) {
++		bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_63268;
++		bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_63268;
+ 	}
+ 
+ 	switch (bcm63xx_get_cpu_id()) {
+ 	case BCM6328_CPU_ID:
+ 	case BCM6362_CPU_ID:
++	case BCM63268_CPU_ID:
+ 		return bcm63xx_register_pcie();
+ 	case BCM3368_CPU_ID:
+ 	case BCM6348_CPU_ID:
diff --git a/target/linux/brcm63xx/patches-3.10/403-6358-enet1-external-mii-clk.patch b/target/linux/brcm63xx/patches-3.10/403-6358-enet1-external-mii-clk.patch
index b40eaff5bf..c84af56ba9 100644
--- a/target/linux/brcm63xx/patches-3.10/403-6358-enet1-external-mii-clk.patch
+++ b/target/linux/brcm63xx/patches-3.10/403-6358-enet1-external-mii-clk.patch
@@ -11,7 +11,7 @@
  	bcm_gpio_writel(val, GPIO_MODE_REG);
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -623,6 +623,8 @@
+@@ -695,6 +695,8 @@
  #define GPIO_MODE_6358_EXTRA_SPI_SS	(1 << 7)
  #define GPIO_MODE_6358_SERIAL_LED	(1 << 10)
  #define GPIO_MODE_6358_UTOPIA		(1 << 12)
diff --git a/target/linux/brcm63xx/patches-3.10/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch b/target/linux/brcm63xx/patches-3.10/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch
index 4a3ee4ce4f..0d69d98121 100644
--- a/target/linux/brcm63xx/patches-3.10/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch
+++ b/target/linux/brcm63xx/patches-3.10/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch
@@ -10,7 +10,7 @@ Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports
 
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -933,6 +933,19 @@
+@@ -1005,6 +1005,19 @@
  #define ENETSW_PORTOV_FDX_MASK		(1 << 1)
  #define ENETSW_PORTOV_LINKUP_MASK	(1 << 0)
  
diff --git a/target/linux/brcm63xx/patches-3.10/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch b/target/linux/brcm63xx/patches-3.10/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
index cdaae990aa..1c2f1b52f1 100644
--- a/target/linux/brcm63xx/patches-3.10/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
+++ b/target/linux/brcm63xx/patches-3.10/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
@@ -58,7 +58,18 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  		if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
  			return BCM63XX_FLASH_TYPE_SERIAL;
  		else
-@@ -86,6 +109,9 @@ static int __init bcm63xx_detect_flash_t
+@@ -80,12 +103,20 @@ static int __init bcm63xx_detect_flash_t
+ 			return BCM63XX_FLASH_TYPE_SERIAL;
+ 	case BCM6362_CPU_ID:
+ 		val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
++		if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
++			bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
++		else
++			bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
++
+ 		if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
+ 			return BCM63XX_FLASH_TYPE_SERIAL;
+ 		else
  			return BCM63XX_FLASH_TYPE_NAND;
  	case BCM6368_CPU_ID:
  		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
@@ -68,13 +79,25 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  		switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
  		case STRAPBUS_6368_BOOT_SEL_NAND:
  			return BCM63XX_FLASH_TYPE_NAND;
-@@ -117,8 +143,14 @@ int __init bcm63xx_flash_register(void)
+@@ -96,6 +127,11 @@ static int __init bcm63xx_detect_flash_t
+ 		}
+ 	case BCM63268_CPU_ID:
+ 		val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
++		if (val & STRAPBUS_63268_HSSPI_CLK_FAST)
++			bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
++		else
++			bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
++
+ 		if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
+ 			return BCM63XX_FLASH_TYPE_SERIAL;
+ 		else
+@@ -123,8 +159,14 @@ int __init bcm63xx_flash_register(void)
  
  		return platform_device_register(&mtd_dev);
  	case BCM63XX_FLASH_TYPE_SERIAL:
 -		pr_warn("unsupported serial flash detected\n");
 -		return -ENODEV;
-+		if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
++		if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
 +			bcm63xx_spi_flash_info[0].bus_num = 1;
 +
 +		if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
@@ -87,7 +110,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  		return -ENODEV;
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -674,6 +674,7 @@
+@@ -746,6 +746,7 @@
  #define GPIO_STRAPBUS_REG		0x40
  #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
  #define STRAPBUS_6358_BOOT_SEL_SERIAL	(0 << 1)
@@ -95,8 +118,8 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  #define STRAPBUS_6368_BOOT_SEL_MASK	0x3
  #define STRAPBUS_6368_BOOT_SEL_NAND	0
  #define STRAPBUS_6368_BOOT_SEL_SERIAL	1
-@@ -1515,6 +1516,7 @@
- #define STRAPBUS_6362_BOOT_SEL_NAND	(0 << 15)
+@@ -1594,6 +1595,7 @@
+ #define STRAPBUS_63268_FCVO_MASK	(0xf << STRAPBUS_63268_FCVO_SHIFT)
  
  #define MISC_STRAPBUS_6328_REG		0x240
 +#define STRAPBUS_6328_HSSPI_CLK_FAST	(1 << 4)
diff --git a/target/linux/brcm63xx/patches-3.10/415-MIPS-BCM63XX-store-the-flash-type-in-global-variable.patch b/target/linux/brcm63xx/patches-3.10/415-MIPS-BCM63XX-store-the-flash-type-in-global-variable.patch
index e7f8bf0f27..18f60332f5 100644
--- a/target/linux/brcm63xx/patches-3.10/415-MIPS-BCM63XX-store-the-flash-type-in-global-variable.patch
+++ b/target/linux/brcm63xx/patches-3.10/415-MIPS-BCM63XX-store-the-flash-type-in-global-variable.patch
@@ -19,7 +19,7 @@ Subject: [PATCH 38/59] MIPS: BCM63XX: store the flash type in global variable
  static struct mtd_partition mtd_partitions[] = {
  	{
  		.name		= "cfe",
-@@ -86,27 +88,31 @@ static int __init bcm63xx_detect_flash_t
+@@ -86,21 +88,24 @@ static int __init bcm63xx_detect_flash_t
  			bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
  
  		if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
@@ -48,6 +48,10 @@ Subject: [PATCH 38/59] MIPS: BCM63XX: store the flash type in global variable
 +		break;
  	case BCM6362_CPU_ID:
  		val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
+ 		if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
+@@ -109,9 +114,10 @@ static int __init bcm63xx_detect_flash_t
+ 			bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
+ 
  		if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
 -			return BCM63XX_FLASH_TYPE_SERIAL;
 +			bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_SERIAL;
@@ -58,7 +62,7 @@ Subject: [PATCH 38/59] MIPS: BCM63XX: store the flash type in global variable
  	case BCM6368_CPU_ID:
  		val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
  		if (val & STRAPBUS_6368_SPI_CLK_FAST)
-@@ -114,25 +120,32 @@ static int __init bcm63xx_detect_flash_t
+@@ -119,11 +125,16 @@ static int __init bcm63xx_detect_flash_t
  
  		switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
  		case STRAPBUS_6368_BOOT_SEL_NAND:
@@ -76,6 +80,17 @@ Subject: [PATCH 38/59] MIPS: BCM63XX: store the flash type in global variable
 +		default:
 +			return -EINVAL;
  		}
+ 	case BCM63268_CPU_ID:
+ 		val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
+@@ -133,22 +144,24 @@ static int __init bcm63xx_detect_flash_t
+ 			bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
+ 
+ 		if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
+-			return BCM63XX_FLASH_TYPE_SERIAL;
++			bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_SERIAL;
+ 		else
+-			return BCM63XX_FLASH_TYPE_NAND;
++			bcm63xx_attached_flash = BCM63XX_FLASH_TYPE_NAND;
  	default:
  		return -EINVAL;
  	}
@@ -97,7 +112,7 @@ Subject: [PATCH 38/59] MIPS: BCM63XX: store the flash type in global variable
  	case BCM63XX_FLASH_TYPE_PARALLEL:
  		/* read base address of boot chip select (0) */
  		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-@@ -156,7 +169,7 @@ int __init bcm63xx_flash_register(void)
+@@ -172,7 +185,7 @@ int __init bcm63xx_flash_register(void)
  		return -ENODEV;
  	default:
  		pr_err("flash detection failed for BCM%x: %d\n",
diff --git a/target/linux/brcm63xx/patches-3.10/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch b/target/linux/brcm63xx/patches-3.10/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch
index 5977a43b58..5a3c9f0914 100644
--- a/target/linux/brcm63xx/patches-3.10/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch
+++ b/target/linux/brcm63xx/patches-3.10/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch
@@ -144,7 +144,7 @@ Subject: [PATCH 61/72] BCM63XX: add a fixup for ath9k devices
 +
 +	switch (bcm63xx_get_cpu_id()) {
 +	case BCM6328_CPU_ID:
-+		val = BCM_PCIE_MEM_BASE_PA;
++		val = BCM_PCIE_MEM_BASE_PA_6328;
 +		break;
 +	case BCM6348_CPU_ID:
 +	case BCM6358_CPU_ID:
diff --git a/target/linux/brcm63xx/patches-3.10/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch b/target/linux/brcm63xx/patches-3.10/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch
index 79b7d6c48a..6f5b0cedc0 100644
--- a/target/linux/brcm63xx/patches-3.10/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch
+++ b/target/linux/brcm63xx/patches-3.10/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch
@@ -46,7 +46,7 @@ Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash
  };
  
  static struct spi_board_info bcm63xx_spi_flash_info[] = {
-@@ -138,10 +142,13 @@ static int __init bcm63xx_detect_flash_t
+@@ -154,10 +158,13 @@ static int __init bcm63xx_detect_flash_t
  	return 0;
  }
  
diff --git a/target/linux/brcm63xx/patches-3.10/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch b/target/linux/brcm63xx/patches-3.10/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch
index 062a871260..851ab2850b 100644
--- a/target/linux/brcm63xx/patches-3.10/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch
+++ b/target/linux/brcm63xx/patches-3.10/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch
@@ -61,7 +61,7 @@ Subject: [PATCH 72/72] 446-BCM63XX-add-a-fixup-for-rt2x00-devices
  }
 --- a/arch/mips/bcm63xx/dev-flash.c
 +++ b/arch/mips/bcm63xx/dev-flash.c
-@@ -142,7 +142,7 @@ static int __init bcm63xx_detect_flash_t
+@@ -158,7 +158,7 @@ static int __init bcm63xx_detect_flash_t
  	return 0;
  }
  
diff --git a/target/linux/brcm63xx/patches-3.10/511-board_V2500V.patch b/target/linux/brcm63xx/patches-3.10/511-board_V2500V.patch
index d0b33803e8..2dfe772681 100644
--- a/target/linux/brcm63xx/patches-3.10/511-board_V2500V.patch
+++ b/target/linux/brcm63xx/patches-3.10/511-board_V2500V.patch
@@ -107,7 +107,7 @@
  #include <bcm63xx_cpu.h>
  #include <bcm63xx_dev_flash.h>
  #include <bcm63xx_dev_hsspi.h>
-@@ -158,6 +159,13 @@ int __init bcm63xx_flash_register(int nu
+@@ -174,6 +175,13 @@ int __init bcm63xx_flash_register(int nu
  		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
  		val &= MPI_CSBASE_BASE_MASK;