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author | Jonas Gorski <jogo@openwrt.org> | 2015-06-22 12:28:46 +0000 |
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committer | Jonas Gorski <jogo@openwrt.org> | 2015-06-22 12:28:46 +0000 |
commit | bd398e1765ebd21024f6ceb303a78c9de79104e8 (patch) | |
tree | 60e6b748e6d51b6eb97623a2007dcd5b38b37e52 /target/linux/brcm63xx/patches-4.1/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch | |
parent | a0c49ef46f7caf5eb02c635d446218201008ecff (diff) | |
download | upstream-bd398e1765ebd21024f6ceb303a78c9de79104e8.tar.gz upstream-bd398e1765ebd21024f6ceb303a78c9de79104e8.tar.bz2 upstream-bd398e1765ebd21024f6ceb303a78c9de79104e8.zip |
brcm63xx: add kernel 4.1 support
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 46113
Diffstat (limited to 'target/linux/brcm63xx/patches-4.1/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch')
-rw-r--r-- | target/linux/brcm63xx/patches-4.1/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-4.1/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch b/target/linux/brcm63xx/patches-4.1/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch new file mode 100644 index 0000000000..2f2eecf38c --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch @@ -0,0 +1,53 @@ +From d8237d704fc25eb2fc25ef4403608b78c6a6d4be Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jonas.gorski@gmail.com> +Date: Sun, 15 Jul 2012 20:08:57 +0200 +Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports + +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 13 +++++++++++++ + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 12 ++++++++++++ + 2 files changed, 25 insertions(+), 0 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -967,6 +967,19 @@ + #define ENETSW_PORTOV_FDX_MASK (1 << 1) + #define ENETSW_PORTOV_LINKUP_MASK (1 << 0) + ++/* Port RGMII control register */ ++#define ENETSW_RGMII_CTRL_REG(x) (0x60 + (x)) ++#define ENETSW_RGMII_CTRL_GMII_CLK_EN (1 << 7) ++#define ENETSW_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6) ++#define ENETSW_RGMII_CTRL_MII_MODE_MASK (3 << 4) ++#define ENETSW_RGMII_CTRL_RGMII_MODE (0 << 4) ++#define ENETSW_RGMII_CTRL_MII_MODE (1 << 4) ++#define ENETSW_RGMII_CTRL_RVMII_MODE (2 << 4) ++#define ENETSW_RGMII_CTRL_TIMING_SEL_EN (1 << 0) ++ ++/* Port RGMII timing register */ ++#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x)) ++ + /* MDIO control register */ + #define ENETSW_MDIOC_REG (0xb0) + #define ENETSW_MDIOC_EXT_MASK (1 << 16) +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2225,6 +2225,18 @@ static int bcm_enetsw_open(struct net_de + priv->sw_port_link[i] = 0; + } + ++ /* enable external ports */ ++ for (i = ENETSW_RGMII_PORT0; i < priv->num_ports; i++) { ++ u8 rgmii_ctrl; ++ ++ if (!priv->used_ports[i].used) ++ continue; ++ ++ rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i)); ++ rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN; ++ enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); ++ } ++ + /* reset mib */ + val = enetsw_readb(priv, ENETSW_GMCR_REG); + val |= ENETSW_GMCR_RST_MIB_MASK; |