aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch
diff options
context:
space:
mode:
authorJonas Gorski <jogo@openwrt.org>2015-06-22 12:28:46 +0000
committerJonas Gorski <jogo@openwrt.org>2015-06-22 12:28:46 +0000
commitbd398e1765ebd21024f6ceb303a78c9de79104e8 (patch)
tree60e6b748e6d51b6eb97623a2007dcd5b38b37e52 /target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch
parenta0c49ef46f7caf5eb02c635d446218201008ecff (diff)
downloadupstream-bd398e1765ebd21024f6ceb303a78c9de79104e8.tar.gz
upstream-bd398e1765ebd21024f6ceb303a78c9de79104e8.tar.bz2
upstream-bd398e1765ebd21024f6ceb303a78c9de79104e8.zip
brcm63xx: add kernel 4.1 support
Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 46113
Diffstat (limited to 'target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch')
-rw-r--r--target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch63
1 files changed, 63 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch b/target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch
new file mode 100644
index 0000000000..2b19600776
--- /dev/null
+++ b/target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch
@@ -0,0 +1,63 @@
+From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 22 Dec 2013 13:25:25 +0100
+Subject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot
+
+Some bootloaders leave the flash access in an invalid state with dual
+read enabled; fix it by disabling it and falling back to simple fast
+reads.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/dev-flash.c | 36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -110,9 +110,46 @@ static int __init bcm63xx_detect_flash_t
+ }
+ }
+
++#define HSSPI_FLASH_CTRL_REG 0x14
++#define FLASH_CTRL_READ_OPCODE_MASK 0xff
++#define FLASH_CTRL_ADDR_BYTES_MASK (0x3 << 8)
++#define FLASH_CTRL_ADDR_BYTES_2 (0 << 8)
++#define FLASH_CTRL_ADDR_BYTES_3 (1 << 8)
++#define FLASH_CTRL_ADDR_BYTES_4 (2 << 8)
++#define FLASH_CTRL_MB_EN (1 << 23)
++
+ void __init bcm63xx_flash_detect(void)
+ {
+ flash_type = bcm63xx_detect_flash_type();
++
++ /* reduce flash mapping to single i/o reads for safety */
++ if (flash_type == BCM63XX_FLASH_TYPE_SERIAL &&
++ (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
++ BCMCPU_IS_63268())) {
++ u32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG);
++
++ if (!(val & FLASH_CTRL_MB_EN))
++ return;
++
++ val &= ~FLASH_CTRL_MB_EN;
++ val &= ~FLASH_CTRL_READ_OPCODE_MASK;
++
++ switch (val & FLASH_CTRL_ADDR_BYTES_MASK) {
++ case FLASH_CTRL_ADDR_BYTES_3:
++ val |= 0x0b; /* OPCODE_FAST_READ */
++ break;
++ case FLASH_CTRL_ADDR_BYTES_4:
++ val |= 0x0c; /* OPCODE_FAST_READ_4B */
++ break;
++ case FLASH_CTRL_ADDR_BYTES_2:
++ default:
++ pr_warn("unsupported address byte mode (%x), not fixing up\n",
++ val & FLASH_CTRL_ADDR_BYTES_MASK);
++ return;
++ }
++
++ bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG);
++ }
+ }
+
+ int __init bcm63xx_flash_register(void)