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| author | Jonas Gorski <jogo@openwrt.org> | 2013-02-04 10:19:50 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2013-02-04 10:19:50 +0000 |
| commit | 3b4fced67dad0b733d77f78205cfecfc0d654695 (patch) | |
| tree | a672ce6b4f937cdff5c23c4d96583c95c6357b9e /target/linux/brcm63xx/patches-3.7/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch | |
| parent | 0e9365b3462d456baba85cad7269c85b0d0f7d8a (diff) | |
| download | upstream-3b4fced67dad0b733d77f78205cfecfc0d654695.tar.gz upstream-3b4fced67dad0b733d77f78205cfecfc0d654695.tar.bz2 upstream-3b4fced67dad0b733d77f78205cfecfc0d654695.zip | |
bcm63xx: add support for linux 3.7
Based on 3.7.6.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 35481
Diffstat (limited to 'target/linux/brcm63xx/patches-3.7/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.7/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.7/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch b/target/linux/brcm63xx/patches-3.7/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch new file mode 100644 index 0000000000..d18633a475 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.7/030-MIPS-BCM63XX-Fix-BCM6345-clock-bits.patch @@ -0,0 +1,35 @@ +From: Florian Fainelli <florian@openwrt.org> +Subject: [PATCH] MIPS: BCM63XX: fix BCM6345 clock bits shifting + +BCM6345 has an intermediate 16-bits wide test control register between the +peripheral identifier function, and its clock control register is only 16-bits +wide contrary to other platforms where it is 32-bits wide. By shifting all +clocks bits by 16-bits to the left we ensure they get written to the proper +clock control register, without adding specific BCM6345 handling in the clock +code. + +Signed-off-by: Florian Fainelli <florian@openwrt.org> +--- +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -53,13 +53,13 @@ + CKCTL_6338_SAR_EN | \ + CKCTL_6338_SPI_EN) + +-#define CKCTL_6345_CPU_EN (1 << 0) +-#define CKCTL_6345_BUS_EN (1 << 1) +-#define CKCTL_6345_EBI_EN (1 << 2) +-#define CKCTL_6345_UART_EN (1 << 3) +-#define CKCTL_6345_ADSLPHY_EN (1 << 4) +-#define CKCTL_6345_ENET_EN (1 << 7) +-#define CKCTL_6345_USBH_EN (1 << 8) ++#define CKCTL_6345_CPU_EN (1 << 16) ++#define CKCTL_6345_BUS_EN (1 << 17) ++#define CKCTL_6345_EBI_EN (1 << 18) ++#define CKCTL_6345_UART_EN (1 << 19) ++#define CKCTL_6345_ADSLPHY_EN (1 << 20) ++#define CKCTL_6345_ENET_EN (1 << 23) ++#define CKCTL_6345_USBH_EN (1 << 24) + + #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ + CKCTL_6345_USBH_EN | \ |