bcm63xx: replace SPI driver with latest upstream version

SVN-Revision: 31130

1 files changed, 93 insertions, 0 deletions

diff --git a/target/linux/brcm63xx/patches-3.3/002-MIPS-BCM63XX-be-consistent-in-clock-bits-enable-nami.patch b/target/linux/brcm63xx/patches-3.3/002-MIPS-BCM63XX-be-consistent-in-clock-bits-enable-nami.patch
new file mode 100644
index 0000000000..439d11ea1d
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.3/002-MIPS-BCM63XX-be-consistent-in-clock-bits-enable-nami.patch
@@ -0,0 +1,93 @@
+From db1cc4ee366bf0528fcb8b4afa65dec915d98889 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Wed, 25 Jan 2012 17:39:55 +0100
+Subject: [PATCH 04/63] MIPS: BCM63XX: be consistent in clock bits enable naming
+
+Remove the _CLK suffix from the BCM6368 clock bits definitions to be
+consistent with what is already present.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/clk.c                           |    6 ++--
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   36 ++++++++++----------
+ 2 files changed, 21 insertions(+), 21 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk,
+ {
+ 	if (!BCMCPU_IS_6368())
+ 		return;
+-	bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
++	bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
+ 			CKCTL_6368_SWPKT_USB_EN |
+ 			CKCTL_6368_SWPKT_SAR_EN, enable);
+ 	if (enable) {
+@@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, in
+ 	if (BCMCPU_IS_6348())
+ 		bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+ 	else if (BCMCPU_IS_6368())
+-		bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
++		bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
+ }
+ 
+ static struct clk clk_usbh = {
+@@ -199,7 +199,7 @@ static void xtm_set(struct clk *clk, int
+ 	if (!BCMCPU_IS_6368())
+ 		return;
+ 
+-	bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
++	bcm_hwclock_set(CKCTL_6368_SAR_EN |
+ 			CKCTL_6368_SWPKT_SAR_EN, enable);
+ 
+ 	if (enable) {
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -90,29 +90,29 @@
+ #define CKCTL_6368_PHYMIPS_EN		(1 << 6)
+ #define CKCTL_6368_SWPKT_USB_EN		(1 << 7)
+ #define CKCTL_6368_SWPKT_SAR_EN		(1 << 8)
+-#define CKCTL_6368_SPI_CLK_EN		(1 << 9)
+-#define CKCTL_6368_USBD_CLK_EN		(1 << 10)
+-#define CKCTL_6368_SAR_CLK_EN		(1 << 11)
+-#define CKCTL_6368_ROBOSW_CLK_EN	(1 << 12)
+-#define CKCTL_6368_UTOPIA_CLK_EN	(1 << 13)
+-#define CKCTL_6368_PCM_CLK_EN		(1 << 14)
+-#define CKCTL_6368_USBH_CLK_EN		(1 << 15)
++#define CKCTL_6368_SPI_EN		(1 << 9)
++#define CKCTL_6368_USBD_EN		(1 << 10)
++#define CKCTL_6368_SAR_EN		(1 << 11)
++#define CKCTL_6368_ROBOSW_EN		(1 << 12)
++#define CKCTL_6368_UTOPIA_EN		(1 << 13)
++#define CKCTL_6368_PCM_EN		(1 << 14)
++#define CKCTL_6368_USBH_EN		(1 << 15)
+ #define CKCTL_6368_DISABLE_GLESS_EN	(1 << 16)
+-#define CKCTL_6368_NAND_CLK_EN		(1 << 17)
+-#define CKCTL_6368_IPSEC_CLK_EN		(1 << 17)
++#define CKCTL_6368_NAND_EN		(1 << 17)
++#define CKCTL_6368_IPSEC_EN		(1 << 17)
+ 
+ #define CKCTL_6368_ALL_SAFE_EN		(CKCTL_6368_SWPKT_USB_EN |	\
+ 					CKCTL_6368_SWPKT_SAR_EN |	\
+-					CKCTL_6368_SPI_CLK_EN |		\
+-					CKCTL_6368_USBD_CLK_EN |	\
+-					CKCTL_6368_SAR_CLK_EN |		\
+-					CKCTL_6368_ROBOSW_CLK_EN |	\
+-					CKCTL_6368_UTOPIA_CLK_EN |	\
+-					CKCTL_6368_PCM_CLK_EN |		\
+-					CKCTL_6368_USBH_CLK_EN |	\
++					CKCTL_6368_SPI_EN |		\
++					CKCTL_6368_USBD_EN |		\
++					CKCTL_6368_SAR_EN |		\
++					CKCTL_6368_ROBOSW_EN |		\
++					CKCTL_6368_UTOPIA_EN |		\
++					CKCTL_6368_PCM_EN |		\
++					CKCTL_6368_USBH_EN |		\
+ 					CKCTL_6368_DISABLE_GLESS_EN |	\
+-					CKCTL_6368_NAND_CLK_EN |	\
+-					CKCTL_6368_IPSEC_CLK_EN)
++					CKCTL_6368_NAND_EN |		\
++					CKCTL_6368_IPSEC_EN)
+ 
+ /* System PLL Control register  */
+ #define PERF_SYS_PLL_CTL_REG		0x8