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authorJonas Gorski <jogo@openwrt.org>2014-02-24 15:54:12 +0000
committerJonas Gorski <jogo@openwrt.org>2014-02-24 15:54:12 +0000
commit0d120f42daa76a299219ce56ac8c3b273d59840c (patch)
tree52d739635e27535ccd5f4b7784dd718f28a59a52 /target/linux/brcm63xx/patches-3.13/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch
parent8ffe7e9d41f86a4a941292bb8d3e637e6ae03be9 (diff)
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brcm63xx: add preliminary support for 3.13
Add support for 3.13 as a development kernel. Mostly untested, only net booted. If flashed may brick your router or kill your cat. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39746
Diffstat (limited to 'target/linux/brcm63xx/patches-3.13/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch')
-rw-r--r--target/linux/brcm63xx/patches-3.13/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch70
1 files changed, 70 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.13/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch b/target/linux/brcm63xx/patches-3.13/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch
new file mode 100644
index 0000000000..1b8921cbf2
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.13/323-MIPS-BCM63XX-add-pin-argument-to-dispatch-internal.patch
@@ -0,0 +1,70 @@
+From a33bb660c712447ba8b561109cda6734954a6efa Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Fri, 26 Apr 2013 11:21:16 +0200
+Subject: [PATCH 34/53] MIPS: BCM63XX: add pin argument to dispatch internal
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c | 18 ++++++++++--------
+ 1 file changed, 10 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -19,9 +19,10 @@
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_irq.h>
+
++
+ static u32 irq_stat_addr[2];
+ static u32 irq_mask_addr[2];
+-static void (*dispatch_internal)(void);
++static void (*dispatch_internal)(int pin);
+ static int is_ext_irq_cascaded;
+ static unsigned int ext_irq_count;
+ static unsigned int ext_irq_start, ext_irq_end;
+@@ -54,19 +55,20 @@ static inline void handle_internal(int i
+ */
+
+ #define BUILD_IPIC_INTERNAL(width) \
+-void __dispatch_internal_##width(void) \
++void __dispatch_internal_##width(int pin) \
+ { \
+ u32 pending[width / 32]; \
+ unsigned int src, tgt; \
+ bool irqs_pending = false; \
+- static int i; \
++ static int i[2]; \
++ int *next = &i[pin]; \
+ \
+ /* read registers in reverse order */ \
+ for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
+ u32 val; \
+ \
+- val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \
+- val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
++ val = bcm_readl(irq_stat_addr[pin] + src * sizeof(u32)); \
++ val &= bcm_readl(irq_mask_addr[pin] + src * sizeof(u32)); \
+ pending[--tgt] = val; \
+ \
+ if (val) \
+@@ -77,9 +79,9 @@ void __dispatch_internal_##width(void)
+ return; \
+ \
+ while (1) { \
+- int to_call = i; \
++ int to_call = *next; \
+ \
+- i = (i + 1) & (width - 1); \
++ *next = (*next + 1) & (width - 1); \
+ if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
+ handle_internal(to_call); \
+ break; \
+@@ -129,7 +131,7 @@ asmlinkage void plat_irq_dispatch(void)
+ if (cause & CAUSEF_IP1)
+ do_IRQ(1);
+ if (cause & CAUSEF_IP2)
+- dispatch_internal();
++ dispatch_internal(0);
+ if (!is_ext_irq_cascaded) {
+ if (cause & CAUSEF_IP3)
+ do_IRQ(IRQ_EXT_0);