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authorJonas Gorski <jogo@openwrt.org>2014-01-13 12:13:51 +0000
committerJonas Gorski <jogo@openwrt.org>2014-01-13 12:13:51 +0000
commit3bdcf040aa47638a1e398d8a6329f515f1cc015a (patch)
tree6b01a0ff5511d7d11db063ed4dfe6e1628194813 /target/linux/brcm63xx/patches-3.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch
parentab8897045cd4bcc547af02c3660f29cceb40e952 (diff)
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brcm63xx: add initial support for BCM63268
Add initial support for the BCM63268 family of SoCs, but keep it disabled for now as most things don't work yet. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39271
Diffstat (limited to 'target/linux/brcm63xx/patches-3.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch')
-rw-r--r--target/linux/brcm63xx/patches-3.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch55
1 files changed, 55 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch
new file mode 100644
index 0000000000..4e8a090791
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch
@@ -0,0 +1,55 @@
+From 5c290c81dbdb4433600593fe80c88eb4af86e791 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 8 Dec 2013 03:22:40 +0100
+Subject: [PATCH 50/53] MIPS: BCM63XX: add pcie support for BCM63268
+
+---
+ arch/mips/bcm63xx/reset.c | 3 ++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 5 +++++
+ arch/mips/pci/pci-bcm63xx.c | 4 ++++
+ 3 files changed, 11 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -136,7 +136,8 @@
+ #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK
+ #define BCM63268_RESET_MPI 0
+ #define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \
+- SOFTRESET_63268_PCIE_CORE_MASK)
++ SOFTRESET_63268_PCIE_CORE_MASK | \
++ SOFTRESET_63268_PCIE_HARD_MASK)
+ #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK
+
+ /*
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+@@ -45,6 +45,11 @@
+ #define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \
+ BCM_PCIE_MEM_SIZE_6328 - 1)
+
++#define BCM_PCIE_MEM_BASE_PA_63268 0x11000000
++#define BCM_PCIE_MEM_SIZE_63268 (15 * 1024 * 1024)
++#define BCM_PCIE_MEM_END_PA_63268 (BCM_PCIE_MEM_BASE_PA_63268 + \
++ BCM_PCIE_MEM_SIZE_63268 - 1)
++
+ /*
+ * Internal registers are accessed through KSEG3
+ */
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -337,11 +337,15 @@ static int __init bcm63xx_pci_init(void)
+ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
+ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
+ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
++ } else if (BCMCPU_IS_63268()) {
++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_63268;
++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_63268;
+ }
+
+ switch (bcm63xx_get_cpu_id()) {
+ case BCM6328_CPU_ID:
+ case BCM6362_CPU_ID:
++ case BCM63268_CPU_ID:
+ return bcm63xx_register_pcie();
+ case BCM3368_CPU_ID:
+ case BCM6348_CPU_ID: