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| author | Jonas Gorski <jogo@openwrt.org> | 2014-01-13 12:13:26 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2014-01-13 12:13:26 +0000 |
| commit | 76164e1a3659d623cbd8b704559bf6241521011f (patch) | |
| tree | ad57a442583a461ff7df57bd7f79bd83d74245d2 /target/linux/brcm63xx/patches-3.10/332-MIPS-BCM63XX-detect-bcm6328-variants.patch | |
| parent | db36359f48ffa15ecfc9d5285d47c09bb95e8fa8 (diff) | |
| download | upstream-76164e1a3659d623cbd8b704559bf6241521011f.tar.gz upstream-76164e1a3659d623cbd8b704559bf6241521011f.tar.bz2 upstream-76164e1a3659d623cbd8b704559bf6241521011f.zip | |
brcm63xx: add support for chip variants
Some SoCs have variants which are mostly the same, but use a different
chip id (or not). Add code for detecting them and handling them as
their standard counterparts.
This adds support for e.g. BCM6369.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 39269
Diffstat (limited to 'target/linux/brcm63xx/patches-3.10/332-MIPS-BCM63XX-detect-bcm6328-variants.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.10/332-MIPS-BCM63XX-detect-bcm6328-variants.patch | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.10/332-MIPS-BCM63XX-detect-bcm6328-variants.patch b/target/linux/brcm63xx/patches-3.10/332-MIPS-BCM63XX-detect-bcm6328-variants.patch new file mode 100644 index 0000000000..9962b1e593 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.10/332-MIPS-BCM63XX-detect-bcm6328-variants.patch @@ -0,0 +1,67 @@ +From 6c8d94aaf5e2f0a3327e4f69ccd980bd5617f925 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Sat, 7 Dec 2013 14:30:59 +0100 +Subject: [PATCH 42/53] MIPS: BCM63XX: detect bcm6328 variants + +--- + arch/mips/bcm63xx/cpu.c | 10 ++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++++-- + 2 files changed, 16 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -304,6 +304,7 @@ void __init bcm63xx_cpu_init(void) + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int cpu = smp_processor_id(); + u32 chipid_reg; ++ u8 varid; + + /* soc registers location depends on cpu type */ + chipid_reg = 0; +@@ -343,6 +344,7 @@ void __init bcm63xx_cpu_init(void) + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; + bcm63xx_cpu_variant = bcm63xx_cpu_id; + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; ++ varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; + + switch (bcm63xx_cpu_id) { + case BCM3368_CPU_ID: +@@ -352,6 +354,14 @@ void __init bcm63xx_cpu_init(void) + case BCM6328_CPU_ID: + bcm63xx_regs_base = bcm6328_regs_base; + bcm63xx_irqs = bcm6328_irqs; ++ ++ if (varid == 1) ++ bcm63xx_cpu_variant = BCM63281_CPU_ID; ++ else if (varid == 3) ++ bcm63xx_cpu_variant = BCM63283_CPU_ID; ++ else ++ pr_warn("unknown BCM6328 variant: %x\n", varid); ++ + break; + case BCM6338_CPU_ID: + bcm63xx_regs_base = bcm6338_regs_base; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -11,6 +11,8 @@ + */ + #define BCM3368_CPU_ID 0x3368 + #define BCM6328_CPU_ID 0x6328 ++#define BCM63281_CPU_ID 0x63281 ++#define BCM63283_CPU_ID 0x63283 + #define BCM6338_CPU_ID 0x6338 + #define BCM6345_CPU_ID 0x6345 + #define BCM6348_CPU_ID 0x6348 +@@ -85,8 +87,10 @@ static inline u16 __pure bcm63xx_get_cpu + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) +-#define BCMCPU_VARIANT_IS_6328() \ +- (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID) ++#define BCMCPU_VARIANT_IS_63281() \ ++ (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID) ++#define BCMCPU_VARIANT_IS_63283() \ ++ (bcm63xx_get_cpu_variant() == BCM63283_CPU_ID) + #define BCMCPU_VARIANT_IS_6338() \ + (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID) + #define BCMCPU_VARIANT_IS_6345() \ |