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| author | Florian Fainelli <florian@openwrt.org> | 2009-03-20 15:08:02 +0000 |
|---|---|---|
| committer | Florian Fainelli <florian@openwrt.org> | 2009-03-20 15:08:02 +0000 |
| commit | 0972ee5331eec00b2fbebfdd8b849d2bbc1a08eb (patch) | |
| tree | 9ce2e90d15bf66eeae7a703e8d0eafb893600410 /target/linux/brcm63xx/files/include | |
| parent | 08b7cbe44e178861cc6bbc11c83272363ae645e6 (diff) | |
| download | upstream-0972ee5331eec00b2fbebfdd8b849d2bbc1a08eb.tar.gz upstream-0972ee5331eec00b2fbebfdd8b849d2bbc1a08eb.tar.bz2 upstream-0972ee5331eec00b2fbebfdd8b849d2bbc1a08eb.zip | |
add support for bcm6345 SoC, needs testing
SVN-Revision: 14953
Diffstat (limited to 'target/linux/brcm63xx/files/include')
| -rw-r--r-- | target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h index 74e553f7da..2ad2c9dc99 100644 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h +++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h @@ -12,6 +12,7 @@ * arm mach-types) */ #define BCM6338_CPU_ID 0x6338 +#define BCM6345_CPU_ID 0x6345 #define BCM6348_CPU_ID 0x6348 #define BCM6358_CPU_ID 0x6358 @@ -33,6 +34,19 @@ unsigned int bcm63xx_get_cpu_freq(void); # define BCMCPU_IS_6338() (0) #endif +#ifdef CONFIG_BCM63XX_CPU_6345 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM6345_CPU_ID +# endif +# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) +#else +# define BCMCPU_IS_6345() (0) +#endif + #ifdef CONFIG_BCM63XX_CPU_6348 # ifdef bcm63xx_get_cpu_id # undef bcm63xx_get_cpu_id @@ -123,6 +137,15 @@ enum bcm63xx_regs_set { #define BCM_6338_MEMC_BASE (0xfffe3100) /* + * 6345 register sets base address + */ +#define BCM_6345_PERF_BASE (0xfffe0000) +#define BCM_6345_TIMER_BASE (0xfffe0200) +#define BCM_6345_WDT_BASE (0xfffe021c) +#define BCM_6345_UART0_BASE (0xfffe0300) +#define BCM_6345_GPIO_BASE (0xfffe0400) + +/* * 6348 register sets base address */ #define BCM_6348_DSL_LMEM_BASE (0xfff00000) @@ -204,6 +227,20 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) return BCM_6338_MEMC_BASE; } #endif +#ifdef CONFIG_BCM63XX_CPU_6345 + switch (set) { + case RSET_PERF: + return BCM_6345_PERF_BASE; + case RSET_TIMER: + return BCM_6345_TIMER_BASE; + case RSET_WDT: + return BCM_6345_WDT_BASE; + case RSET_UART0: + return BCM_6345_UART0_BASE; + case RSET_GPIO: + return BCM_6345_GPIO_BASE; + } +#endif #ifdef CONFIG_BCM63XX_CPU_6348 switch (set) { case RSET_DSL_LMEM: @@ -462,6 +499,17 @@ enum bcm63xx_irq { #define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) /* + * 6345 irqs + */ +#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) +#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) + +/* * 6348 irqs */ #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |