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author | Jonas Gorski <jogo@openwrt.org> | 2014-12-01 00:52:07 +0000 |
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committer | Jonas Gorski <jogo@openwrt.org> | 2014-12-01 00:52:07 +0000 |
commit | e8068f0b1b4e53559ae0c58910b8905bee9b61ab (patch) | |
tree | cf44e0daeb888e0b4c69d9bf8483088a05239b96 /target/linux/brcm63xx/dts/bcm6368.dtsi | |
parent | 443d730da80775f4e6740f947b447e0bffef3644 (diff) | |
download | upstream-e8068f0b1b4e53559ae0c58910b8905bee9b61ab.tar.gz upstream-e8068f0b1b4e53559ae0c58910b8905bee9b61ab.tar.bz2 upstream-e8068f0b1b4e53559ae0c58910b8905bee9b61ab.zip |
brcm63xx: register interrupt-controllers through DT when possible
Add the required nodes for the interrupt controllers and register
them through DT when a DTB is present.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 43457
Diffstat (limited to 'target/linux/brcm63xx/dts/bcm6368.dtsi')
-rw-r--r-- | target/linux/brcm63xx/dts/bcm6368.dtsi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/dts/bcm6368.dtsi b/target/linux/brcm63xx/dts/bcm6368.dtsi index 378f4fb5bf..dcbbdbfe81 100644 --- a/target/linux/brcm63xx/dts/bcm6368.dtsi +++ b/target/linux/brcm63xx/dts/bcm6368.dtsi @@ -24,6 +24,14 @@ }; }; + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + memory { device_type = "memory"; reg = <0 0>; }; ubus@10000000 { @@ -31,6 +39,40 @@ #size-cells = <1>; ranges; compatible = "simple-bus"; + + ext_intc0: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <20>, <21>, <22>, <23>; + }; + + ext_intc1: interrupt-controller@1000001c { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x1000001c 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <24>, <25>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l2-intc"; + reg = <0x10000020 0x10>, + <0x10000030 0x10>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; }; pflash: nor@18000000 { |