openwrt/upstream - upstream openwrt

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author	Hauke Mehrtens <hauke@hauke-m.de>	2012-08-22 21:54:06 +0000
committer	Hauke Mehrtens <hauke@hauke-m.de>	2012-08-22 21:54:06 +0000
commit	847afa343fce680e84bbfdfbf7890af3b7e62e75 (patch)
tree	49881bcc3c7d3a4bf29520c04312085d95c49cf9 /target/linux/brcm47xx/profiles/105-Broadcom-none.mk
parent	a2f82cf7ec59497dc2467ed57d837f0217ab48aa (diff)
download	upstream-847afa343fce680e84bbfdfbf7890af3b7e62e75.tar.gz upstream-847afa343fce680e84bbfdfbf7890af3b7e62e75.tar.bz2 upstream-847afa343fce680e84bbfdfbf7890af3b7e62e75.zip

update profiles

* add profile for BCM4705 based SoC using tg3 instead of b44 * remove redundant 105-Atheros.mk * reorder SVN-Revision: 33235

Diffstat (limited to 'target/linux/brcm47xx/profiles/105-Broadcom-none.mk')

-rw-r--r--

target/linux/brcm47xx/profiles/105-Broadcom-none.mk

1 files changed, 17 insertions, 0 deletions

/* * Copyright 2010 Tilera Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, version 2. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT. See the GNU General Public License for * more details. * */ /** * @file * * Support for invalidating bytes in the instruction cache. */ #ifndef __ARCH_ICACHE_H__ #define __ARCH_ICACHE_H__ #include <arch/chip.h> /** * Invalidate the instruction cache for the given range of memory. * * @param addr The start of memory to be invalidated. * @param size The number of bytes to be invalidated. * @param page_size The system's page size, e.g. getpagesize() in userspace. * This value must be a power of two no larger than the page containing * the code to be invalidated. If the value is smaller than the actual page * size, this function will still work, but may run slower than necessary. */ static __inline void invalidate_icache(const void* addr, unsigned long size, unsigned long page_size) { const unsigned long cache_way_size = CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC(); unsigned long max_useful_size; const char* start, *end; long num_passes; if (__builtin_expect(size == 0, 0)) return; #ifdef __tilegx__ /* Limit the number of bytes visited to avoid redundant iterations. */ max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size; /* No PA aliasing is possible, so one pass always suffices. */ num_passes = 1; #else /* Limit the number of bytes visited to avoid redundant iterations. */ max_useful_size = cache_way_size; /* * Compute how many passes we need (we'll treat 0 as if it were 1). * This works because we know the page size is a power of two. */ num_passes = cache_way_size >> __builtin_ctzl(page_size); #endif if (__builtin_expect(size > max_useful_size, 0)) size = max_useful_size; /* Locate the first and last bytes to be invalidated. */ start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE()); end = (const char*)addr + size - 1; __insn_mf(); do { const char* p; for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE()) __insn_icoh(p); start += page_size; end += page_size; } while (--num_passes > 0); __insn_drain(); } #endif /* __ARCH_ICACHE_H__ */


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