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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2011-06-28 19:33:50 +0000 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2011-06-28 19:33:50 +0000 |
| commit | 2af4f6f634492487a02685e2ad4184b98d574572 (patch) | |
| tree | e05afc7c9c7ad33cb4b5a12700eda8cdcbb4b198 /target/linux/brcm47xx/patches-3.0 | |
| parent | c5821c1a3a94060be1c38315bfdf122aee5567c1 (diff) | |
| download | upstream-2af4f6f634492487a02685e2ad4184b98d574572.tar.gz upstream-2af4f6f634492487a02685e2ad4184b98d574572.tar.bz2 upstream-2af4f6f634492487a02685e2ad4184b98d574572.zip | |
kernel: update ssb and bcma to linux-next next-20110628
SVN-Revision: 27299
Diffstat (limited to 'target/linux/brcm47xx/patches-3.0')
| -rw-r--r-- | target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch b/target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch deleted file mode 100644 index fe6507b8de..0000000000 --- a/target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 974353557959d8ec1c022511cd1b3eeaa7ed482a Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens <hauke@hauke-m.de> -Date: Sat, 4 Jun 2011 15:55:24 +0200 -Subject: [PATCH 15/15] ssb: fix ssb clock rate according to broadcom source - -This fix was done according to si_clock_rate function in broadcom siutils.c - -Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> ---- - drivers/ssb/main.c | 4 ++-- - 1 files changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/ssb/main.c -+++ b/drivers/ssb/main.c -@@ -1002,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 - switch (plltype) { - case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ - if (m & SSB_CHIPCO_CLK_T6_MMASK) -- return SSB_CHIPCO_CLK_T6_M0; -- return SSB_CHIPCO_CLK_T6_M1; -+ return SSB_CHIPCO_CLK_T6_M1; -+ return SSB_CHIPCO_CLK_T6_M0; - case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ - case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ - case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ |