add initial 2.6.28 support for brcm47xx target

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

SVN-Revision: 13909

1 files changed, 93 insertions, 0 deletions

diff --git a/target/linux/brcm47xx/patches-2.6.28/130-remove_scache.patch b/target/linux/brcm47xx/patches-2.6.28/130-remove_scache.patch
new file mode 100644
index 0000000000..e80f51f000
--- /dev/null
+++ b/target/linux/brcm47xx/patches-2.6.28/130-remove_scache.patch
@@ -0,0 +1,93 @@
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -198,7 +198,6 @@ config MIPS_MALTA
+ 	select I8259
+ 	select MIPS_BOARDS_GEN
+ 	select MIPS_BONITO64
+-	select MIPS_CPU_SCACHE
+ 	select PCI_GT64XXX_PCI0
+ 	select MIPS_MSC
+ 	select SWAP_IO_SPACE
+@@ -1383,13 +1382,6 @@ config IP22_CPU_SCACHE
+ 	bool
+ 	select BOARD_SCACHE
+ 
+-#
+-# Support for a MIPS32 / MIPS64 style S-caches
+-#
+-config MIPS_CPU_SCACHE
+-	bool
+-	select BOARD_SCACHE
+-
+ config R5000_CPU_SCACHE
+ 	bool
+ 	select BOARD_SCACHE
+diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
+--- a/arch/mips/kernel/cpu-probe.c
++++ b/arch/mips/kernel/cpu-probe.c
+@@ -755,6 +755,8 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
+ 	case PRID_IMP_25KF:
+ 		c->cputype = CPU_25KF;
+ 		__cpu_name[cpu] = "MIPS 25Kc";
++		/* Probe for L2 cache */
++		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+ 		break;
+ 	case PRID_IMP_34K:
+ 		c->cputype = CPU_34K;
+diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
+--- a/arch/mips/mm/Makefile
++++ b/arch/mips/mm/Makefile
+@@ -31,6 +31,5 @@ obj-$(CONFIG_CPU_VR41XX)	+= c-r4k.o cex-gen.o tlb-r4k.o
+ obj-$(CONFIG_IP22_CPU_SCACHE)	+= sc-ip22.o
+ obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
+ obj-$(CONFIG_RM7000_CPU_SCACHE)	+= sc-rm7k.o
+-obj-$(CONFIG_MIPS_CPU_SCACHE)	+= sc-mips.o
+ 
+ EXTRA_CFLAGS += -Werror
+diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -1121,7 +1121,6 @@ static void __init loongson2_sc_init(void)
+ 
+ extern int r5k_sc_init(void);
+ extern int rm7k_sc_init(void);
+-extern int mips_sc_init(void);
+ 
+ static void __cpuinit setup_scache(void)
+ {
+@@ -1175,29 +1174,17 @@ static void __cpuinit setup_scache(void)
+ #endif
+ 
+ 	default:
+-		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
+-		    c->isa_level == MIPS_CPU_ISA_M32R2 ||
+-		    c->isa_level == MIPS_CPU_ISA_M64R1 ||
+-		    c->isa_level == MIPS_CPU_ISA_M64R2) {
+-#ifdef CONFIG_MIPS_CPU_SCACHE
+-			if (mips_sc_init ()) {
+-				scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+-				printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
+-				       scache_size >> 10,
+-				       way_string[c->scache.ways], c->scache.linesz);
+-			}
+-#else
+-			if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
+-				panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
+-#endif
+-			return;
+-		}
+ 		sc_present = 0;
+ 	}
+ 
+ 	if (!sc_present)
+ 		return;
+ 
++	if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
++	     c->isa_level == MIPS_CPU_ISA_M64R1) &&
++	    !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
++		panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
++
+ 	/* compute a couple of other cache variables */
+ 	c->scache.waysize = scache_size / c->scache.ways;
+