brcm47xx: remove 2.6.25 support

SVN-Revision: 15448

1 files changed, 0 insertions, 1231 deletions

diff --git a/target/linux/brcm47xx/patches-2.6.25/700-ssb-gigabit-ethernet-driver.patch b/target/linux/brcm47xx/patches-2.6.25/700-ssb-gigabit-ethernet-driver.patch
deleted file mode 100644
index 1ed53e5ef8..0000000000
--- a/target/linux/brcm47xx/patches-2.6.25/700-ssb-gigabit-ethernet-driver.patch
+++ /dev/null
@@ -1,1231 +0,0 @@
---- a/drivers/ssb/Kconfig
-+++ b/drivers/ssb/Kconfig
-@@ -125,4 +125,13 @@ config SSB_DRIVER_EXTIF
- 
- 	  If unsure, say N
- 
-+config SSB_DRIVER_GIGE
-+	bool "SSB Broadcom Gigabit Ethernet driver"
-+	depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS
-+	help
-+	  Driver for the Sonics Silicon Backplane attached
-+	  Broadcom Gigabit Ethernet.
-+
-+	  If unsure, say N
-+
- endmenu
---- a/drivers/ssb/Makefile
-+++ b/drivers/ssb/Makefile
-@@ -11,6 +11,7 @@ ssb-y					+= driver_chipcommon.o
- ssb-$(CONFIG_SSB_DRIVER_MIPS)		+= driver_mipscore.o
- ssb-$(CONFIG_SSB_DRIVER_EXTIF)		+= driver_extif.o
- ssb-$(CONFIG_SSB_DRIVER_PCICORE)	+= driver_pcicore.o
-+ssb-$(CONFIG_SSB_DRIVER_GIGE)		+= driver_gige.o
- 
- # b43 pci-ssb-bridge driver
- # Not strictly a part of SSB, but kept here for convenience
---- /dev/null
-+++ b/drivers/ssb/driver_gige.c
-@@ -0,0 +1,294 @@
-+/*
-+ * Sonics Silicon Backplane
-+ * Broadcom Gigabit Ethernet core driver
-+ *
-+ * Copyright 2008, Broadcom Corporation
-+ * Copyright 2008, Michael Buesch <mb@bu3sch.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/ssb/ssb_driver_gige.h>
-+#include <linux/pci.h>
-+#include <linux/pci_regs.h>
-+
-+
-+/*
-+MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
-+MODULE_AUTHOR("Michael Buesch");
-+MODULE_LICENSE("GPL");
-+*/
-+
-+static const struct ssb_device_id ssb_gige_tbl[] = {
-+	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
-+	SSB_DEVTABLE_END
-+};
-+/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
-+
-+
-+static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
-+{
-+	return ssb_read8(dev->dev, offset);
-+}
-+
-+static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
-+{
-+	return ssb_read16(dev->dev, offset);
-+}
-+
-+static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
-+{
-+	return ssb_read32(dev->dev, offset);
-+}
-+
-+static inline void gige_write8(struct ssb_gige *dev,
-+			       u16 offset, u8 value)
-+{
-+	ssb_write8(dev->dev, offset, value);
-+}
-+
-+static inline void gige_write16(struct ssb_gige *dev,
-+				u16 offset, u16 value)
-+{
-+	ssb_write16(dev->dev, offset, value);
-+}
-+
-+static inline void gige_write32(struct ssb_gige *dev,
-+				u16 offset, u32 value)
-+{
-+	ssb_write32(dev->dev, offset, value);
-+}
-+
-+static inline
-+u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
-+{
-+	BUG_ON(offset >= 256);
-+	return gige_read8(dev, SSB_GIGE_PCICFG + offset);
-+}
-+
-+static inline
-+u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
-+{
-+	BUG_ON(offset >= 256);
-+	return gige_read16(dev, SSB_GIGE_PCICFG + offset);
-+}
-+
-+static inline
-+u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
-+{
-+	BUG_ON(offset >= 256);
-+	return gige_read32(dev, SSB_GIGE_PCICFG + offset);
-+}
-+
-+static inline
-+void gige_pcicfg_write8(struct ssb_gige *dev,
-+			unsigned int offset, u8 value)
-+{
-+	BUG_ON(offset >= 256);
-+	gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
-+}
-+
-+static inline
-+void gige_pcicfg_write16(struct ssb_gige *dev,
-+			 unsigned int offset, u16 value)
-+{
-+	BUG_ON(offset >= 256);
-+	gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
-+}
-+
-+static inline
-+void gige_pcicfg_write32(struct ssb_gige *dev,
-+			 unsigned int offset, u32 value)
-+{
-+	BUG_ON(offset >= 256);
-+	gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
-+}
-+
-+static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-+				    int reg, int size, u32 *val)
-+{
-+	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
-+	unsigned long flags;
-+
-+	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+	if (reg >= 256)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	spin_lock_irqsave(&dev->lock, flags);
-+	switch (size) {
-+	case 1:
-+		*val = gige_pcicfg_read8(dev, reg);
-+		break;
-+	case 2:
-+		*val = gige_pcicfg_read16(dev, reg);
-+		break;
-+	case 4:
-+		*val = gige_pcicfg_read32(dev, reg);
-+		break;
-+	default:
-+		WARN_ON(1);
-+	}
-+	spin_unlock_irqrestore(&dev->lock, flags);
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-+				     int reg, int size, u32 val)
-+{
-+	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
-+	unsigned long flags;
-+
-+	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+	if (reg >= 256)
-+		return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	spin_lock_irqsave(&dev->lock, flags);
-+	switch (size) {
-+	case 1:
-+		gige_pcicfg_write8(dev, reg, val);
-+		break;
-+	case 2:
-+		gige_pcicfg_write16(dev, reg, val);
-+		break;
-+	case 4:
-+		gige_pcicfg_write32(dev, reg, val);
-+		break;
-+	default:
-+		WARN_ON(1);
-+	}
-+	spin_unlock_irqrestore(&dev->lock, flags);
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
-+{
-+	struct ssb_gige *dev;
-+	u32 base, tmslow, tmshigh;
-+
-+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
-+	if (!dev)
-+		return -ENOMEM;
-+	dev->dev = sdev;
-+
-+	spin_lock_init(&dev->lock);
-+	dev->pci_controller.pci_ops = &dev->pci_ops;
-+	dev->pci_controller.io_resource = &dev->io_resource;
-+	dev->pci_controller.mem_resource = &dev->mem_resource;
-+	dev->pci_controller.io_map_base = 0x800;
-+	dev->pci_ops.read = ssb_gige_pci_read_config;
-+	dev->pci_ops.write = ssb_gige_pci_write_config;
-+
-+	dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
-+	dev->io_resource.start = 0x800;
-+	dev->io_resource.end = 0x8FF;
-+	dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
-+
-+	if (!ssb_device_is_enabled(sdev))
-+		ssb_device_enable(sdev, 0);
-+
-+	/* Setup BAR0. This is a 64k MMIO region. */
-+	base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
-+	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
-+	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
-+
-+	dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
-+	dev->mem_resource.start = base;
-+	dev->mem_resource.end = base + 0x10000 - 1;
-+	dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
-+
-+	/* Enable the memory region. */
-+	gige_pcicfg_write16(dev, PCI_COMMAND,
-+			    gige_pcicfg_read16(dev, PCI_COMMAND)
-+			    | PCI_COMMAND_MEMORY);
-+
-+	/* Write flushing is controlled by the Flush Status Control register.
-+	 * We want to flush every register write with a timeout and we want
-+	 * to disable the IRQ mask while flushing to avoid concurrency.
-+	 * Note that automatic write flushing does _not_ work from
-+	 * an IRQ handler. The driver must flush manually by reading a register.
-+	 */
-+	gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
-+
-+	/* Check if we have an RGMII or GMII PHY-bus.
-+	 * On RGMII do not bypass the DLLs */
-+	tmslow = ssb_read32(sdev, SSB_TMSLOW);
-+	tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
-+	if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
-+		tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
-+		tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
-+		dev->has_rgmii = 1;
-+	} else {
-+		tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
-+		tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
-+		dev->has_rgmii = 0;
-+	}
-+	tmslow |= SSB_GIGE_TMSLOW_DLLEN;
-+	ssb_write32(sdev, SSB_TMSLOW, tmslow);
-+
-+	ssb_set_drvdata(sdev, dev);
-+	register_pci_controller(&dev->pci_controller);
-+
-+	return 0;
-+}
-+
-+bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
-+{
-+	if (!pdev->resource[0].name)
-+		return 0;
-+	return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
-+}
-+EXPORT_SYMBOL(pdev_is_ssb_gige_core);
-+
-+int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-+				   struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = ssb_get_drvdata(sdev);
-+	struct resource *res;
-+
-+	if (pdev->bus->ops != &dev->pci_ops) {
-+		/* The PCI device is not on this SSB GigE bridge device. */
-+		return -ENODEV;
-+	}
-+
-+	/* Fixup the PCI resources. */
-+	res = &(pdev->resource[0]);
-+	res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
-+	res->name = dev->mem_resource.name;
-+	res->start = dev->mem_resource.start;
-+	res->end = dev->mem_resource.end;
-+
-+	/* Fixup interrupt lines. */
-+	pdev->irq = ssb_mips_irq(sdev) + 2;
-+	pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
-+
-+	return 0;
-+}
-+
-+int ssb_gige_map_irq(struct ssb_device *sdev,
-+		     const struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = ssb_get_drvdata(sdev);
-+
-+	if (pdev->bus->ops != &dev->pci_ops) {
-+		/* The PCI device is not on this SSB GigE bridge device. */
-+		return -ENODEV;
-+	}
-+
-+	return ssb_mips_irq(sdev) + 2;
-+}
-+
-+static struct ssb_driver ssb_gige_driver = {
-+	.name		= "BCM-GigE",
-+	.id_table	= ssb_gige_tbl,
-+	.probe		= ssb_gige_probe,
-+};
-+
-+int ssb_gige_init(void)
-+{
-+	return ssb_driver_register(&ssb_gige_driver);
-+}
---- /dev/null
-+++ b/include/linux/ssb/ssb_driver_gige.h
-@@ -0,0 +1,174 @@
-+#ifndef LINUX_SSB_DRIVER_GIGE_H_
-+#define LINUX_SSB_DRIVER_GIGE_H_
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/pci.h>
-+#include <linux/spinlock.h>
-+
-+
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+
-+
-+#define SSB_GIGE_PCIIO			0x0000 /* PCI I/O Registers (1024 bytes) */
-+#define SSB_GIGE_RESERVED		0x0400 /* Reserved (1024 bytes) */
-+#define SSB_GIGE_PCICFG			0x0800 /* PCI config space (256 bytes) */
-+#define SSB_GIGE_SHIM_FLUSHSTAT		0x0C00 /* PCI to OCP: Flush status control (32bit) */
-+#define SSB_GIGE_SHIM_FLUSHRDA		0x0C04 /* PCI to OCP: Flush read address (32bit) */
-+#define SSB_GIGE_SHIM_FLUSHTO		0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
-+#define SSB_GIGE_SHIM_BARRIER		0x0C0C /* PCI to OCP: Barrier register (32bit) */
-+#define SSB_GIGE_SHIM_MAOCPSI		0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
-+#define SSB_GIGE_SHIM_SIOCPMA		0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
-+
-+/* TM Status High flags */
-+#define SSB_GIGE_TMSHIGH_RGMII		0x00010000 /* Have an RGMII PHY-bus */
-+/* TM Status Low flags */
-+#define SSB_GIGE_TMSLOW_TXBYPASS	0x00080000 /* TX bypass (no delay) */
-+#define SSB_GIGE_TMSLOW_RXBYPASS	0x00100000 /* RX bypass (no delay) */
-+#define SSB_GIGE_TMSLOW_DLLEN		0x01000000 /* Enable DLL controls */
-+
-+/* Boardflags (low) */
-+#define SSB_GIGE_BFL_ROBOSWITCH		0x0010
-+
-+
-+#define SSB_GIGE_MEM_RES_NAME		"SSB Broadcom 47xx GigE memory"
-+#define SSB_GIGE_IO_RES_NAME		"SSB Broadcom 47xx GigE I/O"
-+
-+struct ssb_gige {
-+	struct ssb_device *dev;
-+
-+	spinlock_t lock;
-+
-+	/* True, if the device has an RGMII bus.
-+	 * False, if the device has a GMII bus. */
-+	bool has_rgmii;
-+
-+	/* The PCI controller device. */
-+	struct pci_controller pci_controller;
-+	struct pci_ops pci_ops;
-+	struct resource mem_resource;
-+	struct resource io_resource;
-+};
-+
-+/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
-+extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
-+
-+/* Convert a pci_dev pointer to a ssb_gige pointer. */
-+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
-+{
-+	if (!pdev_is_ssb_gige_core(pdev))
-+		return NULL;
-+	return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
-+}
-+
-+/* Returns whether the PHY is connected by an RGMII bus. */
-+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+	return (dev ? dev->has_rgmii : 0);
-+}
-+
-+/* Returns whether we have a Roboswitch. */
-+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+	if (dev)
-+		return !!(dev->dev->bus->sprom.boardflags_lo &
-+			  SSB_GIGE_BFL_ROBOSWITCH);
-+	return 0;
-+}
-+
-+/* Returns whether we can only do one DMA at once. */
-+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+	if (dev)
-+		return ((dev->dev->bus->chip_id == 0x4785) &&
-+			(dev->dev->bus->chip_rev < 2));
-+	return 0;
-+}
-+
-+/* Returns whether we must flush posted writes. */
-+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
-+{
-+	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
-+	if (dev)
-+		return (dev->dev->bus->chip_id == 0x4785);
-+	return 0;
-+}
-+
-+extern char * nvram_get(const char *name);
-+/* Get the device MAC address */
-+static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
-+{
-+#ifdef CONFIG_BCM947XX
-+	char *res = nvram_get("et0macaddr");
-+	if (res)
-+		memcpy(macaddr, res, 6);
-+#endif
-+}
-+
-+extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-+					  struct pci_dev *pdev);
-+extern int ssb_gige_map_irq(struct ssb_device *sdev,
-+			    const struct pci_dev *pdev);
-+
-+/* The GigE driver is not a standalone module, because we don't have support
-+ * for unregistering the driver. So we could not unload the module anyway. */
-+extern int ssb_gige_init(void);
-+static inline void ssb_gige_exit(void)
-+{
-+	/* Currently we can not unregister the GigE driver,
-+	 * because we can not unregister the PCI bridge. */
-+	BUG();
-+}
-+
-+
-+#else /* CONFIG_SSB_DRIVER_GIGE */
-+/* Gigabit Ethernet driver disabled */
-+
-+
-+static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
-+						 struct pci_dev *pdev)
-+{
-+	return -ENOSYS;
-+}
-+static inline int ssb_gige_map_irq(struct ssb_device *sdev,
-+				   const struct pci_dev *pdev)
-+{
-+	return -ENOSYS;
-+}
-+static inline int ssb_gige_init(void)
-+{
-+	return 0;
-+}
-+static inline void ssb_gige_exit(void)
-+{
-+}
-+
-+static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
-+{
-+	return NULL;
-+}
-+static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
-+{
-+	return 0;
-+}
-+
-+#endif /* CONFIG_SSB_DRIVER_GIGE */
-+#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -60,78 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock);
- /* Core to access the external PCI config space. Can only have one. */
- static struct ssb_pcicore *extpci_core;
- 
--static u32 ssb_pcicore_pcibus_iobase = 0x100;
--static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
--
--int pcibios_plat_dev_init(struct pci_dev *d)
--{
--	struct resource *res;
--	int pos, size;
--	u32 *base;
--
--	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
--		   pci_name(d));
--
--	/* Fix up resource bases */
--	for (pos = 0; pos < 6; pos++) {
--		res = &d->resource[pos];
--		if (res->flags & IORESOURCE_IO)
--			base = &ssb_pcicore_pcibus_iobase;
--		else
--			base = &ssb_pcicore_pcibus_membase;
--		res->flags |= IORESOURCE_PCI_FIXED;
--		if (res->end) {
--			size = res->end - res->start + 1;
--			if (*base & (size - 1))
--				*base = (*base + size) & ~(size - 1);
--			res->start = *base;
--			res->end = res->start + size - 1;
--			*base += size;
--			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
--		}
--		/* Fix up PCI bridge BAR0 only */
--		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
--			break;
--	}
--	/* Fix up interrupt lines */
--	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
--	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
--
--	return 0;
--}
--
--static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
--{
--	u8 lat;
--
--	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
--		return;
--
--	ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
--
--	/* Enable PCI bridge bus mastering and memory space */
--	pci_set_master(dev);
--	if (pcibios_enable_device(dev, ~0) < 0) {
--		ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
--		return;
--	}
--
--	/* Enable PCI bridge BAR1 prefetch and burst */
--	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
--
--	/* Make sure our latency is high enough to handle the devices behind us */
--	lat = 168;
--	ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
--		   pci_name(dev), lat);
--	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
--}
--DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
--
--int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
--{
--	return ssb_mips_irq(extpci_core->dev) + 2;
--}
--
- static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
- 			     unsigned int bus, unsigned int dev,
- 			     unsigned int func, unsigned int off)
-@@ -320,6 +248,95 @@ static struct pci_controller ssb_pcicore
- 	.mem_offset	= 0x24000000,
- };
- 
-+static u32 ssb_pcicore_pcibus_iobase = 0x100;
-+static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
-+
-+/* This function is called when doing a pci_enable_device().
-+ * We must first check if the device is a device on the PCI-core bridge. */
-+int ssb_pcicore_plat_dev_init(struct pci_dev *d)
-+{
-+	struct resource *res;
-+	int pos, size;
-+	u32 *base;
-+
-+	if (d->bus->ops != &ssb_pcicore_pciops) {
-+		/* This is not a device on the PCI-core bridge. */
-+		return -ENODEV;
-+	}
-+
-+	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
-+		   pci_name(d));
-+
-+	/* Fix up resource bases */
-+	for (pos = 0; pos < 6; pos++) {
-+		res = &d->resource[pos];
-+		if (res->flags & IORESOURCE_IO)
-+			base = &ssb_pcicore_pcibus_iobase;
-+		else
-+			base = &ssb_pcicore_pcibus_membase;
-+		res->flags |= IORESOURCE_PCI_FIXED;
-+		if (res->end) {
-+			size = res->end - res->start + 1;
-+			if (*base & (size - 1))
-+				*base = (*base + size) & ~(size - 1);
-+			res->start = *base;
-+			res->end = res->start + size - 1;
-+			*base += size;
-+			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
-+		}
-+		/* Fix up PCI bridge BAR0 only */
-+		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
-+			break;
-+	}
-+	/* Fix up interrupt lines */
-+	d->irq = ssb_mips_irq(extpci_core->dev) + 2;
-+	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
-+
-+	return 0;
-+}
-+
-+/* Early PCI fixup for a device on the PCI-core bridge. */
-+static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)
-+{
-+	u8 lat;
-+
-+	if (dev->bus->ops != &ssb_pcicore_pciops) {
-+		/* This is not a device on the PCI-core bridge. */
-+		return;
-+	}
-+	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
-+		return;
-+
-+	ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
-+
-+	/* Enable PCI bridge bus mastering and memory space */
-+	pci_set_master(dev);
-+	if (pcibios_enable_device(dev, ~0) < 0) {
-+		ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
-+		return;
-+	}
-+
-+	/* Enable PCI bridge BAR1 prefetch and burst */
-+	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
-+
-+	/* Make sure our latency is high enough to handle the devices behind us */
-+	lat = 168;
-+	ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
-+		   pci_name(dev), lat);
-+	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
-+}
-+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
-+
-+/* PCI device IRQ mapping. */
-+int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	if (dev->bus->ops != &ssb_pcicore_pciops) {
-+		/* This is not a device on the PCI-core bridge. */
-+		return -ENODEV;
-+	}
-+	return ssb_mips_irq(extpci_core->dev) + 2;
-+}
-+
- static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
- {
- 	u32 val;
---- a/drivers/ssb/embedded.c
-+++ b/drivers/ssb/embedded.c
-@@ -10,6 +10,9 @@
- 
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_embedded.h>
-+#include <linux/ssb/ssb_driver_pci.h>
-+#include <linux/ssb/ssb_driver_gige.h>
-+#include <linux/pci.h>
- 
- #include "ssb_private.h"
- 
-@@ -130,3 +133,90 @@ u32 ssb_gpio_polarity(struct ssb_bus *bu
- 	return res;
- }
- EXPORT_SYMBOL(ssb_gpio_polarity);
-+
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+static int gige_pci_init_callback(struct ssb_bus *bus, unsigned long data)
-+{
-+	struct pci_dev *pdev = (struct pci_dev *)data;
-+	struct ssb_device *dev;
-+	unsigned int i;
-+	int res;
-+
-+	for (i = 0; i < bus->nr_devices; i++) {
-+		dev = &(bus->devices[i]);
-+		if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
-+			continue;
-+		if (!dev->dev ||
-+		    !dev->dev->driver ||
-+		    !device_is_registered(dev->dev))
-+			continue;
-+		res = ssb_gige_pcibios_plat_dev_init(dev, pdev);
-+		if (res >= 0)
-+			return res;
-+	}
-+
-+	return -ENODEV;
-+}
-+#endif /* CONFIG_SSB_DRIVER_GIGE */
-+
-+int ssb_pcibios_plat_dev_init(struct pci_dev *dev)
-+{
-+	int err;
-+
-+	err = ssb_pcicore_plat_dev_init(dev);
-+	if (!err)
-+		return 0;
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+	err = ssb_for_each_bus_call((unsigned long)dev, gige_pci_init_callback);
-+	if (err >= 0)
-+		return err;
-+#endif
-+	/* This is not a PCI device on any SSB device. */
-+
-+	return -ENODEV;
-+}
-+
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+static int gige_map_irq_callback(struct ssb_bus *bus, unsigned long data)
-+{
-+	const struct pci_dev *pdev = (const struct pci_dev *)data;
-+	struct ssb_device *dev;
-+	unsigned int i;
-+	int res;
-+
-+	for (i = 0; i < bus->nr_devices; i++) {
-+		dev = &(bus->devices[i]);
-+		if (dev->id.coreid != SSB_DEV_ETHERNET_GBIT)
-+			continue;
-+		if (!dev->dev ||
-+		    !dev->dev->driver ||
-+		    !device_is_registered(dev->dev))
-+			continue;
-+		res = ssb_gige_map_irq(dev, pdev);
-+		if (res >= 0)
-+			return res;
-+	}
-+
-+	return -ENODEV;
-+}
-+#endif /* CONFIG_SSB_DRIVER_GIGE */
-+
-+int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	int res;
-+
-+	/* Check if this PCI device is a device on a SSB bus or device
-+	 * and return the IRQ number for it. */
-+
-+	res = ssb_pcicore_pcibios_map_irq(dev, slot, pin);
-+	if (res >= 0)
-+		return res;
-+#ifdef CONFIG_SSB_DRIVER_GIGE
-+	res = ssb_for_each_bus_call((unsigned long)dev, gige_map_irq_callback);
-+	if (res >= 0)
-+		return res;
-+#endif
-+	/* This is not a PCI device on any SSB device. */
-+
-+	return -ENODEV;
-+}
---- a/include/linux/ssb/ssb.h
-+++ b/include/linux/ssb/ssb.h
-@@ -426,5 +426,12 @@ extern int ssb_bus_powerup(struct ssb_bu
- extern u32 ssb_admatch_base(u32 adm);
- extern u32 ssb_admatch_size(u32 adm);
- 
-+/* PCI device mapping and fixup routines.
-+ * Called from the architecture pcibios init code.
-+ * These are only available on SSB_EMBEDDED configurations. */
-+#ifdef CONFIG_SSB_EMBEDDED
-+int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
-+int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-+#endif /* CONFIG_SSB_EMBEDDED */
- 
- #endif /* LINUX_SSB_H_ */
---- a/include/linux/ssb/ssb_driver_pci.h
-+++ b/include/linux/ssb/ssb_driver_pci.h
-@@ -1,6 +1,11 @@
- #ifndef LINUX_SSB_PCICORE_H_
- #define LINUX_SSB_PCICORE_H_
- 
-+#include <linux/types.h>
-+
-+struct pci_dev;
-+
-+
- #ifdef CONFIG_SSB_DRIVER_PCICORE
- 
- /* PCI core registers. */
-@@ -88,6 +93,9 @@ extern void ssb_pcicore_init(struct ssb_
- extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
- 					  struct ssb_device *dev);
- 
-+int ssb_pcicore_plat_dev_init(struct pci_dev *d);
-+int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-+
- 
- #else /* CONFIG_SSB_DRIVER_PCICORE */
- 
-@@ -107,5 +115,16 @@ int ssb_pcicore_dev_irqvecs_enable(struc
- 	return 0;
- }
- 
-+static inline
-+int ssb_pcicore_plat_dev_init(struct pci_dev *d)
-+{
-+	return -ENODEV;
-+}
-+static inline
-+int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+	return -ENODEV;
-+}
-+
- #endif /* CONFIG_SSB_DRIVER_PCICORE */
- #endif /* LINUX_SSB_PCICORE_H_ */
---- a/drivers/ssb/main.c
-+++ b/drivers/ssb/main.c
-@@ -14,6 +14,7 @@
- #include <linux/io.h>
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_regs.h>
-+#include <linux/ssb/ssb_driver_gige.h>
- #include <linux/dma-mapping.h>
- #include <linux/pci.h>
- 
-@@ -68,6 +69,25 @@ found:
- }
- #endif /* CONFIG_SSB_PCIHOST */
- 
-+int ssb_for_each_bus_call(unsigned long data,
-+			  int (*func)(struct ssb_bus *bus, unsigned long data))
-+{
-+	struct ssb_bus *bus;
-+	int res;
-+
-+	ssb_buses_lock();
-+	list_for_each_entry(bus, &buses, list) {
-+		res = func(bus, data);
-+		if (res >= 0) {
-+			ssb_buses_unlock();
-+			return res;
-+		}
-+	}
-+	ssb_buses_unlock();
-+
-+	return -ENODEV;
-+}
-+
- static struct ssb_device *ssb_device_get(struct ssb_device *dev)
- {
- 	if (dev)
-@@ -1181,7 +1201,14 @@ static int __init ssb_modinit(void)
- 	err = b43_pci_ssb_bridge_init();
- 	if (err) {
- 		ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
--			   "initialization failed");
-+			   "initialization failed\n");
-+		/* don't fail SSB init because of this */
-+		err = 0;
-+	}
-+	err = ssb_gige_init();
-+	if (err) {
-+		ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
-+			   "driver initialization failed\n");
- 		/* don't fail SSB init because of this */
- 		err = 0;
- 	}
-@@ -1195,6 +1222,7 @@ fs_initcall(ssb_modinit);
- 
- static void __exit ssb_modexit(void)
- {
-+	ssb_gige_exit();
- 	b43_pci_ssb_bridge_exit();
- 	bus_unregister(&ssb_bustype);
- }
---- a/drivers/ssb/ssb_private.h
-+++ b/drivers/ssb/ssb_private.h
-@@ -118,6 +118,8 @@ extern u32 ssb_calc_clock_rate(u32 pllty
- extern int ssb_devices_freeze(struct ssb_bus *bus);
- extern int ssb_devices_thaw(struct ssb_bus *bus);
- extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
-+int ssb_for_each_bus_call(unsigned long data,
-+			  int (*func)(struct ssb_bus *bus, unsigned long data));
- 
- /* b43_pci_bridge.c */
- #ifdef CONFIG_SSB_B43_PCI_BRIDGE
---- a/drivers/net/tg3.c
-+++ b/drivers/net/tg3.c
-@@ -38,6 +38,7 @@
- #include <linux/workqueue.h>
- #include <linux/prefetch.h>
- #include <linux/dma-mapping.h>
-+#include <linux/ssb/ssb_driver_gige.h>
- 
- #include <net/checksum.h>
- #include <net/ip.h>
-@@ -425,8 +426,9 @@ static void _tw32_flush(struct tg3 *tp, 
- static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
- {
- 	tp->write32_mbox(tp, off, val);
--	if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
--	    !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
-+	if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
-+	    (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
-+	     !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
- 		tp->read32_mbox(tp, off);
- }
- 
-@@ -706,7 +708,7 @@ static void tg3_switch_clocks(struct tg3
- 
- #define PHY_BUSY_LOOPS	5000
- 
--static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
-+static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
- {
- 	u32 frame_val;
- 	unsigned int loops;
-@@ -720,7 +722,7 @@ static int tg3_readphy(struct tg3 *tp, i
- 
- 	*val = 0x0;
- 
--	frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
-+	frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
- 		      MI_COM_PHY_ADDR_MASK);
- 	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
- 		      MI_COM_REG_ADDR_MASK);
-@@ -755,7 +757,12 @@ static int tg3_readphy(struct tg3 *tp, i
- 	return ret;
- }
- 
--static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
-+static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
-+{
-+	return __tg3_readphy(tp, PHY_ADDR, reg, val);
-+}
-+
-+static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
- {
- 	u32 frame_val;
- 	unsigned int loops;
-@@ -771,7 +778,7 @@ static int tg3_writephy(struct tg3 *tp, 
- 		udelay(80);
- 	}
- 
--	frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
-+	frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
- 		      MI_COM_PHY_ADDR_MASK);
- 	frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
- 		      MI_COM_REG_ADDR_MASK);
-@@ -804,6 +811,11 @@ static int tg3_writephy(struct tg3 *tp, 
- 	return ret;
- }
- 
-+static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
-+{
-+	return __tg3_writephy(tp, PHY_ADDR, reg, val);
-+}
-+
- static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
- {
- 	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
-@@ -2250,6 +2262,14 @@ static int tg3_setup_copper_phy(struct t
- 			}
- 		}
- 
-+		if (tp->tg3_flags & TG3_FLG3_ROBOSWITCH) {
-+			current_link_up = 1;
-+			current_speed = SPEED_1000; //FIXME
-+			current_duplex = DUPLEX_FULL;
-+			tp->link_config.active_speed = current_speed;
-+			tp->link_config.active_duplex = current_duplex;
-+		}
-+
- 		if (current_link_up == 1 &&
- 		    tp->link_config.active_duplex == DUPLEX_FULL)
- 			tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
-@@ -5197,6 +5217,11 @@ static int tg3_poll_fw(struct tg3 *tp)
- 	int i;
- 	u32 val;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* We don't use firmware. */
-+		return 0;
-+	}
-+
- 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
- 		/* Wait up to 20ms for init done. */
- 		for (i = 0; i < 200; i++) {
-@@ -5435,6 +5460,14 @@ static int tg3_chip_reset(struct tg3 *tp
- 		tw32(0x5000, 0x400);
- 	}
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* BCM4785: In order to avoid repercussions from using potentially
-+		 * defective internal ROM, stop the Rx RISC CPU, which is not
-+		 * required. */
-+		tg3_stop_fw(tp);
-+		tg3_halt_cpu(tp, RX_CPU_BASE);
-+	}
-+
- 	tw32(GRC_MODE, tp->grc_mode);
- 
- 	if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
-@@ -5704,9 +5737,12 @@ static int tg3_halt_cpu(struct tg3 *tp, 
- 		return -ENODEV;
- 	}
- 
--	/* Clear firmware's nvram arbitration. */
--	if (tp->tg3_flags & TG3_FLAG_NVRAM)
--		tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
-+	if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
-+		/* Clear firmware's nvram arbitration. */
-+		if (tp->tg3_flags & TG3_FLAG_NVRAM)
-+			tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
-+	}
-+
- 	return 0;
- }
- 
-@@ -5787,6 +5823,11 @@ static int tg3_load_5701_a0_firmware_fix
- 	struct fw_info info;
- 	int err, i;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* We don't use firmware. */
-+		return 0;
-+	}
-+
- 	info.text_base = TG3_FW_TEXT_ADDR;
- 	info.text_len = TG3_FW_TEXT_LEN;
- 	info.text_data = &tg3FwText[0];
-@@ -6345,6 +6386,11 @@ static int tg3_load_tso_firmware(struct 
- 	unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
- 	int err, i;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* We don't use firmware. */
-+		return 0;
-+	}
-+
- 	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
- 		return 0;
- 
-@@ -7306,6 +7352,11 @@ static void tg3_timer(unsigned long __op
- 
- 	spin_lock(&tp->lock);
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
-+		/* BCM4785: Flush posted writes from GbE to host memory. */
-+		tr32(HOSTCC_MODE);
-+	}
-+
- 	if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
- 		/* All of this garbage is because when using non-tagged
- 		 * IRQ status the mailbox/status_block protocol the chip
-@@ -8906,6 +8957,11 @@ static int tg3_test_nvram(struct tg3 *tp
- 	__le32 *buf;
- 	int i, j, k, err = 0, size;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* We don't have NVRAM. */
-+		return 0;
-+	}
-+
- 	if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
- 		return -EIO;
- 
-@@ -9689,7 +9745,7 @@ static int tg3_ioctl(struct net_device *
- 			return -EAGAIN;
- 
- 		spin_lock_bh(&tp->lock);
--		err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
-+		err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
- 		spin_unlock_bh(&tp->lock);
- 
- 		data->val_out = mii_regval;
-@@ -9708,7 +9764,7 @@ static int tg3_ioctl(struct net_device *
- 			return -EAGAIN;
- 
- 		spin_lock_bh(&tp->lock);
--		err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
-+		err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
- 		spin_unlock_bh(&tp->lock);
- 
- 		return err;
-@@ -10177,6 +10233,12 @@ static void __devinit tg3_get_5906_nvram
- /* Chips other than 5700/5701 use the NVRAM for fetching info. */
- static void __devinit tg3_nvram_init(struct tg3 *tp)
- {
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
-+		/* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
-+		tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
-+		return;
-+	}
-+
- 	tw32_f(GRC_EEPROM_ADDR,
- 	     (EEPROM_ADDR_FSM_RESET |
- 	      (EEPROM_DEFAULT_CLOCK_PERIOD <<
-@@ -10317,6 +10379,9 @@ static int tg3_nvram_read(struct tg3 *tp
- {
- 	int ret;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
-+		return -ENODEV;
-+
- 	if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
- 		return tg3_nvram_read_using_eeprom(tp, offset, val);
- 
-@@ -10563,6 +10628,9 @@ static int tg3_nvram_write_block(struct 
- {
- 	int ret;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
-+		return -ENODEV;
-+
- 	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
- 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
- 		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
-@@ -11610,7 +11678,6 @@ static int __devinit tg3_get_invariants(
- 		tp->write32 = tg3_write_flush_reg32;
- 	}
- 
--
- 	if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
- 	    (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
- 		tp->write32_tx_mbox = tg3_write32_tx_mbox;
-@@ -11646,6 +11713,11 @@ static int __devinit tg3_get_invariants(
- 	      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
- 		tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
- 
-+	if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
-+		tp->write32_tx_mbox = tg3_write_flush_reg32;
-+		tp->write32_rx_mbox = tg3_write_flush_reg32;
-+	}
-+
- 	/* Get eeprom hw config before calling tg3_set_power_state().
- 	 * In particular, the TG3_FLG2_IS_NIC flag must be
- 	 * determined before calling tg3_set_power_state() so that
-@@ -12017,6 +12089,10 @@ static int __devinit tg3_get_device_addr
- 	}
- 
- 	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
-+		if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
-+			ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
-+	}
-+	if (!is_valid_ether_addr(&dev->dev_addr[0])) {
- #ifdef CONFIG_SPARC
- 		if (!tg3_get_default_macaddr_sparc(tp))
- 			return 0;
-@@ -12508,6 +12584,7 @@ static char * __devinit tg3_phy_string(s
- 	case PHY_ID_BCM5704:	return "5704";
- 	case PHY_ID_BCM5705:	return "5705";
- 	case PHY_ID_BCM5750:	return "5750";
-+	case PHY_ID_BCM5750_2:	return "5750-2";
- 	case PHY_ID_BCM5752:	return "5752";
- 	case PHY_ID_BCM5714:	return "5714";
- 	case PHY_ID_BCM5780:	return "5780";
-@@ -12695,6 +12772,13 @@ static int __devinit tg3_init_one(struct
- 		tp->msg_enable = tg3_debug;
- 	else
- 		tp->msg_enable = TG3_DEF_MSG_ENABLE;
-+	if (pdev_is_ssb_gige_core(pdev)) {
-+		tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
-+		if (ssb_gige_must_flush_posted_writes(pdev))
-+			tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
-+		if (ssb_gige_have_roboswitch(pdev))
-+			tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
-+	}
- 
- 	/* The word/byte swap controls here control register access byte
- 	 * swapping.  DMA data byte swapping is controlled in the GRC_MODE
---- a/drivers/net/tg3.h
-+++ b/drivers/net/tg3.h
-@@ -2477,6 +2477,9 @@ struct tg3 {
- #define TG3_FLG3_ENABLE_APE		0x00000002
- #define TG3_FLG3_5761_5784_AX_FIXES	0x00000004
- #define TG3_FLG3_5701_DMA_BUG		0x00000008
-+#define TG3_FLG3_IS_SSB_CORE		0x00000010
-+#define TG3_FLG3_FLUSH_POSTED_WRITES	0x00000020
-+#define TG3_FLG3_ROBOSWITCH		0x00000040
- 
- 	struct timer_list		timer;
- 	u16				timer_counter;
-@@ -2532,6 +2535,7 @@ struct tg3 {
- #define PHY_ID_BCM5714			0x60008340
- #define PHY_ID_BCM5780			0x60008350
- #define PHY_ID_BCM5755			0xbc050cc0
-+#define PHY_ID_BCM5750_2		0xbc050cd0
- #define PHY_ID_BCM5787			0xbc050ce0
- #define PHY_ID_BCM5756			0xbc050ed0
- #define PHY_ID_BCM5784			0xbc050fa0
-@@ -2568,7 +2572,7 @@ struct tg3 {
- 	 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
- 	 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
- 	 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
--	 (X) == PHY_ID_BCM8002)
-+	 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2)
- 
- 	struct tg3_hw_stats		*hw_stats;
- 	dma_addr_t			stats_mapping;
---- a/drivers/ssb/driver_mipscore.c
-+++ b/drivers/ssb/driver_mipscore.c
-@@ -212,6 +212,7 @@ void ssb_mipscore_init(struct ssb_mipsco
- 			/* fallthrough */
- 		case SSB_DEV_PCI:
- 		case SSB_DEV_ETHERNET:
-+		case SSB_DEV_ETHERNET_GBIT:
- 		case SSB_DEV_80211:
- 		case SSB_DEV_USB20_HOST:
- 			/* These devices get their own IRQ line if available, the rest goes on IRQ0 */