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authorHauke Mehrtens <hauke@hauke-m.de>2020-11-06 20:43:38 +0100
committerHauke Mehrtens <hauke@hauke-m.de>2020-11-11 00:49:38 +0100
commit3a8cfabe0cd11612f776f6e8adec2f17e71e0987 (patch)
tree80f1ce94c966186648b5e64a9b342d14eaa1b467 /target/linux/brcm2708
parent9cdc02be88d5c25791664b1baaf9a7c1a4382c95 (diff)
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kernel: Update kernel 4.9 to version 4.9.243
Compile and runtime tested on lantiq/xrx200. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/brcm2708')
-rw-r--r--target/linux/brcm2708/patches-4.9/950-0021-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch2
-rw-r--r--target/linux/brcm2708/patches-4.9/950-0026-Register-the-clocks-early-during-the-boot-process.patch4
-rw-r--r--target/linux/brcm2708/patches-4.9/950-0152-clk-bcm-Support-rate-change-propagation-on-bcm2835-c.patch2
-rw-r--r--target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch2
-rw-r--r--target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch28
-rw-r--r--target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch8
-rw-r--r--target/linux/brcm2708/patches-4.9/950-0157-clk-bcm2835-Add-leaf-clock-measurement-support-disab.patch24
-rw-r--r--target/linux/brcm2708/patches-4.9/950-0185-clk-bcm2835-Mark-used-PLLs-and-dividers-CRITICAL.patch2
-rw-r--r--target/linux/brcm2708/patches-4.9/950-0186-clk-bcm2835-Add-claim-clocks-property.patch10
9 files changed, 41 insertions, 41 deletions
diff --git a/target/linux/brcm2708/patches-4.9/950-0021-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch b/target/linux/brcm2708/patches-4.9/950-0021-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch
index fc662619d0..38b24b2fb5 100644
--- a/target/linux/brcm2708/patches-4.9/950-0021-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0021-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch
@@ -19,7 +19,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -1268,6 +1268,15 @@ static struct clk_hw *bcm2835_register_c
+@@ -1270,6 +1270,15 @@ static struct clk_hw *bcm2835_register_c
init.name = data->name;
init.flags = data->flags | CLK_IGNORE_UNUSED;
diff --git a/target/linux/brcm2708/patches-4.9/950-0026-Register-the-clocks-early-during-the-boot-process.patch b/target/linux/brcm2708/patches-4.9/950-0026-Register-the-clocks-early-during-the-boot-process.patch
index ec174b0c9d..8a34d9ea79 100644
--- a/target/linux/brcm2708/patches-4.9/950-0026-Register-the-clocks-early-during-the-boot-process.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0026-Register-the-clocks-early-during-the-boot-process.patch
@@ -13,7 +13,7 @@ Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -1909,8 +1909,15 @@ static int bcm2835_clk_probe(struct plat
+@@ -1911,8 +1911,15 @@ static int bcm2835_clk_probe(struct plat
if (ret)
return ret;
@@ -30,7 +30,7 @@ Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
}
static const struct of_device_id bcm2835_clk_of_match[] = {
-@@ -1927,7 +1934,11 @@ static struct platform_driver bcm2835_cl
+@@ -1929,7 +1936,11 @@ static struct platform_driver bcm2835_cl
.probe = bcm2835_clk_probe,
};
diff --git a/target/linux/brcm2708/patches-4.9/950-0152-clk-bcm-Support-rate-change-propagation-on-bcm2835-c.patch b/target/linux/brcm2708/patches-4.9/950-0152-clk-bcm-Support-rate-change-propagation-on-bcm2835-c.patch
index 0fa32dc7b9..3372416733 100644
--- a/target/linux/brcm2708/patches-4.9/950-0152-clk-bcm-Support-rate-change-propagation-on-bcm2835-c.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0152-clk-bcm-Support-rate-change-propagation-on-bcm2835-c.patch
@@ -108,7 +108,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
if (rate > best_rate && rate <= req->rate) {
best_parent = parent;
best_prate = prate;
-@@ -1277,6 +1329,13 @@ static struct clk_hw *bcm2835_register_c
+@@ -1279,6 +1331,13 @@ static struct clk_hw *bcm2835_register_c
if ((cprman_read(cprman, data->ctl_reg) & CM_ENABLE) == 0)
init.flags &= ~CLK_IS_CRITICAL;
diff --git a/target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch b/target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch
index bab7161428..02fe0e0cfb 100644
--- a/target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0153-clk-bcm-Allow-rate-change-propagation-to-PLLH_AUX-on.patch
@@ -19,7 +19,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -1876,7 +1876,12 @@ static const struct bcm2835_clk_desc clk
+@@ -1878,7 +1878,12 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_VECCTL,
.div_reg = CM_VECDIV,
.int_bits = 4,
diff --git a/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch b/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch
index 842e57676b..d4932bd034 100644
--- a/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch
@@ -31,7 +31,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
};
struct bcm2835_clock_data {
-@@ -1258,7 +1259,7 @@ bcm2835_register_pll_divider(struct bcm2
+@@ -1260,7 +1261,7 @@ bcm2835_register_pll_divider(struct bcm2
init.num_parents = 1;
init.name = divider_name;
init.ops = &bcm2835_pll_divider_clk_ops;
@@ -40,7 +40,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
if (!divider)
-@@ -1481,7 +1482,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1483,7 +1484,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLA_CORE,
.load_mask = CM_PLLA_LOADCORE,
.hold_mask = CM_PLLA_HOLDCORE,
@@ -50,7 +50,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
.name = "plla_per",
.source_pll = "plla",
-@@ -1489,7 +1491,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1491,7 +1493,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLA_PER,
.load_mask = CM_PLLA_LOADPER,
.hold_mask = CM_PLLA_HOLDPER,
@@ -60,7 +60,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
.name = "plla_dsi0",
.source_pll = "plla",
-@@ -1505,7 +1508,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1507,7 +1510,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLA_CCP2,
.load_mask = CM_PLLA_LOADCCP2,
.hold_mask = CM_PLLA_HOLDCCP2,
@@ -70,7 +70,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/* PLLB is used for the ARM's clock. */
[BCM2835_PLLB] = REGISTER_PLL(
-@@ -1529,7 +1533,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1531,7 +1535,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLB_ARM,
.load_mask = CM_PLLB_LOADARM,
.hold_mask = CM_PLLB_HOLDARM,
@@ -80,7 +80,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/*
* PLLC is the core PLL, used to drive the core VPU clock.
-@@ -1558,7 +1563,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1560,7 +1565,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLC_CORE0,
.load_mask = CM_PLLC_LOADCORE0,
.hold_mask = CM_PLLC_HOLDCORE0,
@@ -90,7 +90,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
.name = "pllc_core1",
.source_pll = "pllc",
-@@ -1566,7 +1572,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1568,7 +1574,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLC_CORE1,
.load_mask = CM_PLLC_LOADCORE1,
.hold_mask = CM_PLLC_HOLDCORE1,
@@ -100,7 +100,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
.name = "pllc_core2",
.source_pll = "pllc",
-@@ -1574,7 +1581,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1576,7 +1583,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLC_CORE2,
.load_mask = CM_PLLC_LOADCORE2,
.hold_mask = CM_PLLC_HOLDCORE2,
@@ -110,7 +110,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
.name = "pllc_per",
.source_pll = "pllc",
-@@ -1582,7 +1590,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1584,7 +1592,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLC_PER,
.load_mask = CM_PLLC_LOADPER,
.hold_mask = CM_PLLC_HOLDPER,
@@ -120,7 +120,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/*
* PLLD is the display PLL, used to drive DSI display panels.
-@@ -1611,7 +1620,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1613,7 +1622,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLD_CORE,
.load_mask = CM_PLLD_LOADCORE,
.hold_mask = CM_PLLD_HOLDCORE,
@@ -130,7 +130,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
.name = "plld_per",
.source_pll = "plld",
-@@ -1619,7 +1629,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1621,7 +1631,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLD_PER,
.load_mask = CM_PLLD_LOADPER,
.hold_mask = CM_PLLD_HOLDPER,
@@ -140,7 +140,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
.name = "plld_dsi0",
.source_pll = "plld",
-@@ -1664,7 +1675,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1666,7 +1677,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLH_RCAL,
.load_mask = CM_PLLH_LOADRCAL,
.hold_mask = 0,
@@ -150,7 +150,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
.name = "pllh_aux",
.source_pll = "pllh",
-@@ -1672,7 +1684,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1674,7 +1686,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLH_AUX,
.load_mask = CM_PLLH_LOADAUX,
.hold_mask = 0,
@@ -160,7 +160,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
.name = "pllh_pix",
.source_pll = "pllh",
-@@ -1680,7 +1693,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1682,7 +1695,8 @@ static const struct bcm2835_clk_desc clk
.a2w_reg = A2W_PLLH_PIX,
.load_mask = CM_PLLH_LOADPIX,
.hold_mask = 0,
diff --git a/target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch b/target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch
index 0a06cabe68..9ee0e48db9 100644
--- a/target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0156-clk-bcm2835-Register-the-DSI0-DSI1-pixel-clocks.patch
@@ -109,7 +109,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
init.num_parents = 1;
init.name = data->name;
init.ops = &bcm2835_pll_clk_ops;
-@@ -1301,18 +1330,22 @@ static struct clk_hw *bcm2835_register_c
+@@ -1303,18 +1332,22 @@ static struct clk_hw *bcm2835_register_c
struct bcm2835_clock *clock;
struct clk_init_data init;
const char *parents[1 << CM_SRC_BITS];
@@ -139,7 +139,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
}
memset(&init, 0, sizeof(init));
-@@ -1448,6 +1481,47 @@ static const char *const bcm2835_clock_v
+@@ -1450,6 +1483,47 @@ static const char *const bcm2835_clock_v
__VA_ARGS__)
/*
@@ -187,7 +187,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* the real definition of all the pll, pll_dividers and clocks
* these make use of the above REGISTER_* macros
*/
-@@ -1910,6 +1984,18 @@ static const struct bcm2835_clk_desc clk
+@@ -1912,6 +1986,18 @@ static const struct bcm2835_clk_desc clk
.div_reg = CM_DSI1EDIV,
.int_bits = 4,
.frac_bits = 8),
@@ -206,7 +206,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/* the gates */
-@@ -1968,8 +2054,19 @@ static int bcm2835_clk_probe(struct plat
+@@ -1970,8 +2056,19 @@ static int bcm2835_clk_probe(struct plat
if (IS_ERR(cprman->regs))
return PTR_ERR(cprman->regs);
diff --git a/target/linux/brcm2708/patches-4.9/950-0157-clk-bcm2835-Add-leaf-clock-measurement-support-disab.patch b/target/linux/brcm2708/patches-4.9/950-0157-clk-bcm2835-Add-leaf-clock-measurement-support-disab.patch
index d10f60017d..819db2c9c6 100644
--- a/target/linux/brcm2708/patches-4.9/950-0157-clk-bcm2835-Add-leaf-clock-measurement-support-disab.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0157-clk-bcm2835-Add-leaf-clock-measurement-support-disab.patch
@@ -125,7 +125,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
return 0;
}
-@@ -1780,7 +1850,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1782,7 +1852,8 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_OTPCTL,
.div_reg = CM_OTPDIV,
.int_bits = 4,
@@ -135,7 +135,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/*
* Used for a 1Mhz clock for the system clocksource, and also used
* bythe watchdog timer and the camera pulse generator.
-@@ -1814,13 +1885,15 @@ static const struct bcm2835_clk_desc clk
+@@ -1816,13 +1887,15 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_H264CTL,
.div_reg = CM_H264DIV,
.int_bits = 4,
@@ -153,7 +153,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/*
* Secondary SDRAM clock. Used for low-voltage modes when the PLL
-@@ -1831,13 +1904,15 @@ static const struct bcm2835_clk_desc clk
+@@ -1833,13 +1906,15 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_SDCCTL,
.div_reg = CM_SDCDIV,
.int_bits = 6,
@@ -171,7 +171,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/*
* VPU clock. This doesn't have an enable bit, since it drives
* the bus for everything else, and is special so it doesn't need
-@@ -1851,7 +1926,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1853,7 +1928,8 @@ static const struct bcm2835_clk_desc clk
.int_bits = 12,
.frac_bits = 8,
.flags = CLK_IS_CRITICAL,
@@ -181,7 +181,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/* clocks with per parent mux */
[BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
-@@ -1859,19 +1935,22 @@ static const struct bcm2835_clk_desc clk
+@@ -1861,19 +1937,22 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_AVEOCTL,
.div_reg = CM_AVEODIV,
.int_bits = 4,
@@ -207,7 +207,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
.name = "dft",
.ctl_reg = CM_DFTCTL,
-@@ -1883,7 +1962,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1885,7 +1964,8 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_DPICTL,
.div_reg = CM_DPIDIV,
.int_bits = 4,
@@ -217,7 +217,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/* Arasan EMMC clock */
[BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
-@@ -1891,7 +1971,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1893,7 +1973,8 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_EMMCCTL,
.div_reg = CM_EMMCDIV,
.int_bits = 4,
@@ -227,7 +227,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/* General purpose (GPIO) clocks */
[BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
-@@ -1900,7 +1981,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1902,7 +1983,8 @@ static const struct bcm2835_clk_desc clk
.div_reg = CM_GP0DIV,
.int_bits = 12,
.frac_bits = 12,
@@ -237,7 +237,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
.name = "gp1",
.ctl_reg = CM_GP1CTL,
-@@ -1908,7 +1990,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1910,7 +1992,8 @@ static const struct bcm2835_clk_desc clk
.int_bits = 12,
.frac_bits = 12,
.flags = CLK_IS_CRITICAL,
@@ -247,7 +247,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
.name = "gp2",
.ctl_reg = CM_GP2CTL,
-@@ -1923,40 +2006,46 @@ static const struct bcm2835_clk_desc clk
+@@ -1925,40 +2008,46 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_HSMCTL,
.div_reg = CM_HSMDIV,
.int_bits = 4,
@@ -300,7 +300,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/* TV encoder clock. Only operating frequency is 108Mhz. */
[BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
-@@ -1969,7 +2058,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1971,7 +2060,8 @@ static const struct bcm2835_clk_desc clk
* Allow rate change propagation only on PLLH_AUX which is
* assigned index 7 in the parent array.
*/
@@ -310,7 +310,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
/* dsi clocks */
[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
-@@ -1977,25 +2067,29 @@ static const struct bcm2835_clk_desc clk
+@@ -1979,25 +2069,29 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_DSI0ECTL,
.div_reg = CM_DSI0EDIV,
.int_bits = 4,
diff --git a/target/linux/brcm2708/patches-4.9/950-0185-clk-bcm2835-Mark-used-PLLs-and-dividers-CRITICAL.patch b/target/linux/brcm2708/patches-4.9/950-0185-clk-bcm2835-Mark-used-PLLs-and-dividers-CRITICAL.patch
index a8e5e1b645..db584a2275 100644
--- a/target/linux/brcm2708/patches-4.9/950-0185-clk-bcm2835-Mark-used-PLLs-and-dividers-CRITICAL.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0185-clk-bcm2835-Mark-used-PLLs-and-dividers-CRITICAL.patch
@@ -14,7 +14,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -1372,6 +1372,11 @@ bcm2835_register_pll_divider(struct bcm2
+@@ -1374,6 +1374,11 @@ bcm2835_register_pll_divider(struct bcm2
divider->div.hw.init = &init;
divider->div.table = NULL;
diff --git a/target/linux/brcm2708/patches-4.9/950-0186-clk-bcm2835-Add-claim-clocks-property.patch b/target/linux/brcm2708/patches-4.9/950-0186-clk-bcm2835-Add-claim-clocks-property.patch
index 021f7521bc..0cc87eb53f 100644
--- a/target/linux/brcm2708/patches-4.9/950-0186-clk-bcm2835-Add-claim-clocks-property.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0186-clk-bcm2835-Add-claim-clocks-property.patch
@@ -67,7 +67,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
return NULL;
-@@ -1373,8 +1378,10 @@ bcm2835_register_pll_divider(struct bcm2
+@@ -1375,8 +1380,10 @@ bcm2835_register_pll_divider(struct bcm2
divider->div.table = NULL;
if (!(cprman_read(cprman, data->cm_reg) & data->hold_mask)) {
@@ -80,7 +80,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
}
divider->cprman = cprman;
-@@ -2110,6 +2117,8 @@ static const struct bcm2835_clk_desc clk
+@@ -2112,6 +2119,8 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_PERIICTL),
};
@@ -89,7 +89,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
/*
* Permanently take a reference on the parent of the SDRAM clock.
*
-@@ -2129,6 +2138,19 @@ static int bcm2835_mark_sdc_parent_criti
+@@ -2131,6 +2140,19 @@ static int bcm2835_mark_sdc_parent_criti
return clk_prepare_enable(parent);
}
@@ -109,7 +109,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
static int bcm2835_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
-@@ -2138,6 +2160,7 @@ static int bcm2835_clk_probe(struct plat
+@@ -2140,6 +2162,7 @@ static int bcm2835_clk_probe(struct plat
const struct bcm2835_clk_desc *desc;
const size_t asize = ARRAY_SIZE(clk_desc_array);
size_t i;
@@ -117,7 +117,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
int ret;
cprman = devm_kzalloc(dev, sizeof(*cprman) +
-@@ -2153,6 +2176,13 @@ static int bcm2835_clk_probe(struct plat
+@@ -2155,6 +2178,13 @@ static int bcm2835_clk_probe(struct plat
if (IS_ERR(cprman->regs))
return PTR_ERR(cprman->regs);