kernel: bump 4.9 to 4.9.96

Refresh patches, following required reworking:

ar71xx/patches-4.9/930-chipidea-pullup.patch
layerscape/patches-4.9/302-dts-support-layercape.patch
sunxi/patches-4.9/0052-stmmac-form-4-12.patch

Fixes for CVEs:
CVE-2018-1108
CVE-2018-1092

Tested on: ar71xx Archer C7 v2

Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Tested-by: Arjen de Korte <build+openwrt@de-korte.org>

1 files changed, 14 insertions, 14 deletions

diff --git a/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch b/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch
index 1382204249..842e57676b 100644
--- a/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch
+++ b/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch
@@ -31,7 +31,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  };
  
  struct bcm2835_clock_data {
-@@ -1256,7 +1257,7 @@ bcm2835_register_pll_divider(struct bcm2
+@@ -1258,7 +1259,7 @@ bcm2835_register_pll_divider(struct bcm2
  	init.num_parents = 1;
  	init.name = divider_name;
  	init.ops = &bcm2835_pll_divider_clk_ops;
@@ -40,7 +40,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  
  	divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
  	if (!divider)
-@@ -1479,7 +1480,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1481,7 +1482,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLA_CORE,
  		.load_mask = CM_PLLA_LOADCORE,
  		.hold_mask = CM_PLLA_HOLDCORE,
@@ -50,7 +50,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  	[BCM2835_PLLA_PER]	= REGISTER_PLL_DIV(
  		.name = "plla_per",
  		.source_pll = "plla",
-@@ -1487,7 +1489,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1489,7 +1491,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLA_PER,
  		.load_mask = CM_PLLA_LOADPER,
  		.hold_mask = CM_PLLA_HOLDPER,
@@ -60,7 +60,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  	[BCM2835_PLLA_DSI0]	= REGISTER_PLL_DIV(
  		.name = "plla_dsi0",
  		.source_pll = "plla",
-@@ -1503,7 +1506,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1505,7 +1508,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLA_CCP2,
  		.load_mask = CM_PLLA_LOADCCP2,
  		.hold_mask = CM_PLLA_HOLDCCP2,
@@ -70,7 +70,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  
  	/* PLLB is used for the ARM's clock. */
  	[BCM2835_PLLB]		= REGISTER_PLL(
-@@ -1527,7 +1531,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1529,7 +1533,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLB_ARM,
  		.load_mask = CM_PLLB_LOADARM,
  		.hold_mask = CM_PLLB_HOLDARM,
@@ -80,7 +80,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  
  	/*
  	 * PLLC is the core PLL, used to drive the core VPU clock.
-@@ -1556,7 +1561,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1558,7 +1563,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLC_CORE0,
  		.load_mask = CM_PLLC_LOADCORE0,
  		.hold_mask = CM_PLLC_HOLDCORE0,
@@ -90,7 +90,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  	[BCM2835_PLLC_CORE1]	= REGISTER_PLL_DIV(
  		.name = "pllc_core1",
  		.source_pll = "pllc",
-@@ -1564,7 +1570,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1566,7 +1572,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLC_CORE1,
  		.load_mask = CM_PLLC_LOADCORE1,
  		.hold_mask = CM_PLLC_HOLDCORE1,
@@ -100,7 +100,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  	[BCM2835_PLLC_CORE2]	= REGISTER_PLL_DIV(
  		.name = "pllc_core2",
  		.source_pll = "pllc",
-@@ -1572,7 +1579,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1574,7 +1581,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLC_CORE2,
  		.load_mask = CM_PLLC_LOADCORE2,
  		.hold_mask = CM_PLLC_HOLDCORE2,
@@ -110,7 +110,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  	[BCM2835_PLLC_PER]	= REGISTER_PLL_DIV(
  		.name = "pllc_per",
  		.source_pll = "pllc",
-@@ -1580,7 +1588,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1582,7 +1590,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLC_PER,
  		.load_mask = CM_PLLC_LOADPER,
  		.hold_mask = CM_PLLC_HOLDPER,
@@ -120,7 +120,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  
  	/*
  	 * PLLD is the display PLL, used to drive DSI display panels.
-@@ -1609,7 +1618,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1611,7 +1620,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLD_CORE,
  		.load_mask = CM_PLLD_LOADCORE,
  		.hold_mask = CM_PLLD_HOLDCORE,
@@ -130,7 +130,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  	[BCM2835_PLLD_PER]	= REGISTER_PLL_DIV(
  		.name = "plld_per",
  		.source_pll = "plld",
-@@ -1617,7 +1627,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1619,7 +1629,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLD_PER,
  		.load_mask = CM_PLLD_LOADPER,
  		.hold_mask = CM_PLLD_HOLDPER,
@@ -140,7 +140,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  	[BCM2835_PLLD_DSI0]	= REGISTER_PLL_DIV(
  		.name = "plld_dsi0",
  		.source_pll = "plld",
-@@ -1662,7 +1673,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1664,7 +1675,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLH_RCAL,
  		.load_mask = CM_PLLH_LOADRCAL,
  		.hold_mask = 0,
@@ -150,7 +150,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  	[BCM2835_PLLH_AUX]	= REGISTER_PLL_DIV(
  		.name = "pllh_aux",
  		.source_pll = "pllh",
-@@ -1670,7 +1682,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1672,7 +1684,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLH_AUX,
  		.load_mask = CM_PLLH_LOADAUX,
  		.hold_mask = 0,
@@ -160,7 +160,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  	[BCM2835_PLLH_PIX]	= REGISTER_PLL_DIV(
  		.name = "pllh_pix",
  		.source_pll = "pllh",
-@@ -1678,7 +1691,8 @@ static const struct bcm2835_clk_desc clk
+@@ -1680,7 +1693,8 @@ static const struct bcm2835_clk_desc clk
  		.a2w_reg = A2W_PLLH_PIX,
  		.load_mask = CM_PLLH_LOADPIX,
  		.hold_mask = 0,