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authorÁlvaro Fernández Rojas <noltari@gmail.com>2016-12-02 11:50:26 +0100
committerÁlvaro Fernández Rojas <noltari@gmail.com>2016-12-04 12:32:04 +0100
commit011f2c26f1b62e309f2eac6a3101bfe0a3c76c7e (patch)
treebe53d4f11f7625508ee3aea9889e854ab5b5f263 /target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch
parent4257f6548b9480cdb436115b63d5c134c5e91303 (diff)
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brcm2708: update linux 4.4 patches to latest version
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Diffstat (limited to 'target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch')
-rw-r--r--target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch27
1 files changed, 27 insertions, 0 deletions
diff --git a/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch b/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch
new file mode 100644
index 0000000000..c5233b5ed1
--- /dev/null
+++ b/target/linux/brcm2708/patches-4.4/0432-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-divi.patch
@@ -0,0 +1,27 @@
+From bf239659e82c137de23c322fa852b24a0acd3156 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Thu, 31 Mar 2016 12:51:04 -0700
+Subject: [PATCH] clk: bcm2835: Don't rate change PLLs on behalf of dividers.
+
+Our core PLLs are intended to be configured once and left alone. With
+the flag set, asking to set the PLLD_DSI1 clock rate would change PLLD
+just to get closer to the requested DSI clock, thus changing PLLD_PER,
+the UART and ethernet PHY clock rates downstream of it, and breaking
+ethernet.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+---
+ drivers/clk/bcm/clk-bcm2835.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1209,7 +1209,7 @@ bcm2835_register_pll_divider(struct bcm2
+ init.num_parents = 1;
+ init.name = divider_name;
+ init.ops = &bcm2835_pll_divider_clk_ops;
+- init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
++ init.flags = CLK_IGNORE_UNUSED;
+
+ divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
+ if (!divider)