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| author | Álvaro Fernández Rojas <noltari@gmail.com> | 2016-06-08 11:59:37 +0200 |
|---|---|---|
| committer | Álvaro Fernández Rojas <noltari@gmail.com> | 2016-06-08 21:23:21 +0200 |
| commit | 3fc661a98c8046a27dcf45a63049ee6605ebd364 (patch) | |
| tree | 0468b8f3c8d4aa13ecce333ab3ad84146263cbc4 /target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch | |
| parent | c17f02d2f272c6d74b20c2df050437f761d013a6 (diff) | |
| download | upstream-3fc661a98c8046a27dcf45a63049ee6605ebd364.tar.gz upstream-3fc661a98c8046a27dcf45a63049ee6605ebd364.tar.bz2 upstream-3fc661a98c8046a27dcf45a63049ee6605ebd364.zip | |
brcm2708: update linux 4.4 patches to latest version
As usual these patches were extracted from the raspberry pi repo:
https://github.com/raspberrypi/linux/tree/rpi-4.4.y
Also alphabetically order sound-soc kernel packages.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Diffstat (limited to 'target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch')
| -rw-r--r-- | target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch b/target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch new file mode 100644 index 0000000000..1b92074202 --- /dev/null +++ b/target/linux/brcm2708/patches-4.4/0264-clk-bcm2835-add-missing-PLL-clock-dividers.patch @@ -0,0 +1,73 @@ +From 108999bf5b0b9dba4094ca0cff0f0f7e193f3297 Mon Sep 17 00:00:00 2001 +From: Martin Sperl <kernel@martin.sperl.org> +Date: Mon, 29 Feb 2016 15:43:56 +0000 +Subject: [PATCH 264/381] clk: bcm2835: add missing PLL clock dividers + +Signed-off-by: Martin Sperl <kernel@martin.sperl.org> +Signed-off-by: Eric Anholt <eric@anholt.net> +Reviewed-by: Eric Anholt <eric@anholt.net> +(cherry picked from commit 728436956aa172b24a3212295f8b53feb6479f32) +--- + drivers/clk/bcm/clk-bcm2835.c | 32 ++++++++++++++++++++++++++++++++ + include/dt-bindings/clock/bcm2835.h | 5 +++++ + 2 files changed, 37 insertions(+) + +--- a/drivers/clk/bcm/clk-bcm2835.c ++++ b/drivers/clk/bcm/clk-bcm2835.c +@@ -1383,6 +1383,22 @@ static const struct bcm2835_clk_desc clk + .load_mask = CM_PLLA_LOADPER, + .hold_mask = CM_PLLA_HOLDPER, + .fixed_divider = 1), ++ [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( ++ .name = "plla_dsi0", ++ .source_pll = "plla", ++ .cm_reg = CM_PLLA, ++ .a2w_reg = A2W_PLLA_DSI0, ++ .load_mask = CM_PLLA_LOADDSI0, ++ .hold_mask = CM_PLLA_HOLDDSI0, ++ .fixed_divider = 1), ++ [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( ++ .name = "plla_ccp2", ++ .source_pll = "plla", ++ .cm_reg = CM_PLLA, ++ .a2w_reg = A2W_PLLA_CCP2, ++ .load_mask = CM_PLLA_LOADCCP2, ++ .hold_mask = CM_PLLA_HOLDCCP2, ++ .fixed_divider = 1), + + /* PLLB is used for the ARM's clock. */ + [BCM2835_PLLB] = REGISTER_PLL( +@@ -1497,6 +1513,22 @@ static const struct bcm2835_clk_desc clk + .load_mask = CM_PLLD_LOADPER, + .hold_mask = CM_PLLD_HOLDPER, + .fixed_divider = 1), ++ [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( ++ .name = "plld_dsi0", ++ .source_pll = "plld", ++ .cm_reg = CM_PLLD, ++ .a2w_reg = A2W_PLLD_DSI0, ++ .load_mask = CM_PLLD_LOADDSI0, ++ .hold_mask = CM_PLLD_HOLDDSI0, ++ .fixed_divider = 1), ++ [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( ++ .name = "plld_dsi1", ++ .source_pll = "plld", ++ .cm_reg = CM_PLLD, ++ .a2w_reg = A2W_PLLD_DSI1, ++ .load_mask = CM_PLLD_LOADDSI1, ++ .hold_mask = CM_PLLD_HOLDDSI1, ++ .fixed_divider = 1), + + /* + * PLLH is used to supply the pixel clock or the AUX clock for the +--- a/include/dt-bindings/clock/bcm2835.h ++++ b/include/dt-bindings/clock/bcm2835.h +@@ -45,3 +45,8 @@ + #define BCM2835_CLOCK_PERI_IMAGE 29 + #define BCM2835_CLOCK_PWM 30 + #define BCM2835_CLOCK_PCM 31 ++ ++#define BCM2835_PLLA_DSI0 32 ++#define BCM2835_PLLA_CCP2 33 ++#define BCM2835_PLLD_DSI0 34 ++#define BCM2835_PLLD_DSI1 35 |