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authorÁlvaro Fernández Rojas <noltari@gmail.com>2019-07-09 20:32:28 +0200
committerÁlvaro Fernández Rojas <noltari@gmail.com>2019-07-14 12:44:14 +0200
commit42954857190b9df16d9d873ecc7f6cc38e013e44 (patch)
tree98c588f629ff534d458eb0884782ea99672d7634 /target/linux/brcm2708/patches-4.19/950-0190-media-tc358743-Increase-FIFO-level-to-374.patch
parentf1875e902d0afb7d9b9e5285b4fd8da7f6c5e30a (diff)
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brcm2708: add linux 4.19 support
Boot tested on Raspberry Pi B+ (BCM2708) and Raspberry Pi 2 (BCM2709) Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Diffstat (limited to 'target/linux/brcm2708/patches-4.19/950-0190-media-tc358743-Increase-FIFO-level-to-374.patch')
-rw-r--r--target/linux/brcm2708/patches-4.19/950-0190-media-tc358743-Increase-FIFO-level-to-374.patch31
1 files changed, 31 insertions, 0 deletions
diff --git a/target/linux/brcm2708/patches-4.19/950-0190-media-tc358743-Increase-FIFO-level-to-374.patch b/target/linux/brcm2708/patches-4.19/950-0190-media-tc358743-Increase-FIFO-level-to-374.patch
new file mode 100644
index 0000000000..6dac072ff6
--- /dev/null
+++ b/target/linux/brcm2708/patches-4.19/950-0190-media-tc358743-Increase-FIFO-level-to-374.patch
@@ -0,0 +1,31 @@
+From 74cfa3689511a7befa86ab18ff4d4d9662472c08 Mon Sep 17 00:00:00 2001
+From: Dave Stevenson <dave.stevenson@raspberrypi.org>
+Date: Wed, 31 Oct 2018 14:56:59 +0000
+Subject: [PATCH 190/703] media: tc358743: Increase FIFO level to 374.
+
+The existing fixed value of 16 worked for UYVY 720P60 over
+2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888
+1080P60 needs 6 lanes at 594MHz).
+It doesn't allow for lower resolutions to work as the FIFO
+underflows.
+
+374 is required for 1080P24-30 UYVY over 2 lanes @ 972Mbit/s, but
+>374 means that the FIFO underflows on 1080P50 UYVY over 2 lanes
+@ 972Mbit/s.
+
+Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
+---
+ drivers/media/i2c/tc358743.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/media/i2c/tc358743.c
++++ b/drivers/media/i2c/tc358743.c
+@@ -1946,7 +1946,7 @@ static int tc358743_probe_of(struct tc35
+ state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
+ state->pdata.enable_hdcp = false;
+ /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
+- state->pdata.fifo_level = 16;
++ state->pdata.fifo_level = 374;
+ /*
+ * The PLL input clock is obtained by dividing refclk by pll_prd.
+ * It must be between 6 MHz and 40 MHz, lower frequency is better.