brcm2708: add kernel 4.14 support

Patch generation process:
- rebase rpi/rpi-4.14.y on v4.14.89 from linux-stable
- git format-patch v4.14.89

Patches skipped during rebase:
- lan78xx: Read MAC address from DT if present
- lan78xx: Enable LEDs and auto-negotiation
- Revert "softirq: Let ksoftirqd do its job"
- sc16is7xx: Fix for multi-channel stall
- lan78xx: Ignore DT MAC address if already valid
- lan78xx: Simple patch to prevent some crashes
- tcp_write_queue_purge clears all the SKBs in the write queue
- Revert "lan78xx: Simple patch to prevent some crashes"
- lan78xx: Connect phy early
- Arm: mm: ftrace: Only set text back to ro after kernel has been marked ro
- Revert "Revert "softirq: Let ksoftirqd do its job""
- ASoC: cs4265: SOC_SINGLE register value error fix
- Revert "ASoC: cs4265: SOC_SINGLE register value error fix"
- Revert "net: pskb_trim_rcsum() and CHECKSUM_COMPLETE are friends"
- Revert "Revert "net: pskb_trim_rcsum() and CHECKSUM_COMPLETE are friends""

Patches dropped after rebase:
- net: Add non-mainline source for rtl8192cu wlan
- net: Fix rtl8192cu build errors on other platforms
- brcm: adds support for BCM43341 wifi
- brcmfmac: Mute expected startup 'errors'
- ARM64: Fix build break for RTL8187/RTL8192CU wifi
- ARM64: Enable RTL8187/RTL8192CU wifi in build config
- This is the driver for Sony CXD2880 DVB-T2/T tuner + demodulator
- brcmfmac: add CLM download support
- brcmfmac: request_firmware_direct is quieter
- Sets the BCDC priority to constant 0
- brcmfmac: Disable ARP offloading when promiscuous
- brcmfmac: Avoid possible out-of-bounds read
- brcmfmac: Delete redundant length check
- net: rtl8192cu: Normalize indentation
- net: rtl8192cu: Fix implicit fallthrough warnings
- Revert "Sets the BCDC priority to constant 0"
- media: cxd2880: Bump to match 4.18.y version
- media: cxd2880-spi: Bump to match 4.18.y version
- Revert "mm: alloc_contig: re-allow CMA to compact FS pages"
- Revert "Revert "mm: alloc_contig: re-allow CMA to compact FS pages""
- cxd2880: CXD2880_SPI_DRV should select DVB_CXD2880 with
  MEDIA_SUBDRV_AUTOSELECT
- 950-0421-HID-hid-bigbenff-driver-for-BigBen-Interactive-PS3OF.patch
- 950-0453-Add-hid-bigbenff-to-list-of-have_special_driver-for-.patch

Make I2C built-in instead of modular as in upstream defconfig; also the
easiest way to get MFD_ARIZONA enabled, which is required by
kmod-sound-soc-rpi-cirrus.
Add missing compatible strings from
4.9/960-add-rasbperrypi-compatible.patch, using upstream names for
compute modules.
Add extra patch to enable the LEDs on lan78xx.

Compile-tested: bcm2708, bcm2709, bcm2710 (with CONFIG_ALL_KMODS=y)
Runtime-tested: bcm2708, bcm2710

Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>

1 files changed, 149 insertions, 0 deletions

diff --git a/target/linux/brcm2708/patches-4.14/950-0355-drm-vc4-Add-some-missing-HVS-register-definitions.patch b/target/linux/brcm2708/patches-4.14/950-0355-drm-vc4-Add-some-missing-HVS-register-definitions.patch
new file mode 100644
index 0000000000..d86b23e862
--- /dev/null
+++ b/target/linux/brcm2708/patches-4.14/950-0355-drm-vc4-Add-some-missing-HVS-register-definitions.patch
@@ -0,0 +1,149 @@
+From a40aa2492372d46688fc6952c13f38e57ae51a6b Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Wed, 11 Apr 2018 22:49:12 +0200
+Subject: [PATCH 355/454] drm/vc4: Add some missing HVS register definitions.
+
+At least the RGBA expand field we should have been setting, because we
+aren't expanding correctly for 565 -> 8888.  Other registers are ones
+that may be interesting for various projects that have been discussed.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Acked-by: Stefan Schake <stschake@gmail.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/1523479755-20812-2-git-send-email-stschake@gmail.com
+(cherry picked from commit aa808440426f6d163a4f51076132628fee6e1e7d)
+---
+ drivers/gpu/drm/vc4/vc4_regs.h | 96 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 96 insertions(+)
+
+--- a/drivers/gpu/drm/vc4/vc4_regs.h
++++ b/drivers/gpu/drm/vc4/vc4_regs.h
+@@ -359,6 +359,21 @@
+ #define SCALER_DISPCTRL0                        0x00000040
+ # define SCALER_DISPCTRLX_ENABLE		BIT(31)
+ # define SCALER_DISPCTRLX_RESET			BIT(30)
++/* Generates a single frame when VSTART is seen and stops at the last
++ * pixel read from the FIFO.
++ */
++# define SCALER_DISPCTRLX_ONESHOT		BIT(29)
++/* Processes a single context in the dlist and then task switch,
++ * instead of an entire line.
++ */
++# define SCALER_DISPCTRLX_ONECTX		BIT(28)
++/* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
++# define SCALER_DISPCTRLX_FIFO32		BIT(27)
++/* Turns on output to the DISPSLAVE register instead of the normal
++ * FIFO.
++ */
++# define SCALER_DISPCTRLX_FIFOREG		BIT(26)
++
+ # define SCALER_DISPCTRLX_WIDTH_MASK		VC4_MASK(23, 12)
+ # define SCALER_DISPCTRLX_WIDTH_SHIFT		12
+ # define SCALER_DISPCTRLX_HEIGHT_MASK		VC4_MASK(11, 0)
+@@ -431,6 +446,68 @@
+  */
+ # define SCALER_GAMADDR_SRAMENB			BIT(30)
+ 
++#define SCALER_OLEDOFFS                         0x00000080
++/* Clamps R to [16,235] and G/B to [16,240]. */
++# define SCALER_OLEDOFFS_YUVCLAMP               BIT(31)
++
++/* Chooses which display FIFO the matrix applies to. */
++# define SCALER_OLEDOFFS_DISPFIFO_MASK          VC4_MASK(25, 24)
++# define SCALER_OLEDOFFS_DISPFIFO_SHIFT         24
++# define SCALER_OLEDOFFS_DISPFIFO_DISABLED      0
++# define SCALER_OLEDOFFS_DISPFIFO_0             1
++# define SCALER_OLEDOFFS_DISPFIFO_1             2
++# define SCALER_OLEDOFFS_DISPFIFO_2             3
++
++/* Offsets are 8-bit 2s-complement. */
++# define SCALER_OLEDOFFS_RED_MASK               VC4_MASK(23, 16)
++# define SCALER_OLEDOFFS_RED_SHIFT              16
++# define SCALER_OLEDOFFS_GREEN_MASK             VC4_MASK(15, 8)
++# define SCALER_OLEDOFFS_GREEN_SHIFT            8
++# define SCALER_OLEDOFFS_BLUE_MASK              VC4_MASK(7, 0)
++# define SCALER_OLEDOFFS_BLUE_SHIFT             0
++
++/* The coefficients are S0.9 fractions. */
++#define SCALER_OLEDCOEF0                        0x00000084
++# define SCALER_OLEDCOEF0_B_TO_R_MASK           VC4_MASK(29, 20)
++# define SCALER_OLEDCOEF0_B_TO_R_SHIFT          20
++# define SCALER_OLEDCOEF0_B_TO_G_MASK           VC4_MASK(19, 10)
++# define SCALER_OLEDCOEF0_B_TO_G_SHIFT          10
++# define SCALER_OLEDCOEF0_B_TO_B_MASK           VC4_MASK(9, 0)
++# define SCALER_OLEDCOEF0_B_TO_B_SHIFT          0
++
++#define SCALER_OLEDCOEF1                        0x00000088
++# define SCALER_OLEDCOEF1_G_TO_R_MASK           VC4_MASK(29, 20)
++# define SCALER_OLEDCOEF1_G_TO_R_SHIFT          20
++# define SCALER_OLEDCOEF1_G_TO_G_MASK           VC4_MASK(19, 10)
++# define SCALER_OLEDCOEF1_G_TO_G_SHIFT          10
++# define SCALER_OLEDCOEF1_G_TO_B_MASK           VC4_MASK(9, 0)
++# define SCALER_OLEDCOEF1_G_TO_B_SHIFT          0
++
++#define SCALER_OLEDCOEF2                        0x0000008c
++# define SCALER_OLEDCOEF2_R_TO_R_MASK           VC4_MASK(29, 20)
++# define SCALER_OLEDCOEF2_R_TO_R_SHIFT          20
++# define SCALER_OLEDCOEF2_R_TO_G_MASK           VC4_MASK(19, 10)
++# define SCALER_OLEDCOEF2_R_TO_G_SHIFT          10
++# define SCALER_OLEDCOEF2_R_TO_B_MASK           VC4_MASK(9, 0)
++# define SCALER_OLEDCOEF2_R_TO_B_SHIFT          0
++
++/* Slave addresses for DMAing from HVS composition output to other
++ * devices.  The top bits are valid only in !FIFO32 mode.
++ */
++#define SCALER_DISPSLAVE0                       0x000000c0
++#define SCALER_DISPSLAVE1                       0x000000c9
++#define SCALER_DISPSLAVE2                       0x000000d0
++# define SCALER_DISPSLAVE_ISSUE_VSTART          BIT(31)
++# define SCALER_DISPSLAVE_ISSUE_HSTART          BIT(30)
++/* Set when the current line has been read and an HSTART is required. */
++# define SCALER_DISPSLAVE_EOL                   BIT(26)
++/* Set when the display FIFO is empty. */
++# define SCALER_DISPSLAVE_EMPTY                 BIT(25)
++/* Set when there is RGB data ready to read. */
++# define SCALER_DISPSLAVE_VALID                 BIT(24)
++# define SCALER_DISPSLAVE_RGB_MASK              VC4_MASK(23, 0)
++# define SCALER_DISPSLAVE_RGB_SHIFT             0
++
+ #define SCALER_GAMDATA                          0x000000e0
+ #define SCALER_DLIST_START                      0x00002000
+ #define SCALER_DLIST_SIZE                       0x00004000
+@@ -796,6 +873,10 @@ enum hvs_pixel_format {
+ 	HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
+ 	HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
+ 	HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
++	HVS_PIXEL_FORMAT_H264 = 12,
++	HVS_PIXEL_FORMAT_PALETTE = 13,
++	HVS_PIXEL_FORMAT_YUV444_RGB = 14,
++	HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
+ };
+ 
+ /* Note: the LSB is the rightmost character shown.  Only valid for
+@@ -829,12 +910,27 @@ enum hvs_pixel_format {
+ #define SCALER_CTL0_TILING_128B			2
+ #define SCALER_CTL0_TILING_256B_OR_T		3
+ 
++#define SCALER_CTL0_ALPHA_MASK                  BIT(19)
+ #define SCALER_CTL0_HFLIP                       BIT(16)
+ #define SCALER_CTL0_VFLIP                       BIT(15)
+ 
++#define SCALER_CTL0_KEY_MODE_MASK		VC4_MASK(18, 17)
++#define SCALER_CTL0_KEY_MODE_SHIFT		17
++#define SCALER_CTL0_KEY_DISABLED		0
++#define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB	1
++#define SCALER_CTL0_KEY_MATCH			2 /* turn transparent */
++#define SCALER_CTL0_KEY_REPLACE			3 /* replace with value from key mask word 2 */
++
+ #define SCALER_CTL0_ORDER_MASK			VC4_MASK(14, 13)
+ #define SCALER_CTL0_ORDER_SHIFT			13
+ 
++#define SCALER_CTL0_RGBA_EXPAND_MASK		VC4_MASK(12, 11)
++#define SCALER_CTL0_RGBA_EXPAND_SHIFT		11
++#define SCALER_CTL0_RGBA_EXPAND_ZERO		0
++#define SCALER_CTL0_RGBA_EXPAND_LSB		1
++#define SCALER_CTL0_RGBA_EXPAND_MSB		2
++#define SCALER_CTL0_RGBA_EXPAND_ROUND		3
++
+ #define SCALER_CTL0_SCL1_MASK			VC4_MASK(10, 8)
+ #define SCALER_CTL0_SCL1_SHIFT			8
+