diff options
| author | Álvaro Fernández Rojas <noltari@gmail.com> | 2022-05-20 12:39:34 +0200 |
|---|---|---|
| committer | Álvaro Fernández Rojas <noltari@gmail.com> | 2022-05-20 12:39:34 +0200 |
| commit | 66994d68cd815f1e675851b61352e7d52f80cc45 (patch) | |
| tree | 923711643fe15eff11d67308f49fc9eb88b036f7 /target/linux/bmips | |
| parent | 0ad209709973830ff14cba3dd3c275015c0c548e (diff) | |
| download | upstream-66994d68cd815f1e675851b61352e7d52f80cc45.tar.gz upstream-66994d68cd815f1e675851b61352e7d52f80cc45.tar.bz2 upstream-66994d68cd815f1e675851b61352e7d52f80cc45.zip | |
bmips: remove linux 5.10 compatibility
A devent amount of patches have been upstreamed, so maintaining linux 5.10 on
this target makes no sense.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Diffstat (limited to 'target/linux/bmips')
62 files changed, 0 insertions, 9491 deletions
diff --git a/target/linux/bmips/config-5.10 b/target/linux/bmips/config-5.10 deleted file mode 100644 index e42d32bdaa..0000000000 --- a/target/linux/bmips/config-5.10 +++ /dev/null @@ -1,297 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_B53=y -CONFIG_B53_MDIO_DRIVER=y -CONFIG_B53_MMAP_DRIVER=y -CONFIG_B53_SPI_DRIVER=y -CONFIG_BCM6345_EXT_IRQ=y -CONFIG_BCM6345_L1_IRQ=y -CONFIG_BCM6368_ENETSW=y -CONFIG_BCM63XX_POWER=y -CONFIG_BCM7038_L1_IRQ=y -CONFIG_BCM7038_WDT=y -CONFIG_BCM7120_L2_IRQ=y -CONFIG_BCMA=y -CONFIG_BCMA_BLOCKIO=y -# CONFIG_BCMA_DEBUG is not set -# CONFIG_BCMA_DRIVER_GMAC_CMN is not set -# CONFIG_BCMA_DRIVER_MIPS is not set -CONFIG_BCMA_DRIVER_PCI=y -# CONFIG_BCMA_DRIVER_PCI_HOSTMODE is not set -CONFIG_BCMA_HOST_PCI=y -CONFIG_BCMA_HOST_PCI_POSSIBLE=y -# CONFIG_BCMA_HOST_SOC is not set -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BMIPS_GENERIC=y -CONFIG_BOARD_SCACHE=y -CONFIG_BRCMSTB_L2_IRQ=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLK_BCM63268_TIMER=y -CONFIG_CLK_BCM_63XX_GATE=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_BMIPS=y -CONFIG_CPU_BMIPS32_3300=y -CONFIG_CPU_BMIPS4350=y -CONFIG_CPU_BMIPS4380=y -CONFIG_CPU_BMIPS5000=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_CPU_MIPS32=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_NO_EFFICIENT_FFS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_CPUFREQ=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRASH_DUMP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -# CONFIG_DT_BCM93384WVG is not set -# CONFIG_DT_BCM93384WVG_VIPER is not set -# CONFIG_DT_BCM96368MVWG is not set -# CONFIG_DT_BCM97125CBMB is not set -# CONFIG_DT_BCM97346DBSMB is not set -# CONFIG_DT_BCM97358SVMB is not set -# CONFIG_DT_BCM97360SVMB is not set -# CONFIG_DT_BCM97362SVMB is not set -# CONFIG_DT_BCM97420C is not set -# CONFIG_DT_BCM97425SVMB is not set -# CONFIG_DT_BCM97435SVMB is not set -# CONFIG_DT_BCM9EJTAGPRB is not set -# CONFIG_DT_COMTREND_VR3032U is not set -# CONFIG_DT_NETGEAR_CVG834G is not set -CONFIG_DT_NONE=y -# CONFIG_DT_SFR_NEUFBOX4_SERCOMM is not set -# CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -# CONFIG_GPIO_BRCMSTB is not set -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_BCM2835=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LEDS_BCM6328=y -CONFIG_LEDS_BCM6358=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_BUS_MUX=y -CONFIG_MDIO_BUS_MUX_BCM6368=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_CPU_SCACHE=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_EXTERNAL_TIMER=y -CONFIG_MIPS_L1_CACHE_SHIFT=7 -CONFIG_MIPS_L1_CACHE_SHIFT_6=y -CONFIG_MIPS_L1_CACHE_SHIFT_7=y -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_NR_CPU_NR_MAP=2 -CONFIG_MIPS_O32_FP64_SUPPORT=y -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MTD_BCM63XX_PARTS is not set -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_BE_BYTE_SWAP=y -# CONFIG_MTD_CFI_GEOMETRY is not set -# CONFIG_MTD_CFI_NOSWAP is not set -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_JEDECPROBE=y -# CONFIG_MTD_PARSER_IMAGETAG is not set -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_TAG_BRCM=y -CONFIG_NET_DSA_TAG_BRCM_COMMON=y -CONFIG_NET_DSA_TAG_BRCM_LEGACY=y -CONFIG_NET_DSA_TAG_BRCM_PREPEND=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NO_EXCEPT_FILL=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PADATA=y -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_BCM6318=y -CONFIG_PCIE_BCM6328=y -CONFIG_PCIE_PME=y -CONFIG_PCI_BCM6348=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYSICAL_START=0x80010000 -CONFIG_PHY_BCM63XX_USBH=y -# CONFIG_PHY_BRCM_SATA is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_BCM6318=y -CONFIG_PINCTRL_BCM63268=y -CONFIG_PINCTRL_BCM6328=y -CONFIG_PINCTRL_BCM6358=y -CONFIG_PINCTRL_BCM6362=y -CONFIG_PINCTRL_BCM6368=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PROC_VMCORE=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RELAY=y -CONFIG_RESET_BCM6345=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_BCM63XX=y -CONFIG_SERIAL_BCM63XX_CONSOLE=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SOC_BCM63XX=y -CONFIG_SPI=y -CONFIG_SPI_BCM63XX=y -CONFIG_SPI_BCM63XX_HSSPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -CONFIG_SSB=y -CONFIG_SSB_B43_PCI_BRIDGE=y -CONFIG_SSB_BLOCKIO=y -# CONFIG_SSB_DRIVER_MIPS is not set -CONFIG_SSB_DRIVER_PCICORE=y -CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y -CONFIG_SSB_PCIHOST=y -CONFIG_SSB_PCIHOST_POSSIBLE=y -CONFIG_SSB_SPROM=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_SWPHY=y -CONFIG_SYNC_R4K=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_BMIPS=y -CONFIG_SYS_HAS_CPU_BMIPS32_3300=y -CONFIG_SYS_HAS_CPU_BMIPS4350=y -CONFIG_SYS_HAS_CPU_BMIPS4380=y -CONFIG_SYS_HAS_CPU_BMIPS5000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TARGET_ISA_REV=0 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y -CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y -CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y -CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_WEAK_ORDERING=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/bmips/files/drivers/pci/controller/pci-bcm6348.c b/target/linux/bmips/files/drivers/pci/controller/pci-bcm6348.c index 085cc30eba..730068ae79 100644 --- a/target/linux/bmips/files/drivers/pci/controller/pci-bcm6348.c +++ b/target/linux/bmips/files/drivers/pci/controller/pci-bcm6348.c @@ -21,7 +21,6 @@ #include <linux/pci.h> #include <linux/reset.h> #include <linux/types.h> -#include <linux/version.h> #include <linux/vmalloc.h> #include "../pci.h" @@ -347,9 +346,6 @@ static struct pci_controller bcm6348_pci_controller = { .pci_ops = &bcm6348_pci_ops, .io_resource = &bcm6348_pci_io_resource, .mem_resource = &bcm6348_pci_mem_resource, -#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) - .busn_resource = &bcm6348_pci_busn_resource, -#endif }; #ifdef CONFIG_CARDBUS @@ -732,9 +728,7 @@ static int bcm6348_pci_probe(struct platform_device *pdev) struct device_node *np = dev->of_node; struct bcm6348_pci *priv = &bcm6348_pci; struct resource *res; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0) LIST_HEAD(resources); -#endif of_pci_check_probe_only(); @@ -777,9 +771,7 @@ static int bcm6348_pci_probe(struct platform_device *pdev) return -EINVAL; of_pci_parse_bus_range(np, &bcm6348_pci_busn_resource); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0) pci_add_resource(&resources, &bcm6348_pci_busn_resource); -#endif /* * Configuration accesses are done through IO space, remap 4 diff --git a/target/linux/bmips/files/drivers/pci/controller/pcie-bcm6318.c b/target/linux/bmips/files/drivers/pci/controller/pcie-bcm6318.c index 21d8e50063..d73bf850fb 100644 --- a/target/linux/bmips/files/drivers/pci/controller/pcie-bcm6318.c +++ b/target/linux/bmips/files/drivers/pci/controller/pcie-bcm6318.c @@ -227,9 +227,6 @@ static struct pci_controller bcm6318_pcie_controller = { .pci_ops = &bcm6318_pcie_ops, .io_resource = &bcm6318_pcie_io_resource, .mem_resource = &bcm6318_pcie_mem_resource, -#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) - .busn_resource = &bcm6318_pcie_busn_resource, -#endif }; static void bcm6318_pcie_reset(struct bcm6318_pcie *priv) @@ -308,9 +305,7 @@ static int bcm6318_pcie_probe(struct platform_device *pdev) struct bcm6318_pcie *priv = &bcm6318_pcie; struct resource *res; int ret; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0) LIST_HEAD(resources); -#endif of_pci_check_probe_only(); @@ -376,9 +371,7 @@ static int bcm6318_pcie_probe(struct platform_device *pdev) return -EINVAL; of_pci_parse_bus_range(np, &bcm6318_pcie_busn_resource); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0) pci_add_resource(&resources, &bcm6318_pcie_busn_resource); -#endif bcm6318_pcie_reset(priv); bcm6318_pcie_setup(priv); diff --git a/target/linux/bmips/files/drivers/pci/controller/pcie-bcm6328.c b/target/linux/bmips/files/drivers/pci/controller/pcie-bcm6328.c index 4c032cf3d9..f2f74fd5e6 100644 --- a/target/linux/bmips/files/drivers/pci/controller/pcie-bcm6328.c +++ b/target/linux/bmips/files/drivers/pci/controller/pcie-bcm6328.c @@ -210,9 +210,6 @@ static struct pci_controller bcm6328_pcie_controller = { .pci_ops = &bcm6328_pcie_ops, .io_resource = &bcm6328_pcie_io_resource, .mem_resource = &bcm6328_pcie_mem_resource, -#if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0) - .busn_resource = &bcm6328_pcie_busn_resource, -#endif }; static void bcm6328_pcie_reset(struct bcm6328_pcie *priv) @@ -297,9 +294,7 @@ static int bcm6328_pcie_probe(struct platform_device *pdev) struct resource *res; unsigned int i; int ret; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0) LIST_HEAD(resources); -#endif pm_runtime_enable(dev); pm_runtime_no_callbacks(dev); @@ -386,9 +381,7 @@ static int bcm6328_pcie_probe(struct platform_device *pdev) return -EINVAL; of_pci_parse_bus_range(np, &bcm6328_pcie_busn_resource); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0) pci_add_resource(&resources, &bcm6328_pcie_busn_resource); -#endif bcm6328_pcie_reset(priv); bcm6328_pcie_setup(priv); diff --git a/target/linux/bmips/patches-5.10/001-v5.11-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch b/target/linux/bmips/patches-5.10/001-v5.11-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch deleted file mode 100644 index 43ba9ab5b2..0000000000 --- a/target/linux/bmips/patches-5.10/001-v5.11-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 29906e1aac11bf9907e26608216dc7970e73a70e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:33 +0200 -Subject: [PATCH 1/9] mips: bmips: select ARCH_HAS_RESET_CONTROLLER -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This allows to add reset controllers support. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - arch/mips/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -252,6 +252,7 @@ config ATH79 - - config BMIPS_GENERIC - bool "Broadcom Generic BMIPS kernel" -+ select ARCH_HAS_RESET_CONTROLLER - select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL - select ARCH_HAS_PHYS_TO_DMA - select BOOT_RAW diff --git a/target/linux/bmips/patches-5.10/002-v5.11-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch b/target/linux/bmips/patches-5.10/002-v5.11-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch deleted file mode 100644 index 95eb299576..0000000000 --- a/target/linux/bmips/patches-5.10/002-v5.11-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 10c1e714a68b45b124157aa02d80abe244a2a61a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:34 +0200 -Subject: [PATCH 2/9] dt-bindings: reset: add BCM6345 reset controller bindings -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add device tree binding documentation for BCM6345 reset controller. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - .../bindings/reset/brcm,bcm6345-reset.yaml | 37 +++++++++++++++++++ - 1 file changed, 37 insertions(+) - create mode 100644 Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml -@@ -0,0 +1,37 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: "http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#" -+$schema: "http://devicetree.org/meta-schemas/core.yaml#" -+ -+title: BCM6345 reset controller -+ -+description: This document describes the BCM6345 reset controller. -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ -+properties: -+ compatible: -+ const: brcm,bcm6345-reset -+ -+ reg: -+ maxItems: 1 -+ -+ "#reset-cells": -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - "#reset-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; diff --git a/target/linux/bmips/patches-5.10/003-v5.11-reset-add-BCM6345-reset-controller-driver.patch b/target/linux/bmips/patches-5.10/003-v5.11-reset-add-BCM6345-reset-controller-driver.patch deleted file mode 100644 index 39b607d5bd..0000000000 --- a/target/linux/bmips/patches-5.10/003-v5.11-reset-add-BCM6345-reset-controller-driver.patch +++ /dev/null @@ -1,186 +0,0 @@ -From aac025437f14c1647dc6054b95daeebed34f6971 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:35 +0200 -Subject: [PATCH 3/9] reset: add BCM6345 reset controller driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add support for resetting blocks through the Linux reset controller -subsystem for BCM63xx SoCs. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Florian Fainelli <F.fainelli@gmail.com> -Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - drivers/reset/Kconfig | 7 ++ - drivers/reset/Makefile | 1 + - drivers/reset/reset-bcm6345.c | 135 ++++++++++++++++++++++++++++++++++ - 3 files changed, 143 insertions(+) - create mode 100644 drivers/reset/reset-bcm6345.c - ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -35,6 +35,13 @@ config RESET_AXS10X - help - This enables the reset controller driver for AXS10x. - -+config RESET_BCM6345 -+ bool "BCM6345 Reset Controller" -+ depends on BMIPS_GENERIC || COMPILE_TEST -+ default BMIPS_GENERIC -+ help -+ This enables the reset controller driver for BCM6345 SoCs. -+ - config RESET_BERLIN - bool "Berlin Reset Driver" if COMPILE_TEST - default ARCH_BERLIN ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ - obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o - obj-$(CONFIG_RESET_ATH79) += reset-ath79.o - obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o -+obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o - obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o - obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o - obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o ---- /dev/null -+++ b/drivers/reset/reset-bcm6345.c -@@ -0,0 +1,135 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * BCM6345 Reset Controller Driver -+ * -+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com> -+ */ -+ -+#include <linux/delay.h> -+#include <linux/init.h> -+#include <linux/io.h> -+#include <linux/mod_devicetable.h> -+#include <linux/platform_device.h> -+#include <linux/reset-controller.h> -+ -+#define BCM6345_RESET_NUM 32 -+#define BCM6345_RESET_SLEEP_MIN_US 10000 -+#define BCM6345_RESET_SLEEP_MAX_US 20000 -+ -+struct bcm6345_reset { -+ struct reset_controller_dev rcdev; -+ void __iomem *base; -+ spinlock_t lock; -+}; -+ -+static inline struct bcm6345_reset * -+to_bcm6345_reset(struct reset_controller_dev *rcdev) -+{ -+ return container_of(rcdev, struct bcm6345_reset, rcdev); -+} -+ -+static int bcm6345_reset_update(struct reset_controller_dev *rcdev, -+ unsigned long id, bool assert) -+{ -+ struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev); -+ unsigned long flags; -+ uint32_t val; -+ -+ spin_lock_irqsave(&bcm6345_reset->lock, flags); -+ val = __raw_readl(bcm6345_reset->base); -+ if (assert) -+ val &= ~BIT(id); -+ else -+ val |= BIT(id); -+ __raw_writel(val, bcm6345_reset->base); -+ spin_unlock_irqrestore(&bcm6345_reset->lock, flags); -+ -+ return 0; -+} -+ -+static int bcm6345_reset_assert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return bcm6345_reset_update(rcdev, id, true); -+} -+ -+static int bcm6345_reset_deassert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return bcm6345_reset_update(rcdev, id, false); -+} -+ -+static int bcm6345_reset_reset(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ bcm6345_reset_update(rcdev, id, true); -+ usleep_range(BCM6345_RESET_SLEEP_MIN_US, -+ BCM6345_RESET_SLEEP_MAX_US); -+ -+ bcm6345_reset_update(rcdev, id, false); -+ /* -+ * Ensure component is taken out reset state by sleeping also after -+ * deasserting the reset. Otherwise, the component may not be ready -+ * for operation. -+ */ -+ usleep_range(BCM6345_RESET_SLEEP_MIN_US, -+ BCM6345_RESET_SLEEP_MAX_US); -+ -+ return 0; -+} -+ -+static int bcm6345_reset_status(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ struct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev); -+ -+ return !(__raw_readl(bcm6345_reset->base) & BIT(id)); -+} -+ -+static struct reset_control_ops bcm6345_reset_ops = { -+ .assert = bcm6345_reset_assert, -+ .deassert = bcm6345_reset_deassert, -+ .reset = bcm6345_reset_reset, -+ .status = bcm6345_reset_status, -+}; -+ -+static int bcm6345_reset_probe(struct platform_device *pdev) -+{ -+ struct bcm6345_reset *bcm6345_reset; -+ -+ bcm6345_reset = devm_kzalloc(&pdev->dev, -+ sizeof(*bcm6345_reset), GFP_KERNEL); -+ if (!bcm6345_reset) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, bcm6345_reset); -+ -+ bcm6345_reset->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(bcm6345_reset->base)) -+ return PTR_ERR(bcm6345_reset->base); -+ -+ spin_lock_init(&bcm6345_reset->lock); -+ bcm6345_reset->rcdev.ops = &bcm6345_reset_ops; -+ bcm6345_reset->rcdev.owner = THIS_MODULE; -+ bcm6345_reset->rcdev.of_node = pdev->dev.of_node; -+ bcm6345_reset->rcdev.of_reset_n_cells = 1; -+ bcm6345_reset->rcdev.nr_resets = BCM6345_RESET_NUM; -+ -+ return devm_reset_controller_register(&pdev->dev, -+ &bcm6345_reset->rcdev); -+} -+ -+static const struct of_device_id bcm6345_reset_of_match[] = { -+ { .compatible = "brcm,bcm6345-reset" }, -+ { /* sentinel */ }, -+}; -+ -+static struct platform_driver bcm6345_reset_driver = { -+ .probe = bcm6345_reset_probe, -+ .driver = { -+ .name = "bcm6345-reset", -+ .of_match_table = bcm6345_reset_of_match, -+ .suppress_bind_attrs = true, -+ }, -+}; -+builtin_platform_driver(bcm6345_reset_driver); diff --git a/target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch b/target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch deleted file mode 100644 index 85c63f6bd1..0000000000 --- a/target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 83f865d7e32e40b4903b1f83537c63fc5cdf1eb8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:36 +0200 -Subject: [PATCH 4/9] mips: bmips: dts: add BCM6328 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6328 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 ++++++ - include/dt-bindings/reset/bcm6328-reset.h | 18 ++++++++++++++++++ - 2 files changed, 24 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6328-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm6328.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi -@@ -57,6 +57,12 @@ - #clock-cells = <1>; - }; - -+ periph_rst: reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; -+ - periph_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x10>, ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6328-reset.h -@@ -0,0 +1,18 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6328_H -+#define __DT_BINDINGS_RESET_BCM6328_H -+ -+#define BCM6328_RST_SPI 0 -+#define BCM6328_RST_EPHY 1 -+#define BCM6328_RST_SAR 2 -+#define BCM6328_RST_ENETSW 3 -+#define BCM6328_RST_USBS 4 -+#define BCM6328_RST_USBH 5 -+#define BCM6328_RST_PCM 6 -+#define BCM6328_RST_PCIE_CORE 7 -+#define BCM6328_RST_PCIE 8 -+#define BCM6328_RST_PCIE_EXT 9 -+#define BCM6328_RST_PCIE_HARD 10 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6328_H */ diff --git a/target/linux/bmips/patches-5.10/005-v5.11-mips-bmips-dts-add-BCM6358-reset-controller-support.patch b/target/linux/bmips/patches-5.10/005-v5.11-mips-bmips-dts-add-BCM6358-reset-controller-support.patch deleted file mode 100644 index d350dbb190..0000000000 --- a/target/linux/bmips/patches-5.10/005-v5.11-mips-bmips-dts-add-BCM6358-reset-controller-support.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 8079cfba4c7b8cae900c27104b4512fa5ed1f021 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:37 +0200 -Subject: [PATCH 5/9] mips: bmips: dts: add BCM6358 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6358 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - arch/mips/boot/dts/brcm/bcm6358.dtsi | 6 ++++++ - include/dt-bindings/reset/bcm6358-reset.h | 15 +++++++++++++++ - 2 files changed, 21 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6358-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm6358.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi -@@ -82,6 +82,12 @@ - interrupts = <2>, <3>; - }; - -+ periph_rst: reset-controller@fffe0034 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0xfffe0034 0x4>; -+ #reset-cells = <1>; -+ }; -+ - leds0: led-controller@fffe00d0 { - #address-cells = <1>; - #size-cells = <0>; ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6358-reset.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6358_H -+#define __DT_BINDINGS_RESET_BCM6358_H -+ -+#define BCM6358_RST_SPI 0 -+#define BCM6358_RST_ENET 2 -+#define BCM6358_RST_MPI 3 -+#define BCM6358_RST_EPHY 6 -+#define BCM6358_RST_SAR 7 -+#define BCM6358_RST_USBH 12 -+#define BCM6358_RST_PCM 13 -+#define BCM6358_RST_ADSL 14 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6358_H */ diff --git a/target/linux/bmips/patches-5.10/006-v5.11-mips-bmips-dts-add-BCM6362-reset-controller-support.patch b/target/linux/bmips/patches-5.10/006-v5.11-mips-bmips-dts-add-BCM6362-reset-controller-support.patch deleted file mode 100644 index 31a8edd87d..0000000000 --- a/target/linux/bmips/patches-5.10/006-v5.11-mips-bmips-dts-add-BCM6362-reset-controller-support.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 226383600be58dcf2e070e4ac8a371640024fe54 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:38 +0200 -Subject: [PATCH 6/9] mips: bmips: dts: add BCM6362 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6362 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - arch/mips/boot/dts/brcm/bcm6362.dtsi | 6 ++++++ - include/dt-bindings/reset/bcm6362-reset.h | 22 ++++++++++++++++++++++ - 2 files changed, 28 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6362-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm6362.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm6362.dtsi -@@ -70,6 +70,12 @@ - mask = <0x1>; - }; - -+ periph_rst: reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; -+ - periph_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x10>, ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6362-reset.h -@@ -0,0 +1,22 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6362_H -+#define __DT_BINDINGS_RESET_BCM6362_H -+ -+#define BCM6362_RST_SPI 0 -+#define BCM6362_RST_IPSEC 1 -+#define BCM6362_RST_EPHY 2 -+#define BCM6362_RST_SAR 3 -+#define BCM6362_RST_ENETSW 4 -+#define BCM6362_RST_USBD 5 -+#define BCM6362_RST_USBH 6 -+#define BCM6362_RST_PCM 7 -+#define BCM6362_RST_PCIE_CORE 8 -+#define BCM6362_RST_PCIE 9 -+#define BCM6362_RST_PCIE_EXT 10 -+#define BCM6362_RST_WLAN_SHIM 11 -+#define BCM6362_RST_DDR_PHY 12 -+#define BCM6362_RST_FAP 13 -+#define BCM6362_RST_WLAN_UBUS 14 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6362_H */ diff --git a/target/linux/bmips/patches-5.10/007-v5.11-mips-bmips-dts-add-BCM6368-reset-controller-support.patch b/target/linux/bmips/patches-5.10/007-v5.11-mips-bmips-dts-add-BCM6368-reset-controller-support.patch deleted file mode 100644 index 9d03665d19..0000000000 --- a/target/linux/bmips/patches-5.10/007-v5.11-mips-bmips-dts-add-BCM6368-reset-controller-support.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 7acf84e87857721d66a1ba800c2c50669089f43d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:39 +0200 -Subject: [PATCH 7/9] mips: bmips: dts: add BCM6368 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6368 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - arch/mips/boot/dts/brcm/bcm6368.dtsi | 6 ++++++ - include/dt-bindings/reset/bcm6368-reset.h | 16 ++++++++++++++++ - 2 files changed, 22 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6368-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm6368.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi -@@ -70,6 +70,12 @@ - mask = <0x1>; - }; - -+ periph_rst: reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; -+ - periph_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x10>, ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6368-reset.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6368_H -+#define __DT_BINDINGS_RESET_BCM6368_H -+ -+#define BCM6368_RST_SPI 0 -+#define BCM6368_RST_MPI 3 -+#define BCM6368_RST_IPSEC 4 -+#define BCM6368_RST_EPHY 6 -+#define BCM6368_RST_SAR 7 -+#define BCM6368_RST_SWITCH 10 -+#define BCM6368_RST_USBD 11 -+#define BCM6368_RST_USBH 12 -+#define BCM6368_RST_PCM 13 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6368_H */ diff --git a/target/linux/bmips/patches-5.10/008-v5.11-mips-bmips-dts-add-BCM63268-reset-controller-support.patch b/target/linux/bmips/patches-5.10/008-v5.11-mips-bmips-dts-add-BCM63268-reset-controller-support.patch deleted file mode 100644 index b508190b91..0000000000 --- a/target/linux/bmips/patches-5.10/008-v5.11-mips-bmips-dts-add-BCM63268-reset-controller-support.patch +++ /dev/null @@ -1,64 +0,0 @@ -From b7aa228813bdf014d6ad173ca3abfced30f1ed37 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:40 +0200 -Subject: [PATCH 8/9] mips: bmips: dts: add BCM63268 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM63268 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - arch/mips/boot/dts/brcm/bcm63268.dtsi | 6 +++++ - include/dt-bindings/reset/bcm63268-reset.h | 26 ++++++++++++++++++++++ - 2 files changed, 32 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm63268-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm63268.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi -@@ -70,6 +70,12 @@ - mask = <0x1>; - }; - -+ periph_rst: reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; -+ - periph_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x20>, ---- /dev/null -+++ b/include/dt-bindings/reset/bcm63268-reset.h -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM63268_H -+#define __DT_BINDINGS_RESET_BCM63268_H -+ -+#define BCM63268_RST_SPI 0 -+#define BCM63268_RST_IPSEC 1 -+#define BCM63268_RST_EPHY 2 -+#define BCM63268_RST_SAR 3 -+#define BCM63268_RST_ENETSW 4 -+#define BCM63268_RST_USBS 5 -+#define BCM63268_RST_USBH 6 -+#define BCM63268_RST_PCM 7 -+#define BCM63268_RST_PCIE_CORE 8 -+#define BCM63268_RST_PCIE 9 -+#define BCM63268_RST_PCIE_EXT 10 -+#define BCM63268_RST_WLAN_SHIM 11 -+#define BCM63268_RST_DDR_PHY 12 -+#define BCM63268_RST_FAP0 13 -+#define BCM63268_RST_WLAN_UBUS 14 -+#define BCM63268_RST_DECT 15 -+#define BCM63268_RST_FAP1 16 -+#define BCM63268_RST_PCIE_HARD 17 -+#define BCM63268_RST_GPHY 18 -+ -+#endif /* __DT_BINDINGS_RESET_BCM63268_H */ diff --git a/target/linux/bmips/patches-5.10/009-v5.11-mips-bmips-add-BCM6318-reset-controller-definitions.patch b/target/linux/bmips/patches-5.10/009-v5.11-mips-bmips-add-BCM6318-reset-controller-definitions.patch deleted file mode 100644 index 4cbaa569cd..0000000000 --- a/target/linux/bmips/patches-5.10/009-v5.11-mips-bmips-add-BCM6318-reset-controller-definitions.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 8c9e8b0a28225c46f2cca0a09a3a111bb043e874 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:41 +0200 -Subject: [PATCH 9/9] mips: bmips: add BCM6318 reset controller definitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6318 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Acked-by: Florian Fainelli <F.fainelli@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - include/dt-bindings/reset/bcm6318-reset.h | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6318-reset.h - ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6318-reset.h -@@ -0,0 +1,20 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6318_H -+#define __DT_BINDINGS_RESET_BCM6318_H -+ -+#define BCM6318_RST_SPI 0 -+#define BCM6318_RST_EPHY 1 -+#define BCM6318_RST_SAR 2 -+#define BCM6318_RST_ENETSW 3 -+#define BCM6318_RST_USBD 4 -+#define BCM6318_RST_USBH 5 -+#define BCM6318_RST_PCIE_CORE 6 -+#define BCM6318_RST_PCIE 7 -+#define BCM6318_RST_PCIE_EXT 8 -+#define BCM6318_RST_PCIE_HARD 9 -+#define BCM6318_RST_ADSL 10 -+#define BCM6318_RST_PHYMIPS 11 -+#define BCM6318_RST_HOSTMIPS 12 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6318_H */ diff --git a/target/linux/bmips/patches-5.10/020-v5.12-mips-bmips-init-clocks-earlier.patch b/target/linux/bmips/patches-5.10/020-v5.12-mips-bmips-init-clocks-earlier.patch deleted file mode 100644 index 7b9d92609f..0000000000 --- a/target/linux/bmips/patches-5.10/020-v5.12-mips-bmips-init-clocks-earlier.patch +++ /dev/null @@ -1,25 +0,0 @@ -From faf3c25e51a7e91b69ea26da72c74a8786af7968 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Mon, 22 Feb 2021 21:33:50 +0100 -Subject: [PATCH] mips: bmips: init clocks earlier -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -device_initcall() is too late for bcm63xx. -We need to call of_clk_init() earlier in order to properly boot. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - arch/mips/bmips/setup.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/bmips/setup.c -+++ b/arch/mips/bmips/setup.c -@@ -201,4 +201,4 @@ static int __init plat_dev_init(void) - return 0; - } - --device_initcall(plat_dev_init); -+arch_initcall(plat_dev_init); diff --git a/target/linux/bmips/patches-5.10/021-v5.12-spi-bcm63xx-spi-fix-pm_runtime.patch b/target/linux/bmips/patches-5.10/021-v5.12-spi-bcm63xx-spi-fix-pm_runtime.patch deleted file mode 100644 index 3fe7a552cd..0000000000 --- a/target/linux/bmips/patches-5.10/021-v5.12-spi-bcm63xx-spi-fix-pm_runtime.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 73ae625da5c36300fccd809738e7c68f49ebce35 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Tue, 23 Feb 2021 16:18:50 +0100 -Subject: [PATCH 1/2] spi: bcm63xx-spi: fix pm_runtime -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The driver sets auto_runtime_pm to true, but it doesn't call -pm_runtime_enable(), which results in "Failed to power device" when PM support -is enabled. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210223151851.4110-2-noltari@gmail.com -Signed-off-by: Mark Brown <broonie@kernel.org> ---- - drivers/spi/spi-bcm63xx.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/spi/spi-bcm63xx.c -+++ b/drivers/spi/spi-bcm63xx.c -@@ -593,11 +593,13 @@ static int bcm63xx_spi_probe(struct plat - - bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); - -+ pm_runtime_enable(&pdev->dev); -+ - /* register and we are done */ - ret = devm_spi_register_master(dev, master); - if (ret) { - dev_err(dev, "spi register failed\n"); -- goto out_clk_disable; -+ goto out_pm_disable; - } - - dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n", -@@ -605,6 +607,8 @@ static int bcm63xx_spi_probe(struct plat - - return 0; - -+out_pm_disable: -+ pm_runtime_disable(&pdev->dev); - out_clk_disable: - clk_disable_unprepare(clk); - out_err: diff --git a/target/linux/bmips/patches-5.10/022-v5.12-spi-bcm63xx-hsspi-fix-pm_runtime.patch b/target/linux/bmips/patches-5.10/022-v5.12-spi-bcm63xx-hsspi-fix-pm_runtime.patch deleted file mode 100644 index 47c75659b9..0000000000 --- a/target/linux/bmips/patches-5.10/022-v5.12-spi-bcm63xx-hsspi-fix-pm_runtime.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 216e8e80057a9f0b6366327881acf88eaf9f1fd4 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Tue, 23 Feb 2021 16:18:51 +0100 -Subject: [PATCH 2/2] spi: bcm63xx-hsspi: fix pm_runtime -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The driver sets auto_runtime_pm to true, but it doesn't call -pm_runtime_enable(), which results in "Failed to power device" when PM support -is enabled. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210223151851.4110-3-noltari@gmail.com -Signed-off-by: Mark Brown <broonie@kernel.org> ---- - drivers/spi/spi-bcm63xx-hsspi.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/drivers/spi/spi-bcm63xx-hsspi.c -+++ b/drivers/spi/spi-bcm63xx-hsspi.c -@@ -21,6 +21,7 @@ - #include <linux/mutex.h> - #include <linux/of.h> - #include <linux/reset.h> -+#include <linux/pm_runtime.h> - - #define HSSPI_GLOBAL_CTRL_REG 0x0 - #define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 -@@ -439,13 +440,17 @@ static int bcm63xx_hsspi_probe(struct pl - if (ret) - goto out_put_master; - -+ pm_runtime_enable(&pdev->dev); -+ - /* register and we are done */ - ret = devm_spi_register_master(dev, master); - if (ret) -- goto out_put_master; -+ goto out_pm_disable; - - return 0; - -+out_pm_disable: -+ pm_runtime_disable(&pdev->dev); - out_put_master: - spi_master_put(master); - out_disable_pll_clk: diff --git a/target/linux/bmips/patches-5.10/040-v5.13-mips-smp-bmips-fix-CPU-mappings.patch b/target/linux/bmips/patches-5.10/040-v5.13-mips-smp-bmips-fix-CPU-mappings.patch deleted file mode 100644 index 6ae4330439..0000000000 --- a/target/linux/bmips/patches-5.10/040-v5.13-mips-smp-bmips-fix-CPU-mappings.patch +++ /dev/null @@ -1,60 +0,0 @@ -From c0f41a0dac1f3db6c40aabc0f3ac8868709ba6a6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Feb 2021 08:33:36 +0100 -Subject: [PATCH] mips: smp-bmips: fix CPU mappings -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -When booting bmips with SMP enabled on a BCM6358 running on CPU #1 instead of -CPU #0, the current CPU mapping code produces the following: -- smp_processor_id(): 0 -- cpu_logical_map(0): 1 -- cpu_number_map(0): 1 - -This is because SMP isn't supported on BCM6358 since it has a shared TLB, so -it is disabled and max_cpus is decreased from 2 to 1. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - arch/mips/kernel/smp-bmips.c | 27 +++++++++++++++++---------- - 1 file changed, 17 insertions(+), 10 deletions(-) - ---- a/arch/mips/kernel/smp-bmips.c -+++ b/arch/mips/kernel/smp-bmips.c -@@ -134,17 +134,24 @@ static void __init bmips_smp_setup(void) - if (!board_ebase_setup) - board_ebase_setup = &bmips_ebase_setup; - -- __cpu_number_map[boot_cpu] = 0; -- __cpu_logical_map[0] = boot_cpu; -+ if (max_cpus > 1) { -+ __cpu_number_map[boot_cpu] = 0; -+ __cpu_logical_map[0] = boot_cpu; - -- for (i = 0; i < max_cpus; i++) { -- if (i != boot_cpu) { -- __cpu_number_map[i] = cpu; -- __cpu_logical_map[cpu] = i; -- cpu++; -+ for (i = 0; i < max_cpus; i++) { -+ if (i != boot_cpu) { -+ __cpu_number_map[i] = cpu; -+ __cpu_logical_map[cpu] = i; -+ cpu++; -+ } -+ set_cpu_possible(i, 1); -+ set_cpu_present(i, 1); - } -- set_cpu_possible(i, 1); -- set_cpu_present(i, 1); -+ } else { -+ __cpu_number_map[0] = boot_cpu; -+ __cpu_logical_map[0] = 0; -+ set_cpu_possible(0, 1); -+ set_cpu_present(0, 1); - } - } - diff --git a/target/linux/bmips/patches-5.10/042-v5.13-dt-bindings-rng-bcm2835-add-clock-constraints.patch b/target/linux/bmips/patches-5.10/042-v5.13-dt-bindings-rng-bcm2835-add-clock-constraints.patch deleted file mode 100644 index 246293e384..0000000000 --- a/target/linux/bmips/patches-5.10/042-v5.13-dt-bindings-rng-bcm2835-add-clock-constraints.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 0618e07ea3e0981d7765b43d3f7db39e739842eb Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Fri, 5 Mar 2021 08:01:30 +0100 -Subject: [PATCH 1/3] dt-bindings: rng: bcm2835: add clock constraints -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -brcm,bcm6368-rng controllers require enabling the IPSEC clock in order to get -a functional RNG. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> ---- - .../devicetree/bindings/rng/brcm,bcm2835.yaml | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml -+++ b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml -@@ -35,6 +35,16 @@ required: - - compatible - - reg - -+if: -+ properties: -+ compatible: -+ enum: -+ - brcm,bcm6368-rng -+then: -+ required: -+ - clocks -+ - clock-names -+ - additionalProperties: false - - examples: diff --git a/target/linux/bmips/patches-5.10/043-v5.13-dt-bindings-rng-bcm2835-document-reset-support.patch b/target/linux/bmips/patches-5.10/043-v5.13-dt-bindings-rng-bcm2835-document-reset-support.patch deleted file mode 100644 index ce14a1037c..0000000000 --- a/target/linux/bmips/patches-5.10/043-v5.13-dt-bindings-rng-bcm2835-document-reset-support.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 381345820db55bf8e7289de047c24c00a2e3690d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Fri, 5 Mar 2021 08:01:31 +0100 -Subject: [PATCH 2/3] dt-bindings: rng: bcm2835: document reset support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -brcm,bcm6368-rng controllers require resetting the IPSEC clock in order to get -a functional RNG. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> ---- - .../devicetree/bindings/rng/brcm,bcm2835.yaml | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml -+++ b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml -@@ -28,6 +28,12 @@ properties: - clock-names: - const: ipsec - -+ resets: -+ maxItems: 1 -+ -+ reset-names: -+ const: ipsec -+ - interrupts: - maxItems: 1 - -@@ -44,6 +50,8 @@ then: - required: - - clocks - - clock-names -+ - resets -+ - reset-names - - additionalProperties: false - -@@ -68,4 +76,7 @@ examples: - - clocks = <&periph_clk 18>; - clock-names = "ipsec"; -+ -+ resets = <&periph_rst 4>; -+ reset-names = "ipsec"; - }; diff --git a/target/linux/bmips/patches-5.10/044-v5.13-hwrng-bcm2835-add-reset-support.patch b/target/linux/bmips/patches-5.10/044-v5.13-hwrng-bcm2835-add-reset-support.patch deleted file mode 100644 index 24b74817be..0000000000 --- a/target/linux/bmips/patches-5.10/044-v5.13-hwrng-bcm2835-add-reset-support.patch +++ /dev/null @@ -1,78 +0,0 @@ -From e5f9f41d5e62004c913bfd4ddf06abe032f5ce1c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Fri, 5 Mar 2021 08:01:32 +0100 -Subject: [PATCH 3/3] hwrng: bcm2835 - add reset support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6368 devices need to reset the IPSEC controller in order to generate true -random numbers. - -This is what BCM6368 produces without a reset: -root@OpenWrt:/# cat /dev/hwrng | rngtest -c 1000 -rngtest 6.10 -Copyright (c) 2004 by Henrique de Moraes Holschuh -This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - -rngtest: starting FIPS tests... -rngtest: bits received from input: 20000032 -rngtest: FIPS 140-2 successes: 0 -rngtest: FIPS 140-2 failures: 1000 -rngtest: FIPS 140-2(2001-10-10) Monobit: 2 -rngtest: FIPS 140-2(2001-10-10) Poker: 1000 -rngtest: FIPS 140-2(2001-10-10) Runs: 1000 -rngtest: FIPS 140-2(2001-10-10) Long run: 30 -rngtest: FIPS 140-2(2001-10-10) Continuous run: 0 -rngtest: input channel speed: (min=37.253; avg=320.827; max=635.783)Mibits/s -rngtest: FIPS tests speed: (min=12.141; avg=15.034; max=16.428)Mibits/s -rngtest: Program run time: 1336176 microseconds - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> ---- - drivers/char/hw_random/bcm2835-rng.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/char/hw_random/bcm2835-rng.c -+++ b/drivers/char/hw_random/bcm2835-rng.c -@@ -13,6 +13,7 @@ - #include <linux/platform_device.h> - #include <linux/printk.h> - #include <linux/clk.h> -+#include <linux/reset.h> - - #define RNG_CTRL 0x0 - #define RNG_STATUS 0x4 -@@ -32,6 +33,7 @@ struct bcm2835_rng_priv { - void __iomem *base; - bool mask_interrupts; - struct clk *clk; -+ struct reset_control *reset; - }; - - static inline struct bcm2835_rng_priv *to_rng_priv(struct hwrng *rng) -@@ -94,6 +96,10 @@ static int bcm2835_rng_init(struct hwrng - return ret; - } - -+ ret = reset_control_reset(priv->reset); -+ if (ret) -+ return ret; -+ - if (priv->mask_interrupts) { - /* mask the interrupt */ - val = rng_readl(priv, RNG_INT_MASK); -@@ -159,6 +165,10 @@ static int bcm2835_rng_probe(struct plat - if (PTR_ERR(priv->clk) == -EPROBE_DEFER) - return -EPROBE_DEFER; - -+ priv->reset = devm_reset_control_get_optional_exclusive(dev, NULL); -+ if (IS_ERR(priv->reset)) -+ return PTR_ERR(priv->reset); -+ - priv->rng.name = pdev->name; - priv->rng.init = bcm2835_rng_init; - priv->rng.read = bcm2835_rng_read; diff --git a/target/linux/bmips/patches-5.10/046-v5.13-dt-bindings-net-Add-bcm6368-mdio-mux-bindings.patch b/target/linux/bmips/patches-5.10/046-v5.13-dt-bindings-net-Add-bcm6368-mdio-mux-bindings.patch deleted file mode 100644 index 05d688fe03..0000000000 --- a/target/linux/bmips/patches-5.10/046-v5.13-dt-bindings-net-Add-bcm6368-mdio-mux-bindings.patch +++ /dev/null @@ -1,96 +0,0 @@ -From da6557edb9f3f4513b01d9a20a36c2fbc31810a1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Mon, 15 Mar 2021 16:45:27 +0100 -Subject: [PATCH 1/2] dt-bindings: net: Add bcm6368-mdio-mux bindings -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add documentations for bcm6368 mdio mux driver. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Signed-off-by: David S. Miller <davem@davemloft.net> ---- - .../bindings/net/brcm,bcm6368-mdio-mux.yaml | 76 +++++++++++++++++++ - 1 file changed, 76 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/brcm,bcm6368-mdio-mux.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/brcm,bcm6368-mdio-mux.yaml -@@ -0,0 +1,76 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6368 MDIO bus multiplexer -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ -+description: -+ This MDIO bus multiplexer defines buses that could be internal as well as -+ external to SoCs. When child bus is selected, one needs to select these two -+ properties as well to generate desired MDIO transaction on appropriate bus. -+ -+allOf: -+ - $ref: "mdio.yaml#" -+ -+properties: -+ compatible: -+ const: brcm,bcm6368-mdio-mux -+ -+ "#address-cells": -+ const: 1 -+ -+ "#size-cells": -+ const: 0 -+ -+ reg: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ -+patternProperties: -+ '^mdio@[0-1]$': -+ type: object -+ properties: -+ reg: -+ maxItems: 1 -+ -+ "#address-cells": -+ const: 1 -+ -+ "#size-cells": -+ const: 0 -+ -+ required: -+ - reg -+ - "#address-cells" -+ - "#size-cells" -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ mdio0: mdio@10e000b0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,bcm6368-mdio-mux"; -+ reg = <0x10e000b0 0x6>; -+ -+ mdio_int: mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ }; -+ -+ mdio_ext: mdio@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/047-v5.13-net-mdio-Add-BCM6368-MDIO-mux-bus-controller.patch b/target/linux/bmips/patches-5.10/047-v5.13-net-mdio-Add-BCM6368-MDIO-mux-bus-controller.patch deleted file mode 100644 index 0f1a2cd9ca..0000000000 --- a/target/linux/bmips/patches-5.10/047-v5.13-net-mdio-Add-BCM6368-MDIO-mux-bus-controller.patch +++ /dev/null @@ -1,237 +0,0 @@ -From e239756717b5c866958823a1609e2ccf268435be Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Mon, 15 Mar 2021 16:45:28 +0100 -Subject: [PATCH 2/2] net: mdio: Add BCM6368 MDIO mux bus controller -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This controller is present on BCM6318, BCM6328, BCM6362, BCM6368 and BCM63268 -SoCs. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Signed-off-by: David S. Miller <davem@davemloft.net> ---- - drivers/net/mdio/Kconfig | 11 ++ - drivers/net/mdio/Makefile | 1 + - drivers/net/mdio/mdio-mux-bcm6368.c | 184 ++++++++++++++++++++++++++++ - 3 files changed, 196 insertions(+) - create mode 100644 drivers/net/mdio/mdio-mux-bcm6368.c - ---- a/drivers/net/mdio/Kconfig -+++ b/drivers/net/mdio/Kconfig -@@ -200,6 +200,17 @@ config MDIO_BUS_MUX_MESON_G12A - the amlogic g12a SoC. The multiplexers connects either the external - or the internal MDIO bus to the parent bus. - -+config MDIO_BUS_MUX_BCM6368 -+ tristate "Broadcom BCM6368 MDIO bus multiplexers" -+ depends on OF && OF_MDIO && (BMIPS_GENERIC || COMPILE_TEST) -+ select MDIO_BUS_MUX -+ default BMIPS_GENERIC -+ help -+ This module provides a driver for MDIO bus multiplexers found in -+ BCM6368 based Broadcom SoCs. This multiplexer connects one of several -+ child MDIO bus to a parent bus. Buses could be internal as well as -+ external and selection logic lies inside the same multiplexer. -+ - config MDIO_BUS_MUX_BCM_IPROC - tristate "Broadcom iProc based MDIO bus multiplexers" - depends on OF && OF_MDIO && (ARCH_BCM_IPROC || COMPILE_TEST) ---- a/drivers/net/mdio/Makefile -+++ b/drivers/net/mdio/Makefile -@@ -22,6 +22,7 @@ obj-$(CONFIG_MDIO_THUNDER) += mdio-thun - obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o - - obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o -+obj-$(CONFIG_MDIO_BUS_MUX_BCM6368) += mdio-mux-bcm6368.o - obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o - obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o - obj-$(CONFIG_MDIO_BUS_MUX_MESON_G12A) += mdio-mux-meson-g12a.o ---- /dev/null -+++ b/drivers/net/mdio/mdio-mux-bcm6368.c -@@ -0,0 +1,184 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Broadcom BCM6368 mdiomux bus controller driver -+ * -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ */ -+ -+#include <linux/delay.h> -+#include <linux/io.h> -+#include <linux/kernel.h> -+#include <linux/mdio-mux.h> -+#include <linux/module.h> -+#include <linux/of.h> -+#include <linux/of_platform.h> -+#include <linux/of_mdio.h> -+#include <linux/phy.h> -+#include <linux/platform_device.h> -+#include <linux/sched.h> -+ -+#define MDIOC_REG 0x0 -+#define MDIOC_EXT_MASK BIT(16) -+#define MDIOC_REG_SHIFT 20 -+#define MDIOC_PHYID_SHIFT 25 -+#define MDIOC_RD_MASK BIT(30) -+#define MDIOC_WR_MASK BIT(31) -+ -+#define MDIOD_REG 0x4 -+ -+struct bcm6368_mdiomux_desc { -+ void *mux_handle; -+ void __iomem *base; -+ struct device *dev; -+ struct mii_bus *mii_bus; -+ int ext_phy; -+}; -+ -+static int bcm6368_mdiomux_read(struct mii_bus *bus, int phy_id, int loc) -+{ -+ struct bcm6368_mdiomux_desc *md = bus->priv; -+ uint32_t reg; -+ int ret; -+ -+ __raw_writel(0, md->base + MDIOC_REG); -+ -+ reg = MDIOC_RD_MASK | -+ (phy_id << MDIOC_PHYID_SHIFT) | -+ (loc << MDIOC_REG_SHIFT); -+ if (md->ext_phy) -+ reg |= MDIOC_EXT_MASK; -+ -+ __raw_writel(reg, md->base + MDIOC_REG); -+ udelay(50); -+ ret = __raw_readw(md->base + MDIOD_REG); -+ -+ return ret; -+} -+ -+static int bcm6368_mdiomux_write(struct mii_bus *bus, int phy_id, int loc, -+ uint16_t val) -+{ -+ struct bcm6368_mdiomux_desc *md = bus->priv; -+ uint32_t reg; -+ -+ __raw_writel(0, md->base + MDIOC_REG); -+ -+ reg = MDIOC_WR_MASK | -+ (phy_id << MDIOC_PHYID_SHIFT) | -+ (loc << MDIOC_REG_SHIFT); -+ if (md->ext_phy) -+ reg |= MDIOC_EXT_MASK; -+ reg |= val; -+ -+ __raw_writel(reg, md->base + MDIOC_REG); -+ udelay(50); -+ -+ return 0; -+} -+ -+static int bcm6368_mdiomux_switch_fn(int current_child, int desired_child, -+ void *data) -+{ -+ struct bcm6368_mdiomux_desc *md = data; -+ -+ md->ext_phy = desired_child; -+ -+ return 0; -+} -+ -+static int bcm6368_mdiomux_probe(struct platform_device *pdev) -+{ -+ struct bcm6368_mdiomux_desc *md; -+ struct mii_bus *bus; -+ struct resource *res; -+ int rc; -+ -+ md = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL); -+ if (!md) -+ return -ENOMEM; -+ md->dev = &pdev->dev; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -EINVAL; -+ -+ /* -+ * Just ioremap, as this MDIO block is usually integrated into an -+ * Ethernet MAC controller register range -+ */ -+ md->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); -+ if (!md->base) { -+ dev_err(&pdev->dev, "failed to ioremap register\n"); -+ return -ENOMEM; -+ } -+ -+ md->mii_bus = devm_mdiobus_alloc(&pdev->dev); -+ if (!md->mii_bus) { -+ dev_err(&pdev->dev, "mdiomux bus alloc failed\n"); -+ return ENOMEM; -+ } -+ -+ bus = md->mii_bus; -+ bus->priv = md; -+ bus->name = "BCM6368 MDIO mux bus"; -+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id); -+ bus->parent = &pdev->dev; -+ bus->read = bcm6368_mdiomux_read; -+ bus->write = bcm6368_mdiomux_write; -+ bus->phy_mask = 0x3f; -+ bus->dev.of_node = pdev->dev.of_node; -+ -+ rc = mdiobus_register(bus); -+ if (rc) { -+ dev_err(&pdev->dev, "mdiomux registration failed\n"); -+ return rc; -+ } -+ -+ platform_set_drvdata(pdev, md); -+ -+ rc = mdio_mux_init(md->dev, md->dev->of_node, -+ bcm6368_mdiomux_switch_fn, &md->mux_handle, md, -+ md->mii_bus); -+ if (rc) { -+ dev_info(md->dev, "mdiomux initialization failed\n"); -+ goto out_register; -+ } -+ -+ dev_info(&pdev->dev, "Broadcom BCM6368 MDIO mux bus\n"); -+ -+ return 0; -+ -+out_register: -+ mdiobus_unregister(bus); -+ return rc; -+} -+ -+static int bcm6368_mdiomux_remove(struct platform_device *pdev) -+{ -+ struct bcm6368_mdiomux_desc *md = platform_get_drvdata(pdev); -+ -+ mdio_mux_uninit(md->mux_handle); -+ mdiobus_unregister(md->mii_bus); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm6368_mdiomux_ids[] = { -+ { .compatible = "brcm,bcm6368-mdio-mux", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, bcm6368_mdiomux_ids); -+ -+static struct platform_driver bcm6368_mdiomux_driver = { -+ .driver = { -+ .name = "bcm6368-mdio-mux", -+ .of_match_table = bcm6368_mdiomux_ids, -+ }, -+ .probe = bcm6368_mdiomux_probe, -+ .remove = bcm6368_mdiomux_remove, -+}; -+module_platform_driver(bcm6368_mdiomux_driver); -+ -+MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>"); -+MODULE_DESCRIPTION("BCM6368 mdiomux bus controller driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/bmips/patches-5.10/053-v5.13-gpio-regmap-set-gpio_chip-of_node.patch b/target/linux/bmips/patches-5.10/053-v5.13-gpio-regmap-set-gpio_chip-of_node.patch deleted file mode 100644 index 58dfaff8bd..0000000000 --- a/target/linux/bmips/patches-5.10/053-v5.13-gpio-regmap-set-gpio_chip-of_node.patch +++ /dev/null @@ -1,63 +0,0 @@ -From d46bf9ec4596654f36245e3b14765bcb422be6ad Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:03 +0100 -Subject: [PATCH 02/22] gpio: regmap: set gpio_chip of_node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This is needed for properly registering GPIO regmap as a child of a regmap -pin controller. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Michael Walle <michael@walle.cc> -Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> -Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> -Link: https://lore.kernel.org/r/20210324081923.20379-3-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/gpio/gpio-regmap.c | 5 +++++ - include/linux/gpio/regmap.h | 4 ++++ - 2 files changed, 9 insertions(+) - ---- a/drivers/gpio/gpio-regmap.c -+++ b/drivers/gpio/gpio-regmap.c -@@ -254,6 +254,11 @@ struct gpio_regmap *gpio_regmap_register - chip->names = config->names; - chip->label = config->label ?: dev_name(config->parent); - -+#if defined(CONFIG_OF_GPIO) -+ /* gpiolib will use of_node of the parent if chip->of_node is NULL */ -+ chip->of_node = to_of_node(config->fwnode); -+#endif /* CONFIG_OF_GPIO */ -+ - /* - * If our regmap is fast_io we should probably set can_sleep to false. - * Right now, the regmap doesn't save this property, nor is there any ---- a/include/linux/gpio/regmap.h -+++ b/include/linux/gpio/regmap.h -@@ -4,6 +4,7 @@ - #define _LINUX_GPIO_REGMAP_H - - struct device; -+struct fwnode_handle; - struct gpio_regmap; - struct irq_domain; - struct regmap; -@@ -16,6 +17,8 @@ struct regmap; - * @parent: The parent device - * @regmap: The regmap used to access the registers - * given, the name of the device is used -+ * @fwnode: (Optional) The firmware node. -+ * If not given, the fwnode of the parent is used. - * @label: (Optional) Descriptive name for GPIO controller. - * If not given, the name of the device is used. - * @ngpio: Number of GPIOs -@@ -57,6 +60,7 @@ struct regmap; - struct gpio_regmap_config { - struct device *parent; - struct regmap *regmap; -+ struct fwnode_handle *fwnode; - - const char *label; - int ngpio; diff --git a/target/linux/bmips/patches-5.10/054-v5.13-dt-bindings-improve-BCM6345-GPIO-binding-documentati.patch b/target/linux/bmips/patches-5.10/054-v5.13-dt-bindings-improve-BCM6345-GPIO-binding-documentati.patch deleted file mode 100644 index 85b751df05..0000000000 --- a/target/linux/bmips/patches-5.10/054-v5.13-dt-bindings-improve-BCM6345-GPIO-binding-documentati.patch +++ /dev/null @@ -1,163 +0,0 @@ -From fb9da17bd26552f48cda4f2f658379e7f5860691 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:04 +0100 -Subject: [PATCH 03/22] dt-bindings: improve BCM6345 GPIO binding documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Convert existing BCM6345 GPIO binding documentation to YAML and add binding -documentation for the GPIO controller found in BCM6318, BCM6328, BCM6358, -BCM6362, BCM6368 and BCM63268 SoCs. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-4-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../bindings/gpio/brcm,bcm6345-gpio.txt | 46 ---------- - .../bindings/gpio/brcm,bcm6345-gpio.yaml | 86 +++++++++++++++++++ - 2 files changed, 86 insertions(+), 46 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt - create mode 100644 Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml - ---- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt -+++ /dev/null -@@ -1,46 +0,0 @@ --Bindings for the Broadcom's brcm,bcm6345-gpio memory-mapped GPIO controllers. -- --These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345 --are the only ones which don't need a pinctrl driver. --BCM6338 have 8-bit data and dirout registers, where GPIO state can be read --and/or written, and the direction changed from input to output. --BCM6345 have 16-bit data and dirout registers, where GPIO state can be read --and/or written, and the direction changed from input to output. -- --Required properties: -- - compatible: should be "brcm,bcm6345-gpio" -- - reg-names: must contain -- "dat" - data register -- "dirout" - direction (output) register -- - reg: address + size pairs describing the GPIO register sets; -- order must correspond with the order of entries in reg-names -- - #gpio-cells: must be set to 2. The first cell is the pin number and -- the second cell is used to specify the gpio polarity: -- 0 = active high -- 1 = active low -- - gpio-controller: Marks the device node as a gpio controller. -- --Optional properties: -- - native-endian: use native endian memory. -- --Examples: -- - BCM6338: -- gpio: gpio-controller@fffe0407 { -- compatible = "brcm,bcm6345-gpio"; -- reg-names = "dirout", "dat"; -- reg = <0xfffe0407 1>, <0xfffe040f 1>; -- -- #gpio-cells = <2>; -- gpio-controller; -- }; -- -- - BCM6345: -- gpio: gpio-controller@fffe0406 { -- compatible = "brcm,bcm6345-gpio"; -- reg-names = "dirout", "dat"; -- reg = <0xfffe0406 2>, <0xfffe040a 2>; -- native-endian; -- -- #gpio-cells = <2>; -- gpio-controller; -- }; ---- /dev/null -+++ b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml -@@ -0,0 +1,86 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6345 GPIO controller -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: |+ -+ Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers. -+ -+ These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345 -+ are the only ones which don't need a pinctrl driver. -+ -+ BCM6338 have 8-bit data and dirout registers, where GPIO state can be read -+ and/or written, and the direction changed from input to output. -+ BCM6345 have 16-bit data and dirout registers, where GPIO state can be read -+ and/or written, and the direction changed from input to output. -+ BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data -+ and dirout registers, where GPIO state can be read and/or written, and the -+ direction changed from input to output. -+ -+properties: -+ compatible: -+ enum: -+ - brcm,bcm6318-gpio -+ - brcm,bcm6328-gpio -+ - brcm,bcm6345-gpio -+ - brcm,bcm6358-gpio -+ - brcm,bcm6362-gpio -+ - brcm,bcm6368-gpio -+ - brcm,bcm63268-gpio -+ -+ gpio-controller: true -+ -+ "#gpio-cells": -+ const: 2 -+ -+ gpio-ranges: -+ maxItems: 1 -+ -+ native-endian: true -+ -+ reg: -+ maxItems: 2 -+ -+ reg-names: -+ items: -+ - const: dirout -+ - const: dat -+ -+required: -+ - compatible -+ - reg -+ - reg-names -+ - gpio-controller -+ - '#gpio-cells' -+ -+additionalProperties: false -+ -+examples: -+ - | -+ gpio@fffe0406 { -+ compatible = "brcm,bcm6345-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0xfffe0406 2>, <0xfffe040a 2>; -+ native-endian; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ - | -+ gpio@0 { -+ compatible = "brcm,bcm63268-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0x0 0x8>, <0x8 0x8>; -+ -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 0 52>; -+ #gpio-cells = <2>; -+ }; diff --git a/target/linux/bmips/patches-5.10/055-v5.13-pinctrl-bcm-add-bcm63xx-base-code.patch b/target/linux/bmips/patches-5.10/055-v5.13-pinctrl-bcm-add-bcm63xx-base-code.patch deleted file mode 100644 index eec8b98a49..0000000000 --- a/target/linux/bmips/patches-5.10/055-v5.13-pinctrl-bcm-add-bcm63xx-base-code.patch +++ /dev/null @@ -1,208 +0,0 @@ -From 132f95016db0a0a0659e99b471a7d3fd0c60f961 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:05 +0100 -Subject: [PATCH 04/22] pinctrl: bcm: add bcm63xx base code -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add a helper for registering BCM63XX pin controllers. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210324081923.20379-5-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/bcm/Kconfig | 7 ++ - drivers/pinctrl/bcm/Makefile | 1 + - drivers/pinctrl/bcm/pinctrl-bcm63xx.c | 109 ++++++++++++++++++++++++++ - drivers/pinctrl/bcm/pinctrl-bcm63xx.h | 43 ++++++++++ - 4 files changed, 160 insertions(+) - create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63xx.c - create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63xx.h - ---- a/drivers/pinctrl/bcm/Kconfig -+++ b/drivers/pinctrl/bcm/Kconfig -@@ -29,6 +29,13 @@ config PINCTRL_BCM2835 - help - Say Y here to enable the Broadcom BCM2835 GPIO driver. - -+config PINCTRL_BCM63XX -+ bool -+ select GENERIC_PINCONF -+ select GPIO_REGMAP -+ select PINCONF -+ select PINMUX -+ - config PINCTRL_IPROC_GPIO - bool "Broadcom iProc GPIO (with PINCONF) driver" - depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) ---- a/drivers/pinctrl/bcm/Makefile -+++ b/drivers/pinctrl/bcm/Makefile -@@ -3,6 +3,7 @@ - - obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o - obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o -+obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o - obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o - obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o - obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o ---- /dev/null -+++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.c -@@ -0,0 +1,109 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Driver for BCM63xx GPIO unit (pinctrl + GPIO) -+ * -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> -+ */ -+ -+#include <linux/gpio/regmap.h> -+#include <linux/mfd/syscon.h> -+#include <linux/mod_devicetable.h> -+#include <linux/of.h> -+#include <linux/platform_device.h> -+ -+#include "pinctrl-bcm63xx.h" -+ -+#define BCM63XX_BANK_SIZE 4 -+ -+#define BCM63XX_DIROUT_REG 0x04 -+#define BCM63XX_DATA_REG 0x0c -+ -+static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio, -+ unsigned int base, unsigned int offset, -+ unsigned int *reg, unsigned int *mask) -+{ -+ unsigned int line = offset % BCM63XX_BANK_GPIOS; -+ unsigned int stride = offset / BCM63XX_BANK_GPIOS; -+ -+ *reg = base - stride * BCM63XX_BANK_SIZE; -+ *mask = BIT(line); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm63xx_gpio_of_match[] = { -+ { .compatible = "brcm,bcm6318-gpio", }, -+ { .compatible = "brcm,bcm6328-gpio", }, -+ { .compatible = "brcm,bcm6358-gpio", }, -+ { .compatible = "brcm,bcm6362-gpio", }, -+ { .compatible = "brcm,bcm6368-gpio", }, -+ { .compatible = "brcm,bcm63268-gpio", }, -+ { /* sentinel */ } -+}; -+ -+static int bcm63xx_gpio_probe(struct device *dev, struct device_node *node, -+ const struct bcm63xx_pinctrl_soc *soc, -+ struct bcm63xx_pinctrl *pc) -+{ -+ struct gpio_regmap_config grc = {0}; -+ -+ grc.parent = dev; -+ grc.fwnode = &node->fwnode; -+ grc.ngpio = soc->ngpios; -+ grc.ngpio_per_reg = BCM63XX_BANK_GPIOS; -+ grc.regmap = pc->regs; -+ grc.reg_dat_base = BCM63XX_DATA_REG; -+ grc.reg_dir_out_base = BCM63XX_DIROUT_REG; -+ grc.reg_set_base = BCM63XX_DATA_REG; -+ grc.reg_mask_xlate = bcm63xx_reg_mask_xlate; -+ -+ return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &grc)); -+} -+ -+int bcm63xx_pinctrl_probe(struct platform_device *pdev, -+ const struct bcm63xx_pinctrl_soc *soc, -+ void *driver_data) -+{ -+ struct device *dev = &pdev->dev; -+ struct bcm63xx_pinctrl *pc; -+ struct device_node *node; -+ int err; -+ -+ pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); -+ if (!pc) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, pc); -+ -+ pc->dev = dev; -+ pc->driver_data = driver_data; -+ -+ pc->regs = syscon_node_to_regmap(dev->parent->of_node); -+ if (IS_ERR(pc->regs)) -+ return PTR_ERR(pc->regs); -+ -+ pc->pctl_desc.name = dev_name(dev); -+ pc->pctl_desc.pins = soc->pins; -+ pc->pctl_desc.npins = soc->npins; -+ pc->pctl_desc.pctlops = soc->pctl_ops; -+ pc->pctl_desc.pmxops = soc->pmx_ops; -+ pc->pctl_desc.owner = THIS_MODULE; -+ -+ pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); -+ if (IS_ERR(pc->pctl_dev)) -+ return PTR_ERR(pc->pctl_dev); -+ -+ for_each_child_of_node(dev->parent->of_node, node) { -+ if (of_match_node(bcm63xx_gpio_of_match, node)) { -+ err = bcm63xx_gpio_probe(dev, node, soc, pc); -+ if (err) { -+ dev_err(dev, "could not add GPIO chip\n"); -+ of_node_put(node); -+ return err; -+ } -+ } -+ } -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h -@@ -0,0 +1,43 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> -+ */ -+ -+#ifndef __PINCTRL_BCM63XX_H__ -+#define __PINCTRL_BCM63XX_H__ -+ -+#include <linux/pinctrl/pinctrl.h> -+ -+#define BCM63XX_BANK_GPIOS 32 -+ -+struct bcm63xx_pinctrl_soc { -+ struct pinctrl_ops *pctl_ops; -+ struct pinmux_ops *pmx_ops; -+ -+ const struct pinctrl_pin_desc *pins; -+ unsigned npins; -+ -+ unsigned int ngpios; -+}; -+ -+struct bcm63xx_pinctrl { -+ struct device *dev; -+ struct regmap *regs; -+ -+ struct pinctrl_desc pctl_desc; -+ struct pinctrl_dev *pctl_dev; -+ -+ void *driver_data; -+}; -+ -+static inline unsigned int bcm63xx_bank_pin(unsigned int pin) -+{ -+ return pin % BCM63XX_BANK_GPIOS; -+} -+ -+int bcm63xx_pinctrl_probe(struct platform_device *pdev, -+ const struct bcm63xx_pinctrl_soc *soc, -+ void *driver_data); -+ -+#endif /* __PINCTRL_BCM63XX_H__ */ diff --git a/target/linux/bmips/patches-5.10/056-v5.13-dt-bindings-add-BCM6328-pincontroller-binding-docume.patch b/target/linux/bmips/patches-5.10/056-v5.13-dt-bindings-add-BCM6328-pincontroller-binding-docume.patch deleted file mode 100644 index af15da971f..0000000000 --- a/target/linux/bmips/patches-5.10/056-v5.13-dt-bindings-add-BCM6328-pincontroller-binding-docume.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 44dbcd8eb08a0febbb46ac7b9331f28a320bdf9a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:06 +0100 -Subject: [PATCH 05/22] dt-bindings: add BCM6328 pincontroller binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the pincontrol core found in BCM6328 SoCs. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-6-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../pinctrl/brcm,bcm6328-pinctrl.yaml | 127 ++++++++++++++++++ - 1 file changed, 127 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml -@@ -0,0 +1,127 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6328-pinctrl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6328 pin controller -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Bindings for Broadcom's BCM6328 memory-mapped pin controller. -+ -+properties: -+ compatible: -+ const: brcm,bcm6328-pinctrl -+ -+ reg: -+ maxItems: 1 -+ -+patternProperties: -+ '-pins$': -+ type: object -+ $ref: pinmux-node.yaml# -+ -+ properties: -+ function: -+ enum: [ serial_led_data, serial_led_clk, inet_act_led, pcie_clkreq, -+ led, ephy0_act_led, ephy1_act_led, ephy2_act_led, -+ ephy3_act_led, hsspi_cs1, usb_device_port, usb_host_port ] -+ -+ pins: -+ enum: [ gpio6, gpio7, gpio11, gpio16, gpio17, gpio18, gpio19, -+ gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1, -+ usb_port1 ] -+ -+required: -+ - compatible -+ - reg -+ -+additionalProperties: false -+ -+examples: -+ - | -+ pinctrl@18 { -+ compatible = "brcm,bcm6328-pinctrl"; -+ reg = <0x18 0x10>; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio7"; -+ }; -+ }; -+ -+ pinctrl_inet_act_led: inet_act_led-pins { -+ function = "inet_act_led"; -+ pins = "gpio11"; -+ }; -+ -+ pinctrl_pcie_clkreq: pcie_clkreq-pins { -+ function = "pcie_clkreq"; -+ pins = "gpio16"; -+ }; -+ -+ pinctrl_ephy0_spd_led: ephy0_spd_led-pins { -+ function = "led"; -+ pins = "gpio17"; -+ }; -+ -+ pinctrl_ephy1_spd_led: ephy1_spd_led-pins { -+ function = "led"; -+ pins = "gpio18"; -+ }; -+ -+ pinctrl_ephy2_spd_led: ephy2_spd_led-pins { -+ function = "led"; -+ pins = "gpio19"; -+ }; -+ -+ pinctrl_ephy3_spd_led: ephy3_spd_led-pins { -+ function = "led"; -+ pins = "gpio20"; -+ }; -+ -+ pinctrl_ephy0_act_led: ephy0_act_led-pins { -+ function = "ephy0_act_led"; -+ pins = "gpio25"; -+ }; -+ -+ pinctrl_ephy1_act_led: ephy1_act_led-pins { -+ function = "ephy1_act_led"; -+ pins = "gpio26"; -+ }; -+ -+ pinctrl_ephy2_act_led: ephy2_act_led-pins { -+ function = "ephy2_act_led"; -+ pins = "gpio27"; -+ }; -+ -+ pinctrl_ephy3_act_led: ephy3_act_led-pins { -+ function = "ephy3_act_led"; -+ pins = "gpio28"; -+ }; -+ -+ pinctrl_hsspi_cs1: hsspi_cs1-pins { -+ function = "hsspi_cs1"; -+ pins = "hsspi_cs1"; -+ }; -+ -+ pinctrl_usb_port1_device: usb_port1_device-pins { -+ function = "usb_device_port"; -+ pins = "usb_port1"; -+ }; -+ -+ pinctrl_usb_port1_host: usb_port1_host-pins { -+ function = "usb_host_port"; -+ pins = "usb_port1"; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/057-v5.13-dt-bindings-add-BCM6328-GPIO-sysctl-binding-document.patch b/target/linux/bmips/patches-5.10/057-v5.13-dt-bindings-add-BCM6328-GPIO-sysctl-binding-document.patch deleted file mode 100644 index 3c1e48d300..0000000000 --- a/target/linux/bmips/patches-5.10/057-v5.13-dt-bindings-add-BCM6328-GPIO-sysctl-binding-document.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 7f9dfaa2afb6bc3481e531c405b05acf6091af29 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:07 +0100 -Subject: [PATCH 06/22] dt-bindings: add BCM6328 GPIO sysctl binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the GPIO sysctl found in BCM6328 SoCs. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-7-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../mfd/brcm,bcm6328-gpio-sysctl.yaml | 162 ++++++++++++++++++ - 1 file changed, 162 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml -@@ -0,0 +1,162 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6328 GPIO System Controller Device Tree Bindings -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Broadcom BCM6328 SoC GPIO system controller which provides a register map -+ for controlling the GPIO and pins of the SoC. -+ -+properties: -+ "#address-cells": true -+ -+ "#size-cells": true -+ -+ compatible: -+ items: -+ - const: brcm,bcm6328-gpio-sysctl -+ - const: syscon -+ - const: simple-mfd -+ -+ ranges: -+ maxItems: 1 -+ -+ reg: -+ maxItems: 1 -+ -+patternProperties: -+ "^gpio@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../gpio/brcm,bcm6345-gpio.yaml" -+ description: -+ GPIO controller for the SoC GPIOs. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. -+ -+ "^pinctrl@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../pinctrl/brcm,bcm6328-pinctrl.yaml" -+ description: -+ Pin controller for the SoC pins. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml. -+ -+required: -+ - "#address-cells" -+ - compatible -+ - ranges -+ - reg -+ - "#size-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ syscon@10000080 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "brcm,bcm6328-gpio-sysctl", "syscon", "simple-mfd"; -+ reg = <0x10000080 0x80>; -+ ranges = <0 0x10000080 0x80>; -+ -+ gpio@0 { -+ compatible = "brcm,bcm6328-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0x0 0x8>, <0x8 0x8>; -+ -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 0 32>; -+ #gpio-cells = <2>; -+ }; -+ -+ pinctrl: pinctrl@18 { -+ compatible = "brcm,bcm6328-pinctrl"; -+ reg = <0x18 0x10>; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio7"; -+ }; -+ }; -+ -+ pinctrl_inet_act_led: inet_act_led-pins { -+ function = "inet_act_led"; -+ pins = "gpio11"; -+ }; -+ -+ pinctrl_pcie_clkreq: pcie_clkreq-pins { -+ function = "pcie_clkreq"; -+ pins = "gpio16"; -+ }; -+ -+ pinctrl_ephy0_spd_led: ephy0_spd_led-pins { -+ function = "led"; -+ pins = "gpio17"; -+ }; -+ -+ pinctrl_ephy1_spd_led: ephy1_spd_led-pins { -+ function = "led"; -+ pins = "gpio18"; -+ }; -+ -+ pinctrl_ephy2_spd_led: ephy2_spd_led-pins { -+ function = "led"; -+ pins = "gpio19"; -+ }; -+ -+ pinctrl_ephy3_spd_led: ephy3_spd_led-pins { -+ function = "led"; -+ pins = "gpio20"; -+ }; -+ -+ pinctrl_ephy0_act_led: ephy0_act_led-pins { -+ function = "ephy0_act_led"; -+ pins = "gpio25"; -+ }; -+ -+ pinctrl_ephy1_act_led: ephy1_act_led-pins { -+ function = "ephy1_act_led"; -+ pins = "gpio26"; -+ }; -+ -+ pinctrl_ephy2_act_led: ephy2_act_led-pins { -+ function = "ephy2_act_led"; -+ pins = "gpio27"; -+ }; -+ -+ pinctrl_ephy3_act_led: ephy3_act_led-pins { -+ function = "ephy3_act_led"; -+ pins = "gpio28"; -+ }; -+ -+ pinctrl_hsspi_cs1: hsspi_cs1-pins { -+ function = "hsspi_cs1"; -+ pins = "hsspi_cs1"; -+ }; -+ -+ pinctrl_usb_port1_device: usb_port1_device-pins { -+ function = "usb_device_port"; -+ pins = "usb_port1"; -+ }; -+ -+ pinctrl_usb_port1_host: usb_port1_host-pins { -+ function = "usb_host_port"; -+ pins = "usb_port1"; -+ }; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/058-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6328.patch b/target/linux/bmips/patches-5.10/058-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6328.patch deleted file mode 100644 index 90929d8d1f..0000000000 --- a/target/linux/bmips/patches-5.10/058-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6328.patch +++ /dev/null @@ -1,459 +0,0 @@ -From 9bf34ac5ab5805f0a798d40423c05596b7a0cee6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:08 +0100 -Subject: [PATCH 07/22] pinctrl: add a pincontrol driver for BCM6328 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add a pincontrol driver for BCM6328. BCM6328 supports muxing 32 pins as -GPIOs, as LEDs for the integrated LED controller, or various other -functions. Its pincontrol mux registers also control other aspects, like -switching the second USB port between host and device mode. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210324081923.20379-8-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/bcm/Kconfig | 8 + - drivers/pinctrl/bcm/Makefile | 1 + - drivers/pinctrl/bcm/pinctrl-bcm6328.c | 404 ++++++++++++++++++++++++++ - 3 files changed, 413 insertions(+) - create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6328.c - ---- a/drivers/pinctrl/bcm/Kconfig -+++ b/drivers/pinctrl/bcm/Kconfig -@@ -36,6 +36,14 @@ config PINCTRL_BCM63XX - select PINCONF - select PINMUX - -+config PINCTRL_BCM6328 -+ bool "Broadcom BCM6328 GPIO driver" -+ depends on (BMIPS_GENERIC || COMPILE_TEST) -+ select PINCTRL_BCM63XX -+ default BMIPS_GENERIC -+ help -+ Say Y here to enable the Broadcom BCM6328 GPIO driver. -+ - config PINCTRL_IPROC_GPIO - bool "Broadcom iProc GPIO (with PINCONF) driver" - depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) ---- a/drivers/pinctrl/bcm/Makefile -+++ b/drivers/pinctrl/bcm/Makefile -@@ -4,6 +4,7 @@ - obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o - obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o - obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o -+obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o - obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o - obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o - obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o ---- /dev/null -+++ b/drivers/pinctrl/bcm/pinctrl-bcm6328.c -@@ -0,0 +1,404 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Driver for BCM6328 GPIO unit (pinctrl + GPIO) -+ * -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> -+ */ -+ -+#include <linux/bits.h> -+#include <linux/gpio/driver.h> -+#include <linux/kernel.h> -+#include <linux/of.h> -+#include <linux/pinctrl/pinmux.h> -+#include <linux/platform_device.h> -+#include <linux/regmap.h> -+ -+#include "../pinctrl-utils.h" -+ -+#include "pinctrl-bcm63xx.h" -+ -+#define BCM6328_NUM_GPIOS 32 -+ -+#define BCM6328_MODE_REG 0x18 -+#define BCM6328_MUX_HI_REG 0x1c -+#define BCM6328_MUX_LO_REG 0x20 -+#define BCM6328_MUX_OTHER_REG 0x24 -+#define BCM6328_MUX_MASK GENMASK(1, 0) -+ -+struct bcm6328_pingroup { -+ const char *name; -+ const unsigned * const pins; -+ const unsigned num_pins; -+}; -+ -+struct bcm6328_function { -+ const char *name; -+ const char * const *groups; -+ const unsigned num_groups; -+ -+ unsigned mode_val:1; -+ unsigned mux_val:2; -+}; -+ -+static const unsigned int bcm6328_mux[] = { -+ BCM6328_MUX_LO_REG, -+ BCM6328_MUX_HI_REG, -+ BCM6328_MUX_OTHER_REG -+}; -+ -+static const struct pinctrl_pin_desc bcm6328_pins[] = { -+ PINCTRL_PIN(0, "gpio0"), -+ PINCTRL_PIN(1, "gpio1"), -+ PINCTRL_PIN(2, "gpio2"), -+ PINCTRL_PIN(3, "gpio3"), -+ PINCTRL_PIN(4, "gpio4"), -+ PINCTRL_PIN(5, "gpio5"), -+ PINCTRL_PIN(6, "gpio6"), -+ PINCTRL_PIN(7, "gpio7"), -+ PINCTRL_PIN(8, "gpio8"), -+ PINCTRL_PIN(9, "gpio9"), -+ PINCTRL_PIN(10, "gpio10"), -+ PINCTRL_PIN(11, "gpio11"), -+ PINCTRL_PIN(12, "gpio12"), -+ PINCTRL_PIN(13, "gpio13"), -+ PINCTRL_PIN(14, "gpio14"), -+ PINCTRL_PIN(15, "gpio15"), -+ PINCTRL_PIN(16, "gpio16"), -+ PINCTRL_PIN(17, "gpio17"), -+ PINCTRL_PIN(18, "gpio18"), -+ PINCTRL_PIN(19, "gpio19"), -+ PINCTRL_PIN(20, "gpio20"), -+ PINCTRL_PIN(21, "gpio21"), -+ PINCTRL_PIN(22, "gpio22"), -+ PINCTRL_PIN(23, "gpio23"), -+ PINCTRL_PIN(24, "gpio24"), -+ PINCTRL_PIN(25, "gpio25"), -+ PINCTRL_PIN(26, "gpio26"), -+ PINCTRL_PIN(27, "gpio27"), -+ PINCTRL_PIN(28, "gpio28"), -+ PINCTRL_PIN(29, "gpio29"), -+ PINCTRL_PIN(30, "gpio30"), -+ PINCTRL_PIN(31, "gpio31"), -+ -+ /* -+ * No idea where they really are; so let's put them according -+ * to their mux offsets. -+ */ -+ PINCTRL_PIN(36, "hsspi_cs1"), -+ PINCTRL_PIN(38, "usb_p2"), -+}; -+ -+static unsigned gpio0_pins[] = { 0 }; -+static unsigned gpio1_pins[] = { 1 }; -+static unsigned gpio2_pins[] = { 2 }; -+static unsigned gpio3_pins[] = { 3 }; -+static unsigned gpio4_pins[] = { 4 }; -+static unsigned gpio5_pins[] = { 5 }; -+static unsigned gpio6_pins[] = { 6 }; -+static unsigned gpio7_pins[] = { 7 }; -+static unsigned gpio8_pins[] = { 8 }; -+static unsigned gpio9_pins[] = { 9 }; -+static unsigned gpio10_pins[] = { 10 }; -+static unsigned gpio11_pins[] = { 11 }; -+static unsigned gpio12_pins[] = { 12 }; -+static unsigned gpio13_pins[] = { 13 }; -+static unsigned gpio14_pins[] = { 14 }; -+static unsigned gpio15_pins[] = { 15 }; -+static unsigned gpio16_pins[] = { 16 }; -+static unsigned gpio17_pins[] = { 17 }; -+static unsigned gpio18_pins[] = { 18 }; -+static unsigned gpio19_pins[] = { 19 }; -+static unsigned gpio20_pins[] = { 20 }; -+static unsigned gpio21_pins[] = { 21 }; -+static unsigned gpio22_pins[] = { 22 }; -+static unsigned gpio23_pins[] = { 23 }; -+static unsigned gpio24_pins[] = { 24 }; -+static unsigned gpio25_pins[] = { 25 }; -+static unsigned gpio26_pins[] = { 26 }; -+static unsigned gpio27_pins[] = { 27 }; -+static unsigned gpio28_pins[] = { 28 }; -+static unsigned gpio29_pins[] = { 29 }; -+static unsigned gpio30_pins[] = { 30 }; -+static unsigned gpio31_pins[] = { 31 }; -+ -+static unsigned hsspi_cs1_pins[] = { 36 }; -+static unsigned usb_port1_pins[] = { 38 }; -+ -+#define BCM6328_GROUP(n) \ -+ { \ -+ .name = #n, \ -+ .pins = n##_pins, \ -+ .num_pins = ARRAY_SIZE(n##_pins), \ -+ } -+ -+static struct bcm6328_pingroup bcm6328_groups[] = { -+ BCM6328_GROUP(gpio0), -+ BCM6328_GROUP(gpio1), -+ BCM6328_GROUP(gpio2), -+ BCM6328_GROUP(gpio3), -+ BCM6328_GROUP(gpio4), -+ BCM6328_GROUP(gpio5), -+ BCM6328_GROUP(gpio6), -+ BCM6328_GROUP(gpio7), -+ BCM6328_GROUP(gpio8), -+ BCM6328_GROUP(gpio9), -+ BCM6328_GROUP(gpio10), -+ BCM6328_GROUP(gpio11), -+ BCM6328_GROUP(gpio12), -+ BCM6328_GROUP(gpio13), -+ BCM6328_GROUP(gpio14), -+ BCM6328_GROUP(gpio15), -+ BCM6328_GROUP(gpio16), -+ BCM6328_GROUP(gpio17), -+ BCM6328_GROUP(gpio18), -+ BCM6328_GROUP(gpio19), -+ BCM6328_GROUP(gpio20), -+ BCM6328_GROUP(gpio21), -+ BCM6328_GROUP(gpio22), -+ BCM6328_GROUP(gpio23), -+ BCM6328_GROUP(gpio24), -+ BCM6328_GROUP(gpio25), -+ BCM6328_GROUP(gpio26), -+ BCM6328_GROUP(gpio27), -+ BCM6328_GROUP(gpio28), -+ BCM6328_GROUP(gpio29), -+ BCM6328_GROUP(gpio30), -+ BCM6328_GROUP(gpio31), -+ -+ BCM6328_GROUP(hsspi_cs1), -+ BCM6328_GROUP(usb_port1), -+}; -+ -+/* GPIO_MODE */ -+static const char * const led_groups[] = { -+ "gpio0", -+ "gpio1", -+ "gpio2", -+ "gpio3", -+ "gpio4", -+ "gpio5", -+ "gpio6", -+ "gpio7", -+ "gpio8", -+ "gpio9", -+ "gpio10", -+ "gpio11", -+ "gpio12", -+ "gpio13", -+ "gpio14", -+ "gpio15", -+ "gpio16", -+ "gpio17", -+ "gpio18", -+ "gpio19", -+ "gpio20", -+ "gpio21", -+ "gpio22", -+ "gpio23", -+}; -+ -+/* PINMUX_SEL */ -+static const char * const serial_led_data_groups[] = { -+ "gpio6", -+}; -+ -+static const char * const serial_led_clk_groups[] = { -+ "gpio7", -+}; -+ -+static const char * const inet_act_led_groups[] = { -+ "gpio11", -+}; -+ -+static const char * const pcie_clkreq_groups[] = { -+ "gpio16", -+}; -+ -+static const char * const ephy0_act_led_groups[] = { -+ "gpio25", -+}; -+ -+static const char * const ephy1_act_led_groups[] = { -+ "gpio26", -+}; -+ -+static const char * const ephy2_act_led_groups[] = { -+ "gpio27", -+}; -+ -+static const char * const ephy3_act_led_groups[] = { -+ "gpio28", -+}; -+ -+static const char * const hsspi_cs1_groups[] = { -+ "hsspi_cs1" -+}; -+ -+static const char * const usb_host_port_groups[] = { -+ "usb_port1", -+}; -+ -+static const char * const usb_device_port_groups[] = { -+ "usb_port1", -+}; -+ -+#define BCM6328_MODE_FUN(n) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .mode_val = 1, \ -+ } -+ -+#define BCM6328_MUX_FUN(n, mux) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .mux_val = mux, \ -+ } -+ -+static const struct bcm6328_function bcm6328_funcs[] = { -+ BCM6328_MODE_FUN(led), -+ BCM6328_MUX_FUN(serial_led_data, 2), -+ BCM6328_MUX_FUN(serial_led_clk, 2), -+ BCM6328_MUX_FUN(inet_act_led, 1), -+ BCM6328_MUX_FUN(pcie_clkreq, 2), -+ BCM6328_MUX_FUN(ephy0_act_led, 1), -+ BCM6328_MUX_FUN(ephy1_act_led, 1), -+ BCM6328_MUX_FUN(ephy2_act_led, 1), -+ BCM6328_MUX_FUN(ephy3_act_led, 1), -+ BCM6328_MUX_FUN(hsspi_cs1, 2), -+ BCM6328_MUX_FUN(usb_host_port, 1), -+ BCM6328_MUX_FUN(usb_device_port, 2), -+}; -+ -+static inline unsigned int bcm6328_mux_off(unsigned int pin) -+{ -+ return bcm6328_mux[pin / 16]; -+} -+ -+static int bcm6328_pinctrl_get_group_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6328_groups); -+} -+ -+static const char *bcm6328_pinctrl_get_group_name(struct pinctrl_dev *pctldev, -+ unsigned group) -+{ -+ return bcm6328_groups[group].name; -+} -+ -+static int bcm6328_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, -+ unsigned group, const unsigned **pins, -+ unsigned *num_pins) -+{ -+ *pins = bcm6328_groups[group].pins; -+ *num_pins = bcm6328_groups[group].num_pins; -+ -+ return 0; -+} -+ -+static int bcm6328_pinctrl_get_func_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6328_funcs); -+} -+ -+static const char *bcm6328_pinctrl_get_func_name(struct pinctrl_dev *pctldev, -+ unsigned selector) -+{ -+ return bcm6328_funcs[selector].name; -+} -+ -+static int bcm6328_pinctrl_get_groups(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ const char * const **groups, -+ unsigned * const num_groups) -+{ -+ *groups = bcm6328_funcs[selector].groups; -+ *num_groups = bcm6328_funcs[selector].num_groups; -+ -+ return 0; -+} -+ -+static void bcm6328_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin, -+ unsigned int mode, unsigned int mux) -+{ -+ if (pin < BCM6328_NUM_GPIOS) -+ regmap_update_bits(pc->regs, BCM6328_MODE_REG, BIT(pin), -+ mode ? BIT(pin) : 0); -+ -+ regmap_update_bits(pc->regs, bcm6328_mux_off(pin), -+ BCM6328_MUX_MASK << ((pin % 16) * 2), -+ mux << ((pin % 16) * 2)); -+} -+ -+static int bcm6328_pinctrl_set_mux(struct pinctrl_dev *pctldev, -+ unsigned selector, unsigned group) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ const struct bcm6328_pingroup *pg = &bcm6328_groups[group]; -+ const struct bcm6328_function *f = &bcm6328_funcs[selector]; -+ -+ bcm6328_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val); -+ -+ return 0; -+} -+ -+static int bcm6328_gpio_request_enable(struct pinctrl_dev *pctldev, -+ struct pinctrl_gpio_range *range, -+ unsigned offset) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ -+ /* disable all functions using this pin */ -+ bcm6328_rmw_mux(pc, offset, 0, 0); -+ -+ return 0; -+} -+ -+static struct pinctrl_ops bcm6328_pctl_ops = { -+ .dt_free_map = pinctrl_utils_free_map, -+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, -+ .get_group_name = bcm6328_pinctrl_get_group_name, -+ .get_group_pins = bcm6328_pinctrl_get_group_pins, -+ .get_groups_count = bcm6328_pinctrl_get_group_count, -+}; -+ -+static struct pinmux_ops bcm6328_pmx_ops = { -+ .get_function_groups = bcm6328_pinctrl_get_groups, -+ .get_function_name = bcm6328_pinctrl_get_func_name, -+ .get_functions_count = bcm6328_pinctrl_get_func_count, -+ .gpio_request_enable = bcm6328_gpio_request_enable, -+ .set_mux = bcm6328_pinctrl_set_mux, -+ .strict = true, -+}; -+ -+static const struct bcm63xx_pinctrl_soc bcm6328_soc = { -+ .ngpios = BCM6328_NUM_GPIOS, -+ .npins = ARRAY_SIZE(bcm6328_pins), -+ .pctl_ops = &bcm6328_pctl_ops, -+ .pins = bcm6328_pins, -+ .pmx_ops = &bcm6328_pmx_ops, -+}; -+ -+static int bcm6328_pinctrl_probe(struct platform_device *pdev) -+{ -+ return bcm63xx_pinctrl_probe(pdev, &bcm6328_soc, NULL); -+} -+ -+static const struct of_device_id bcm6328_pinctrl_match[] = { -+ { .compatible = "brcm,bcm6328-pinctrl", }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver bcm6328_pinctrl_driver = { -+ .probe = bcm6328_pinctrl_probe, -+ .driver = { -+ .name = "bcm6328-pinctrl", -+ .of_match_table = bcm6328_pinctrl_match, -+ }, -+}; -+ -+builtin_platform_driver(bcm6328_pinctrl_driver); diff --git a/target/linux/bmips/patches-5.10/059-v5.13-dt-bindings-add-BCM6358-pincontroller-binding-docume.patch b/target/linux/bmips/patches-5.10/059-v5.13-dt-bindings-add-BCM6358-pincontroller-binding-docume.patch deleted file mode 100644 index 001f94c5a5..0000000000 --- a/target/linux/bmips/patches-5.10/059-v5.13-dt-bindings-add-BCM6358-pincontroller-binding-docume.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 6d591614bfe881bb7664c9bebb6a48231c059411 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:09 +0100 -Subject: [PATCH 08/22] dt-bindings: add BCM6358 pincontroller binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the pincontrol core found in BCM6358 SoCs. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-9-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../pinctrl/brcm,bcm6358-pinctrl.yaml | 93 +++++++++++++++++++ - 1 file changed, 93 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml -@@ -0,0 +1,93 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6358-pinctrl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6358 pin controller -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Bindings for Broadcom's BCM6358 memory-mapped pin controller. -+ -+properties: -+ compatible: -+ const: brcm,bcm6358-pinctrl -+ -+ reg: -+ maxItems: 1 -+ -+patternProperties: -+ '-pins$': -+ type: object -+ $ref: pinmux-node.yaml# -+ -+ properties: -+ function: -+ enum: [ ebi_cs, uart1, serial_led, legacy_led, led, spi_cs, utopia, -+ pwm_syn_clk, sys_irq ] -+ -+ pins: -+ enum: [ ebi_cs_grp, uart1_grp, serial_led_grp, legacy_led_grp, -+ led_grp, spi_cs_grp, utopia_grp, pwm_syn_clk, sys_irq_grp ] -+ -+required: -+ - compatible -+ - reg -+ -+additionalProperties: false -+ -+examples: -+ - | -+ pinctrl@18 { -+ compatible = "brcm,bcm6358-pinctrl"; -+ reg = <0x18 0x4>; -+ -+ pinctrl_ebi_cs: ebi_cs-pins { -+ function = "ebi_cs"; -+ groups = "ebi_cs_grp"; -+ }; -+ -+ pinctrl_uart1: uart1-pins { -+ function = "uart1"; -+ groups = "uart1_grp"; -+ }; -+ -+ pinctrl_serial_led: serial_led-pins { -+ function = "serial_led"; -+ groups = "serial_led_grp"; -+ }; -+ -+ pinctrl_legacy_led: legacy_led-pins { -+ function = "legacy_led"; -+ groups = "legacy_led_grp"; -+ }; -+ -+ pinctrl_led: led-pins { -+ function = "led"; -+ groups = "led_grp"; -+ }; -+ -+ pinctrl_spi_cs_23: spi_cs-pins { -+ function = "spi_cs"; -+ groups = "spi_cs_grp"; -+ }; -+ -+ pinctrl_utopia: utopia-pins { -+ function = "utopia"; -+ groups = "utopia_grp"; -+ }; -+ -+ pinctrl_pwm_syn_clk: pwm_syn_clk-pins { -+ function = "pwm_syn_clk"; -+ groups = "pwm_syn_clk_grp"; -+ }; -+ -+ pinctrl_sys_irq: sys_irq-pins { -+ function = "sys_irq"; -+ groups = "sys_irq_grp"; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/060-v5.13-dt-bindings-add-BCM6358-GPIO-sysctl-binding-document.patch b/target/linux/bmips/patches-5.10/060-v5.13-dt-bindings-add-BCM6358-GPIO-sysctl-binding-document.patch deleted file mode 100644 index a36984e7ad..0000000000 --- a/target/linux/bmips/patches-5.10/060-v5.13-dt-bindings-add-BCM6358-GPIO-sysctl-binding-document.patch +++ /dev/null @@ -1,153 +0,0 @@ -From cfb1b98bc8d5ffd813428cb03c63b54cf63dd785 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:10 +0100 -Subject: [PATCH 09/22] dt-bindings: add BCM6358 GPIO sysctl binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the GPIO sysctl found in BCM6358 SoCs. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-10-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../mfd/brcm,bcm6358-gpio-sysctl.yaml | 130 ++++++++++++++++++ - 1 file changed, 130 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml -@@ -0,0 +1,130 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mfd/brcm,bcm6358-gpio-sysctl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6358 GPIO System Controller Device Tree Bindings -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Broadcom BCM6358 SoC GPIO system controller which provides a register map -+ for controlling the GPIO and pins of the SoC. -+ -+properties: -+ "#address-cells": true -+ -+ "#size-cells": true -+ -+ compatible: -+ items: -+ - const: brcm,bcm6358-gpio-sysctl -+ - const: syscon -+ - const: simple-mfd -+ -+ ranges: -+ maxItems: 1 -+ -+ reg: -+ maxItems: 1 -+ -+patternProperties: -+ "^gpio@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../gpio/brcm,bcm6345-gpio.yaml" -+ description: -+ GPIO controller for the SoC GPIOs. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. -+ -+ "^pinctrl@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../pinctrl/brcm,bcm6358-pinctrl.yaml" -+ description: -+ Pin controller for the SoC pins. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml. -+ -+required: -+ - "#address-cells" -+ - compatible -+ - ranges -+ - reg -+ - "#size-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ syscon@fffe0080 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "brcm,bcm6358-gpio-sysctl", "syscon", "simple-mfd"; -+ reg = <0xfffe0080 0x80>; -+ ranges = <0 0xfffe0080 0x80>; -+ -+ gpio@0 { -+ compatible = "brcm,bcm6358-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0x0 0x8>, <0x8 0x8>; -+ -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 0 40>; -+ #gpio-cells = <2>; -+ }; -+ -+ pinctrl: pinctrl@18 { -+ compatible = "brcm,bcm6358-pinctrl"; -+ reg = <0x18 0x4>; -+ -+ pinctrl_ebi_cs: ebi_cs-pins { -+ function = "ebi_cs"; -+ groups = "ebi_cs_grp"; -+ }; -+ -+ pinctrl_uart1: uart1-pins { -+ function = "uart1"; -+ groups = "uart1_grp"; -+ }; -+ -+ pinctrl_serial_led: serial_led-pins { -+ function = "serial_led"; -+ groups = "serial_led_grp"; -+ }; -+ -+ pinctrl_legacy_led: legacy_led-pins { -+ function = "legacy_led"; -+ groups = "legacy_led_grp"; -+ }; -+ -+ pinctrl_led: led-pins { -+ function = "led"; -+ groups = "led_grp"; -+ }; -+ -+ pinctrl_spi_cs_23: spi_cs-pins { -+ function = "spi_cs"; -+ groups = "spi_cs_grp"; -+ }; -+ -+ pinctrl_utopia: utopia-pins { -+ function = "utopia"; -+ groups = "utopia_grp"; -+ }; -+ -+ pinctrl_pwm_syn_clk: pwm_syn_clk-pins { -+ function = "pwm_syn_clk"; -+ groups = "pwm_syn_clk_grp"; -+ }; -+ -+ pinctrl_sys_irq: sys_irq-pins { -+ function = "sys_irq"; -+ groups = "sys_irq_grp"; -+ }; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/061-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6358.patch b/target/linux/bmips/patches-5.10/061-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6358.patch deleted file mode 100644 index 266ed686dc..0000000000 --- a/target/linux/bmips/patches-5.10/061-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6358.patch +++ /dev/null @@ -1,425 +0,0 @@ -From 9494b16976e1ae3afc643abf638a25f2ce4c3f2b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:11 +0100 -Subject: [PATCH 10/22] pinctrl: add a pincontrol driver for BCM6358 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add a pincotrol driver for BCM6358. BCM6358 allow overlaying different -functions onto the GPIO pins. It does not support configuring individual -pins but only whole groups. These groups may overlap, and still require -the directions to be set correctly in the GPIO register. In addition the -functions register controls other, not directly mux related functions. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210324081923.20379-11-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/bcm/Kconfig | 8 + - drivers/pinctrl/bcm/Makefile | 1 + - drivers/pinctrl/bcm/pinctrl-bcm6358.c | 369 ++++++++++++++++++++++++++ - 3 files changed, 378 insertions(+) - create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6358.c - ---- a/drivers/pinctrl/bcm/Kconfig -+++ b/drivers/pinctrl/bcm/Kconfig -@@ -44,6 +44,14 @@ config PINCTRL_BCM6328 - help - Say Y here to enable the Broadcom BCM6328 GPIO driver. - -+config PINCTRL_BCM6358 -+ bool "Broadcom BCM6358 GPIO driver" -+ depends on (BMIPS_GENERIC || COMPILE_TEST) -+ select PINCTRL_BCM63XX -+ default BMIPS_GENERIC -+ help -+ Say Y here to enable the Broadcom BCM6358 GPIO driver. -+ - config PINCTRL_IPROC_GPIO - bool "Broadcom iProc GPIO (with PINCONF) driver" - depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) ---- a/drivers/pinctrl/bcm/Makefile -+++ b/drivers/pinctrl/bcm/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinct - obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o - obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o - obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o -+obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o - obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o - obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o - obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o ---- /dev/null -+++ b/drivers/pinctrl/bcm/pinctrl-bcm6358.c -@@ -0,0 +1,369 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Driver for BCM6358 GPIO unit (pinctrl + GPIO) -+ * -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> -+ */ -+ -+#include <linux/bits.h> -+#include <linux/gpio/driver.h> -+#include <linux/kernel.h> -+#include <linux/of.h> -+#include <linux/pinctrl/pinmux.h> -+#include <linux/platform_device.h> -+#include <linux/regmap.h> -+ -+#include "../pinctrl-utils.h" -+ -+#include "pinctrl-bcm63xx.h" -+ -+#define BCM6358_NUM_GPIOS 40 -+ -+#define BCM6358_MODE_REG 0x18 -+#define BCM6358_MODE_MUX_NONE 0 -+#define BCM6358_MODE_MUX_EBI_CS BIT(5) -+#define BCM6358_MODE_MUX_UART1 BIT(6) -+#define BCM6358_MODE_MUX_SPI_CS BIT(7) -+#define BCM6358_MODE_MUX_ASYNC_MODEM BIT(8) -+#define BCM6358_MODE_MUX_LEGACY_LED BIT(9) -+#define BCM6358_MODE_MUX_SERIAL_LED BIT(10) -+#define BCM6358_MODE_MUX_LED BIT(11) -+#define BCM6358_MODE_MUX_UTOPIA BIT(12) -+#define BCM6358_MODE_MUX_CLKRST BIT(13) -+#define BCM6358_MODE_MUX_PWM_SYN_CLK BIT(14) -+#define BCM6358_MODE_MUX_SYS_IRQ BIT(15) -+ -+struct bcm6358_pingroup { -+ const char *name; -+ const unsigned * const pins; -+ const unsigned num_pins; -+ -+ const uint16_t mode_val; -+ -+ /* non-GPIO function muxes require the gpio direction to be set */ -+ const uint16_t direction; -+}; -+ -+struct bcm6358_function { -+ const char *name; -+ const char * const *groups; -+ const unsigned num_groups; -+}; -+ -+struct bcm6358_priv { -+ struct regmap_field *overlays; -+}; -+ -+#define BCM6358_GPIO_PIN(a, b, bit1, bit2, bit3) \ -+ { \ -+ .number = a, \ -+ .name = b, \ -+ .drv_data = (void *)(BCM6358_MODE_MUX_##bit1 | \ -+ BCM6358_MODE_MUX_##bit2 | \ -+ BCM6358_MODE_MUX_##bit3), \ -+ } -+ -+static const struct pinctrl_pin_desc bcm6358_pins[] = { -+ BCM6358_GPIO_PIN(0, "gpio0", LED, NONE, NONE), -+ BCM6358_GPIO_PIN(1, "gpio1", LED, NONE, NONE), -+ BCM6358_GPIO_PIN(2, "gpio2", LED, NONE, NONE), -+ BCM6358_GPIO_PIN(3, "gpio3", LED, NONE, NONE), -+ PINCTRL_PIN(4, "gpio4"), -+ BCM6358_GPIO_PIN(5, "gpio5", SYS_IRQ, NONE, NONE), -+ BCM6358_GPIO_PIN(6, "gpio6", SERIAL_LED, NONE, NONE), -+ BCM6358_GPIO_PIN(7, "gpio7", SERIAL_LED, NONE, NONE), -+ BCM6358_GPIO_PIN(8, "gpio8", PWM_SYN_CLK, NONE, NONE), -+ BCM6358_GPIO_PIN(9, "gpio09", LEGACY_LED, NONE, NONE), -+ BCM6358_GPIO_PIN(10, "gpio10", LEGACY_LED, NONE, NONE), -+ BCM6358_GPIO_PIN(11, "gpio11", LEGACY_LED, NONE, NONE), -+ BCM6358_GPIO_PIN(12, "gpio12", LEGACY_LED, ASYNC_MODEM, UTOPIA), -+ BCM6358_GPIO_PIN(13, "gpio13", LEGACY_LED, ASYNC_MODEM, UTOPIA), -+ BCM6358_GPIO_PIN(14, "gpio14", LEGACY_LED, ASYNC_MODEM, UTOPIA), -+ BCM6358_GPIO_PIN(15, "gpio15", LEGACY_LED, ASYNC_MODEM, UTOPIA), -+ PINCTRL_PIN(16, "gpio16"), -+ PINCTRL_PIN(17, "gpio17"), -+ PINCTRL_PIN(18, "gpio18"), -+ PINCTRL_PIN(19, "gpio19"), -+ PINCTRL_PIN(20, "gpio20"), -+ PINCTRL_PIN(21, "gpio21"), -+ BCM6358_GPIO_PIN(22, "gpio22", UTOPIA, NONE, NONE), -+ BCM6358_GPIO_PIN(23, "gpio23", UTOPIA, NONE, NONE), -+ BCM6358_GPIO_PIN(24, "gpio24", UTOPIA, NONE, NONE), -+ BCM6358_GPIO_PIN(25, "gpio25", UTOPIA, NONE, NONE), -+ BCM6358_GPIO_PIN(26, "gpio26", UTOPIA, NONE, NONE), -+ BCM6358_GPIO_PIN(27, "gpio27", UTOPIA, NONE, NONE), -+ BCM6358_GPIO_PIN(28, "gpio28", UTOPIA, UART1, NONE), -+ BCM6358_GPIO_PIN(29, "gpio29", UTOPIA, UART1, NONE), -+ BCM6358_GPIO_PIN(30, "gpio30", UTOPIA, UART1, EBI_CS), -+ BCM6358_GPIO_PIN(31, "gpio31", UTOPIA, UART1, EBI_CS), -+ BCM6358_GPIO_PIN(32, "gpio32", SPI_CS, NONE, NONE), -+ BCM6358_GPIO_PIN(33, "gpio33", SPI_CS, NONE, NONE), -+ PINCTRL_PIN(34, "gpio34"), -+ PINCTRL_PIN(35, "gpio35"), -+ PINCTRL_PIN(36, "gpio36"), -+ PINCTRL_PIN(37, "gpio37"), -+ PINCTRL_PIN(38, "gpio38"), -+ PINCTRL_PIN(39, "gpio39"), -+}; -+ -+static unsigned ebi_cs_grp_pins[] = { 30, 31 }; -+ -+static unsigned uart1_grp_pins[] = { 28, 29, 30, 31 }; -+ -+static unsigned spi_cs_grp_pins[] = { 32, 33 }; -+ -+static unsigned async_modem_grp_pins[] = { 12, 13, 14, 15 }; -+ -+static unsigned serial_led_grp_pins[] = { 6, 7 }; -+ -+static unsigned legacy_led_grp_pins[] = { 9, 10, 11, 12, 13, 14, 15 }; -+ -+static unsigned led_grp_pins[] = { 0, 1, 2, 3 }; -+ -+static unsigned utopia_grp_pins[] = { -+ 12, 13, 14, 15, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -+}; -+ -+static unsigned pwm_syn_clk_grp_pins[] = { 8 }; -+ -+static unsigned sys_irq_grp_pins[] = { 5 }; -+ -+#define BCM6358_GPIO_MUX_GROUP(n, bit, dir) \ -+ { \ -+ .name = #n, \ -+ .pins = n##_pins, \ -+ .num_pins = ARRAY_SIZE(n##_pins), \ -+ .mode_val = BCM6358_MODE_MUX_##bit, \ -+ .direction = dir, \ -+ } -+ -+static const struct bcm6358_pingroup bcm6358_groups[] = { -+ BCM6358_GPIO_MUX_GROUP(ebi_cs_grp, EBI_CS, 0x3), -+ BCM6358_GPIO_MUX_GROUP(uart1_grp, UART1, 0x2), -+ BCM6358_GPIO_MUX_GROUP(spi_cs_grp, SPI_CS, 0x6), -+ BCM6358_GPIO_MUX_GROUP(async_modem_grp, ASYNC_MODEM, 0x6), -+ BCM6358_GPIO_MUX_GROUP(legacy_led_grp, LEGACY_LED, 0x7f), -+ BCM6358_GPIO_MUX_GROUP(serial_led_grp, SERIAL_LED, 0x3), -+ BCM6358_GPIO_MUX_GROUP(led_grp, LED, 0xf), -+ BCM6358_GPIO_MUX_GROUP(utopia_grp, UTOPIA, 0x000f), -+ BCM6358_GPIO_MUX_GROUP(pwm_syn_clk_grp, PWM_SYN_CLK, 0x1), -+ BCM6358_GPIO_MUX_GROUP(sys_irq_grp, SYS_IRQ, 0x1), -+}; -+ -+static const char * const ebi_cs_groups[] = { -+ "ebi_cs_grp" -+}; -+ -+static const char * const uart1_groups[] = { -+ "uart1_grp" -+}; -+ -+static const char * const spi_cs_2_3_groups[] = { -+ "spi_cs_2_3_grp" -+}; -+ -+static const char * const async_modem_groups[] = { -+ "async_modem_grp" -+}; -+ -+static const char * const legacy_led_groups[] = { -+ "legacy_led_grp", -+}; -+ -+static const char * const serial_led_groups[] = { -+ "serial_led_grp", -+}; -+ -+static const char * const led_groups[] = { -+ "led_grp", -+}; -+ -+static const char * const clkrst_groups[] = { -+ "clkrst_grp", -+}; -+ -+static const char * const pwm_syn_clk_groups[] = { -+ "pwm_syn_clk_grp", -+}; -+ -+static const char * const sys_irq_groups[] = { -+ "sys_irq_grp", -+}; -+ -+#define BCM6358_FUN(n) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ } -+ -+static const struct bcm6358_function bcm6358_funcs[] = { -+ BCM6358_FUN(ebi_cs), -+ BCM6358_FUN(uart1), -+ BCM6358_FUN(spi_cs_2_3), -+ BCM6358_FUN(async_modem), -+ BCM6358_FUN(legacy_led), -+ BCM6358_FUN(serial_led), -+ BCM6358_FUN(led), -+ BCM6358_FUN(clkrst), -+ BCM6358_FUN(pwm_syn_clk), -+ BCM6358_FUN(sys_irq), -+}; -+ -+static int bcm6358_pinctrl_get_group_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6358_groups); -+} -+ -+static const char *bcm6358_pinctrl_get_group_name(struct pinctrl_dev *pctldev, -+ unsigned group) -+{ -+ return bcm6358_groups[group].name; -+} -+ -+static int bcm6358_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, -+ unsigned group, const unsigned **pins, -+ unsigned *num_pins) -+{ -+ *pins = bcm6358_groups[group].pins; -+ *num_pins = bcm6358_groups[group].num_pins; -+ -+ return 0; -+} -+ -+static int bcm6358_pinctrl_get_func_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6358_funcs); -+} -+ -+static const char *bcm6358_pinctrl_get_func_name(struct pinctrl_dev *pctldev, -+ unsigned selector) -+{ -+ return bcm6358_funcs[selector].name; -+} -+ -+static int bcm6358_pinctrl_get_groups(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ const char * const **groups, -+ unsigned * const num_groups) -+{ -+ *groups = bcm6358_funcs[selector].groups; -+ *num_groups = bcm6358_funcs[selector].num_groups; -+ -+ return 0; -+} -+ -+static int bcm6358_pinctrl_set_mux(struct pinctrl_dev *pctldev, -+ unsigned selector, unsigned group) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ struct bcm6358_priv *priv = pc->driver_data; -+ const struct bcm6358_pingroup *pg = &bcm6358_groups[group]; -+ unsigned int val = pg->mode_val; -+ unsigned int mask = val; -+ unsigned pin; -+ -+ for (pin = 0; pin < pg->num_pins; pin++) -+ mask |= (unsigned long)bcm6358_pins[pin].drv_data; -+ -+ regmap_field_update_bits(priv->overlays, mask, val); -+ -+ for (pin = 0; pin < pg->num_pins; pin++) { -+ struct pinctrl_gpio_range *range; -+ unsigned int hw_gpio = bcm6358_pins[pin].number; -+ -+ range = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio); -+ if (range) { -+ struct gpio_chip *gc = range->gc; -+ -+ if (pg->direction & BIT(pin)) -+ gc->direction_output(gc, hw_gpio, 0); -+ else -+ gc->direction_input(gc, hw_gpio); -+ } -+ } -+ -+ return 0; -+} -+ -+static int bcm6358_gpio_request_enable(struct pinctrl_dev *pctldev, -+ struct pinctrl_gpio_range *range, -+ unsigned offset) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ struct bcm6358_priv *priv = pc->driver_data; -+ unsigned int mask; -+ -+ mask = (unsigned long) bcm6358_pins[offset].drv_data; -+ if (!mask) -+ return 0; -+ -+ /* disable all functions using this pin */ -+ return regmap_field_update_bits(priv->overlays, mask, 0); -+} -+ -+static struct pinctrl_ops bcm6358_pctl_ops = { -+ .dt_free_map = pinctrl_utils_free_map, -+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, -+ .get_group_name = bcm6358_pinctrl_get_group_name, -+ .get_group_pins = bcm6358_pinctrl_get_group_pins, -+ .get_groups_count = bcm6358_pinctrl_get_group_count, -+}; -+ -+static struct pinmux_ops bcm6358_pmx_ops = { -+ .get_function_groups = bcm6358_pinctrl_get_groups, -+ .get_function_name = bcm6358_pinctrl_get_func_name, -+ .get_functions_count = bcm6358_pinctrl_get_func_count, -+ .gpio_request_enable = bcm6358_gpio_request_enable, -+ .set_mux = bcm6358_pinctrl_set_mux, -+ .strict = true, -+}; -+ -+static const struct bcm63xx_pinctrl_soc bcm6358_soc = { -+ .ngpios = BCM6358_NUM_GPIOS, -+ .npins = ARRAY_SIZE(bcm6358_pins), -+ .pctl_ops = &bcm6358_pctl_ops, -+ .pins = bcm6358_pins, -+ .pmx_ops = &bcm6358_pmx_ops, -+}; -+ -+static int bcm6358_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct reg_field overlays = REG_FIELD(BCM6358_MODE_REG, 0, 15); -+ struct device *dev = &pdev->dev; -+ struct bcm63xx_pinctrl *pc; -+ struct bcm6358_priv *priv; -+ int err; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ err = bcm63xx_pinctrl_probe(pdev, &bcm6358_soc, (void *) priv); -+ if (err) -+ return err; -+ -+ pc = platform_get_drvdata(pdev); -+ -+ priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays); -+ if (IS_ERR(priv->overlays)) -+ return PTR_ERR(priv->overlays); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm6358_pinctrl_match[] = { -+ { .compatible = "brcm,bcm6358-pinctrl", }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver bcm6358_pinctrl_driver = { -+ .probe = bcm6358_pinctrl_probe, -+ .driver = { -+ .name = "bcm6358-pinctrl", -+ .of_match_table = bcm6358_pinctrl_match, -+ }, -+}; -+ -+builtin_platform_driver(bcm6358_pinctrl_driver); diff --git a/target/linux/bmips/patches-5.10/062-v5.13-dt-bindings-add-BCM6362-pincontroller-binding-docume.patch b/target/linux/bmips/patches-5.10/062-v5.13-dt-bindings-add-BCM6362-pincontroller-binding-docume.patch deleted file mode 100644 index afdfbff1c2..0000000000 --- a/target/linux/bmips/patches-5.10/062-v5.13-dt-bindings-add-BCM6362-pincontroller-binding-docume.patch +++ /dev/null @@ -1,231 +0,0 @@ -From 6e4b5e1fc77513359989112e002e08553d0d8d5c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:12 +0100 -Subject: [PATCH 11/22] dt-bindings: add BCM6362 pincontroller binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the pincontrol core found in BCM6362 SoCs. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-12-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../pinctrl/brcm,bcm6362-pinctrl.yaml | 206 ++++++++++++++++++ - 1 file changed, 206 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml -@@ -0,0 +1,206 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6362-pinctrl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6362 pin controller -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Bindings for Broadcom's BCM6362 memory-mapped pin controller. -+ -+properties: -+ compatible: -+ const: brcm,bcm6362-pinctrl -+ -+ reg: -+ maxItems: 2 -+ -+patternProperties: -+ '-pins$': -+ type: object -+ $ref: pinmux-node.yaml# -+ -+ properties: -+ function: -+ enum: [ usb_device_led, sys_irq, serial_led_clk, serial_led_data, -+ robosw_led_data, robosw_led_clk, robosw_led0, robosw_led1, -+ inet_led, spi_cs2, spi_cs3, ntr_pulse, uart1_scts, -+ uart1_srts, uart1_sdin, uart1_sdout, adsl_spi_miso, -+ adsl_spi_mosi, adsl_spi_clk, adsl_spi_cs, ephy0_led, -+ ephy1_led, ephy2_led, ephy3_led, ext_irq0, ext_irq1, -+ ext_irq2, ext_irq3, nand ] -+ -+ pins: -+ enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, -+ gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, -+ gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, -+ gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, nand_grp ] -+ -+required: -+ - compatible -+ - reg -+ -+additionalProperties: false -+ -+examples: -+ - | -+ pinctrl@18 { -+ compatible = "brcm,bcm6362-pinctrl"; -+ reg = <0x18 0x10>, <0x38 0x4>; -+ -+ pinctrl_usb_device_led: usb_device_led-pins { -+ function = "usb_device_led"; -+ pins = "gpio0"; -+ }; -+ -+ pinctrl_sys_irq: sys_irq-pins { -+ function = "sys_irq"; -+ pins = "gpio1"; -+ }; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio2"; -+ }; -+ -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio3"; -+ }; -+ }; -+ -+ pinctrl_robosw_led_data: robosw_led_data-pins { -+ function = "robosw_led_data"; -+ pins = "gpio4"; -+ }; -+ -+ pinctrl_robosw_led_clk: robosw_led_clk-pins { -+ function = "robosw_led_clk"; -+ pins = "gpio5"; -+ }; -+ -+ pinctrl_robosw_led0: robosw_led0-pins { -+ function = "robosw_led0"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_robosw_led1: robosw_led1-pins { -+ function = "robosw_led1"; -+ pins = "gpio7"; -+ }; -+ -+ pinctrl_inet_led: inet_led-pins { -+ function = "inet_led"; -+ pins = "gpio8"; -+ }; -+ -+ pinctrl_spi_cs2: spi_cs2-pins { -+ function = "spi_cs2"; -+ pins = "gpio9"; -+ }; -+ -+ pinctrl_spi_cs3: spi_cs3-pins { -+ function = "spi_cs3"; -+ pins = "gpio10"; -+ }; -+ -+ pinctrl_ntr_pulse: ntr_pulse-pins { -+ function = "ntr_pulse"; -+ pins = "gpio11"; -+ }; -+ -+ pinctrl_uart1_scts: uart1_scts-pins { -+ function = "uart1_scts"; -+ pins = "gpio12"; -+ }; -+ -+ pinctrl_uart1_srts: uart1_srts-pins { -+ function = "uart1_srts"; -+ pins = "gpio13"; -+ }; -+ -+ pinctrl_uart1: uart1-pins { -+ pinctrl_uart1_sdin: uart1_sdin-pins { -+ function = "uart1_sdin"; -+ pins = "gpio14"; -+ }; -+ -+ pinctrl_uart1_sdout: uart1_sdout-pins { -+ function = "uart1_sdout"; -+ pins = "gpio15"; -+ }; -+ }; -+ -+ pinctrl_adsl_spi: adsl_spi-pins { -+ pinctrl_adsl_spi_miso: adsl_spi_miso-pins { -+ function = "adsl_spi_miso"; -+ pins = "gpio16"; -+ }; -+ -+ pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins { -+ function = "adsl_spi_mosi"; -+ pins = "gpio17"; -+ }; -+ -+ pinctrl_adsl_spi_clk: adsl_spi_clk-pins { -+ function = "adsl_spi_clk"; -+ pins = "gpio18"; -+ }; -+ -+ pinctrl_adsl_spi_cs: adsl_spi_cs-pins { -+ function = "adsl_spi_cs"; -+ pins = "gpio19"; -+ }; -+ }; -+ -+ pinctrl_ephy0_led: ephy0_led-pins { -+ function = "ephy0_led"; -+ pins = "gpio20"; -+ }; -+ -+ pinctrl_ephy1_led: ephy1_led-pins { -+ function = "ephy1_led"; -+ pins = "gpio21"; -+ }; -+ -+ pinctrl_ephy2_led: ephy2_led-pins { -+ function = "ephy2_led"; -+ pins = "gpio22"; -+ }; -+ -+ pinctrl_ephy3_led: ephy3_led-pins { -+ function = "ephy3_led"; -+ pins = "gpio23"; -+ }; -+ -+ pinctrl_ext_irq0: ext_irq0-pins { -+ function = "ext_irq0"; -+ pins = "gpio24"; -+ }; -+ -+ pinctrl_ext_irq1: ext_irq1-pins { -+ function = "ext_irq1"; -+ pins = "gpio25"; -+ }; -+ -+ pinctrl_ext_irq2: ext_irq2-pins { -+ function = "ext_irq2"; -+ pins = "gpio26"; -+ }; -+ -+ pinctrl_ext_irq3: ext_irq3-pins { -+ function = "ext_irq3"; -+ pins = "gpio27"; -+ }; -+ -+ pinctrl_nand: nand-pins { -+ function = "nand"; -+ group = "nand_grp"; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/063-v5.13-dt-bindings-add-BCM6362-GPIO-sysctl-binding-document.patch b/target/linux/bmips/patches-5.10/063-v5.13-dt-bindings-add-BCM6362-GPIO-sysctl-binding-document.patch deleted file mode 100644 index db0952211e..0000000000 --- a/target/linux/bmips/patches-5.10/063-v5.13-dt-bindings-add-BCM6362-GPIO-sysctl-binding-document.patch +++ /dev/null @@ -1,259 +0,0 @@ -From 7ca989eafbd6ce1c216a775556c4893baab1959b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:13 +0100 -Subject: [PATCH 12/22] dt-bindings: add BCM6362 GPIO sysctl binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the GPIO sysctl found in BCM6362 SoCs. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-13-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../mfd/brcm,bcm6362-gpio-sysctl.yaml | 236 ++++++++++++++++++ - 1 file changed, 236 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml -@@ -0,0 +1,236 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6362 GPIO System Controller Device Tree Bindings -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Broadcom BCM6362 SoC GPIO system controller which provides a register map -+ for controlling the GPIO and pins of the SoC. -+ -+properties: -+ "#address-cells": true -+ -+ "#size-cells": true -+ -+ compatible: -+ items: -+ - const: brcm,bcm6362-gpio-sysctl -+ - const: syscon -+ - const: simple-mfd -+ -+ ranges: -+ maxItems: 1 -+ -+ reg: -+ maxItems: 1 -+ -+patternProperties: -+ "^gpio@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../gpio/brcm,bcm6345-gpio.yaml" -+ description: -+ GPIO controller for the SoC GPIOs. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. -+ -+ "^pinctrl@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../pinctrl/brcm,bcm6362-pinctrl.yaml" -+ description: -+ Pin controller for the SoC pins. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml. -+ -+required: -+ - "#address-cells" -+ - compatible -+ - ranges -+ - reg -+ - "#size-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ syscon@10000080 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "brcm,bcm6362-gpio-sysctl", "syscon", "simple-mfd"; -+ reg = <0x10000080 0x80>; -+ ranges = <0 0x10000080 0x80>; -+ -+ gpio@0 { -+ compatible = "brcm,bcm6362-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0x0 0x8>, <0x8 0x8>; -+ -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 0 48>; -+ #gpio-cells = <2>; -+ }; -+ -+ pinctrl: pinctrl@18 { -+ compatible = "brcm,bcm6362-pinctrl"; -+ reg = <0x18 0x10>, <0x38 0x4>; -+ -+ pinctrl_usb_device_led: usb_device_led-pins { -+ function = "usb_device_led"; -+ pins = "gpio0"; -+ }; -+ -+ pinctrl_sys_irq: sys_irq-pins { -+ function = "sys_irq"; -+ pins = "gpio1"; -+ }; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio2"; -+ }; -+ -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio3"; -+ }; -+ }; -+ -+ pinctrl_robosw_led_data: robosw_led_data-pins { -+ function = "robosw_led_data"; -+ pins = "gpio4"; -+ }; -+ -+ pinctrl_robosw_led_clk: robosw_led_clk-pins { -+ function = "robosw_led_clk"; -+ pins = "gpio5"; -+ }; -+ -+ pinctrl_robosw_led0: robosw_led0-pins { -+ function = "robosw_led0"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_robosw_led1: robosw_led1-pins { -+ function = "robosw_led1"; -+ pins = "gpio7"; -+ }; -+ -+ pinctrl_inet_led: inet_led-pins { -+ function = "inet_led"; -+ pins = "gpio8"; -+ }; -+ -+ pinctrl_spi_cs2: spi_cs2-pins { -+ function = "spi_cs2"; -+ pins = "gpio9"; -+ }; -+ -+ pinctrl_spi_cs3: spi_cs3-pins { -+ function = "spi_cs3"; -+ pins = "gpio10"; -+ }; -+ -+ pinctrl_ntr_pulse: ntr_pulse-pins { -+ function = "ntr_pulse"; -+ pins = "gpio11"; -+ }; -+ -+ pinctrl_uart1_scts: uart1_scts-pins { -+ function = "uart1_scts"; -+ pins = "gpio12"; -+ }; -+ -+ pinctrl_uart1_srts: uart1_srts-pins { -+ function = "uart1_srts"; -+ pins = "gpio13"; -+ }; -+ -+ pinctrl_uart1: uart1-pins { -+ pinctrl_uart1_sdin: uart1_sdin-pins { -+ function = "uart1_sdin"; -+ pins = "gpio14"; -+ }; -+ -+ pinctrl_uart1_sdout: uart1_sdout-pins { -+ function = "uart1_sdout"; -+ pins = "gpio15"; -+ }; -+ }; -+ -+ pinctrl_adsl_spi: adsl_spi-pins { -+ pinctrl_adsl_spi_miso: adsl_spi_miso-pins { -+ function = "adsl_spi_miso"; -+ pins = "gpio16"; -+ }; -+ -+ pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins { -+ function = "adsl_spi_mosi"; -+ pins = "gpio17"; -+ }; -+ -+ pinctrl_adsl_spi_clk: adsl_spi_clk-pins { -+ function = "adsl_spi_clk"; -+ pins = "gpio18"; -+ }; -+ -+ pinctrl_adsl_spi_cs: adsl_spi_cs-pins { -+ function = "adsl_spi_cs"; -+ pins = "gpio19"; -+ }; -+ }; -+ -+ pinctrl_ephy0_led: ephy0_led-pins { -+ function = "ephy0_led"; -+ pins = "gpio20"; -+ }; -+ -+ pinctrl_ephy1_led: ephy1_led-pins { -+ function = "ephy1_led"; -+ pins = "gpio21"; -+ }; -+ -+ pinctrl_ephy2_led: ephy2_led-pins { -+ function = "ephy2_led"; -+ pins = "gpio22"; -+ }; -+ -+ pinctrl_ephy3_led: ephy3_led-pins { -+ function = "ephy3_led"; -+ pins = "gpio23"; -+ }; -+ -+ pinctrl_ext_irq0: ext_irq0-pins { -+ function = "ext_irq0"; -+ pins = "gpio24"; -+ }; -+ -+ pinctrl_ext_irq1: ext_irq1-pins { -+ function = "ext_irq1"; -+ pins = "gpio25"; -+ }; -+ -+ pinctrl_ext_irq2: ext_irq2-pins { -+ function = "ext_irq2"; -+ pins = "gpio26"; -+ }; -+ -+ pinctrl_ext_irq3: ext_irq3-pins { -+ function = "ext_irq3"; -+ pins = "gpio27"; -+ }; -+ -+ pinctrl_nand: nand-pins { -+ function = "nand"; -+ group = "nand_grp"; -+ }; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/064-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6362.patch b/target/linux/bmips/patches-5.10/064-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6362.patch deleted file mode 100644 index dc775c3c2c..0000000000 --- a/target/linux/bmips/patches-5.10/064-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6362.patch +++ /dev/null @@ -1,672 +0,0 @@ -From 705791e23ecd93d6c2697234fdf0c22b499c0a5b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:14 +0100 -Subject: [PATCH 13/22] pinctrl: add a pincontrol driver for BCM6362 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add a pincotrol driver for BCM6362. BCM6362 allows muxing individual -GPIO pins to the LED controller, to be available by the integrated -wifi, or other functions. It also supports overlay groups, of which -only NAND is documented. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210324081923.20379-14-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/bcm/Kconfig | 8 + - drivers/pinctrl/bcm/Makefile | 1 + - drivers/pinctrl/bcm/pinctrl-bcm6362.c | 617 ++++++++++++++++++++++++++ - 3 files changed, 626 insertions(+) - create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6362.c - ---- a/drivers/pinctrl/bcm/Kconfig -+++ b/drivers/pinctrl/bcm/Kconfig -@@ -52,6 +52,14 @@ config PINCTRL_BCM6358 - help - Say Y here to enable the Broadcom BCM6358 GPIO driver. - -+config PINCTRL_BCM6362 -+ bool "Broadcom BCM6362 GPIO driver" -+ depends on (BMIPS_GENERIC || COMPILE_TEST) -+ select PINCTRL_BCM63XX -+ default BMIPS_GENERIC -+ help -+ Say Y here to enable the Broadcom BCM6362 GPIO driver. -+ - config PINCTRL_IPROC_GPIO - bool "Broadcom iProc GPIO (with PINCONF) driver" - depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) ---- a/drivers/pinctrl/bcm/Makefile -+++ b/drivers/pinctrl/bcm/Makefile -@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_BCM2835) += pinctr - obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o - obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o - obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o -+obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o - obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o - obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o - obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o ---- /dev/null -+++ b/drivers/pinctrl/bcm/pinctrl-bcm6362.c -@@ -0,0 +1,617 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Driver for BCM6362 GPIO unit (pinctrl + GPIO) -+ * -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> -+ */ -+ -+#include <linux/bits.h> -+#include <linux/gpio/driver.h> -+#include <linux/kernel.h> -+#include <linux/of.h> -+#include <linux/pinctrl/pinmux.h> -+#include <linux/platform_device.h> -+#include <linux/regmap.h> -+ -+#include "../pinctrl-utils.h" -+ -+#include "pinctrl-bcm63xx.h" -+ -+#define BCM6362_BANK_GPIOS 32 -+#define BCM6362_NUM_GPIOS 48 -+#define BCM6362_NUM_LEDS 24 -+ -+#define BCM6362_LED_REG 0x10 -+#define BCM6362_MODE_REG 0x18 -+#define BCM6362_CTRL_REG 0x1c -+#define BCM6362_BASEMODE_REG 0x38 -+#define BASEMODE_NAND BIT(2) -+ -+enum bcm6362_pinctrl_reg { -+ BCM6362_LEDCTRL, -+ BCM6362_MODE, -+ BCM6362_CTRL, -+ BCM6362_BASEMODE, -+}; -+ -+struct bcm6362_pingroup { -+ const char *name; -+ const unsigned * const pins; -+ const unsigned num_pins; -+}; -+ -+struct bcm6362_function { -+ const char *name; -+ const char * const *groups; -+ const unsigned num_groups; -+ -+ enum bcm6362_pinctrl_reg reg; -+ uint32_t basemode_mask; -+}; -+ -+#define BCM6362_PIN(a, b, mask) \ -+ { \ -+ .number = a, \ -+ .name = b, \ -+ .drv_data = (void *)(mask), \ -+ } -+ -+static const struct pinctrl_pin_desc bcm6362_pins[] = { -+ PINCTRL_PIN(0, "gpio0"), -+ PINCTRL_PIN(1, "gpio1"), -+ PINCTRL_PIN(2, "gpio2"), -+ PINCTRL_PIN(3, "gpio3"), -+ PINCTRL_PIN(4, "gpio4"), -+ PINCTRL_PIN(5, "gpio5"), -+ PINCTRL_PIN(6, "gpio6"), -+ PINCTRL_PIN(7, "gpio7"), -+ BCM6362_PIN(8, "gpio8", BASEMODE_NAND), -+ PINCTRL_PIN(9, "gpio9"), -+ PINCTRL_PIN(10, "gpio10"), -+ PINCTRL_PIN(11, "gpio11"), -+ BCM6362_PIN(12, "gpio12", BASEMODE_NAND), -+ BCM6362_PIN(13, "gpio13", BASEMODE_NAND), -+ BCM6362_PIN(14, "gpio14", BASEMODE_NAND), -+ BCM6362_PIN(15, "gpio15", BASEMODE_NAND), -+ BCM6362_PIN(16, "gpio16", BASEMODE_NAND), -+ BCM6362_PIN(17, "gpio17", BASEMODE_NAND), -+ BCM6362_PIN(18, "gpio18", BASEMODE_NAND), -+ BCM6362_PIN(19, "gpio19", BASEMODE_NAND), -+ BCM6362_PIN(20, "gpio20", BASEMODE_NAND), -+ BCM6362_PIN(21, "gpio21", BASEMODE_NAND), -+ BCM6362_PIN(22, "gpio22", BASEMODE_NAND), -+ BCM6362_PIN(23, "gpio23", BASEMODE_NAND), -+ PINCTRL_PIN(24, "gpio24"), -+ PINCTRL_PIN(25, "gpio25"), -+ PINCTRL_PIN(26, "gpio26"), -+ BCM6362_PIN(27, "gpio27", BASEMODE_NAND), -+ PINCTRL_PIN(28, "gpio28"), -+ PINCTRL_PIN(29, "gpio29"), -+ PINCTRL_PIN(30, "gpio30"), -+ PINCTRL_PIN(31, "gpio31"), -+ PINCTRL_PIN(32, "gpio32"), -+ PINCTRL_PIN(33, "gpio33"), -+ PINCTRL_PIN(34, "gpio34"), -+ PINCTRL_PIN(35, "gpio35"), -+ PINCTRL_PIN(36, "gpio36"), -+ PINCTRL_PIN(37, "gpio37"), -+ PINCTRL_PIN(38, "gpio38"), -+ PINCTRL_PIN(39, "gpio39"), -+ PINCTRL_PIN(40, "gpio40"), -+ PINCTRL_PIN(41, "gpio41"), -+ PINCTRL_PIN(42, "gpio42"), -+ PINCTRL_PIN(43, "gpio43"), -+ PINCTRL_PIN(44, "gpio44"), -+ PINCTRL_PIN(45, "gpio45"), -+ PINCTRL_PIN(46, "gpio46"), -+ PINCTRL_PIN(47, "gpio47"), -+}; -+ -+static unsigned gpio0_pins[] = { 0 }; -+static unsigned gpio1_pins[] = { 1 }; -+static unsigned gpio2_pins[] = { 2 }; -+static unsigned gpio3_pins[] = { 3 }; -+static unsigned gpio4_pins[] = { 4 }; -+static unsigned gpio5_pins[] = { 5 }; -+static unsigned gpio6_pins[] = { 6 }; -+static unsigned gpio7_pins[] = { 7 }; -+static unsigned gpio8_pins[] = { 8 }; -+static unsigned gpio9_pins[] = { 9 }; -+static unsigned gpio10_pins[] = { 10 }; -+static unsigned gpio11_pins[] = { 11 }; -+static unsigned gpio12_pins[] = { 12 }; -+static unsigned gpio13_pins[] = { 13 }; -+static unsigned gpio14_pins[] = { 14 }; -+static unsigned gpio15_pins[] = { 15 }; -+static unsigned gpio16_pins[] = { 16 }; -+static unsigned gpio17_pins[] = { 17 }; -+static unsigned gpio18_pins[] = { 18 }; -+static unsigned gpio19_pins[] = { 19 }; -+static unsigned gpio20_pins[] = { 20 }; -+static unsigned gpio21_pins[] = { 21 }; -+static unsigned gpio22_pins[] = { 22 }; -+static unsigned gpio23_pins[] = { 23 }; -+static unsigned gpio24_pins[] = { 24 }; -+static unsigned gpio25_pins[] = { 25 }; -+static unsigned gpio26_pins[] = { 26 }; -+static unsigned gpio27_pins[] = { 27 }; -+static unsigned gpio28_pins[] = { 28 }; -+static unsigned gpio29_pins[] = { 29 }; -+static unsigned gpio30_pins[] = { 30 }; -+static unsigned gpio31_pins[] = { 31 }; -+static unsigned gpio32_pins[] = { 32 }; -+static unsigned gpio33_pins[] = { 33 }; -+static unsigned gpio34_pins[] = { 34 }; -+static unsigned gpio35_pins[] = { 35 }; -+static unsigned gpio36_pins[] = { 36 }; -+static unsigned gpio37_pins[] = { 37 }; -+static unsigned gpio38_pins[] = { 38 }; -+static unsigned gpio39_pins[] = { 39 }; -+static unsigned gpio40_pins[] = { 40 }; -+static unsigned gpio41_pins[] = { 41 }; -+static unsigned gpio42_pins[] = { 42 }; -+static unsigned gpio43_pins[] = { 43 }; -+static unsigned gpio44_pins[] = { 44 }; -+static unsigned gpio45_pins[] = { 45 }; -+static unsigned gpio46_pins[] = { 46 }; -+static unsigned gpio47_pins[] = { 47 }; -+ -+static unsigned nand_grp_pins[] = { -+ 8, 12, 13, 14, 15, 16, 17, -+ 18, 19, 20, 21, 22, 23, 27, -+}; -+ -+#define BCM6362_GROUP(n) \ -+ { \ -+ .name = #n, \ -+ .pins = n##_pins, \ -+ .num_pins = ARRAY_SIZE(n##_pins), \ -+ } -+ -+static struct bcm6362_pingroup bcm6362_groups[] = { -+ BCM6362_GROUP(gpio0), -+ BCM6362_GROUP(gpio1), -+ BCM6362_GROUP(gpio2), -+ BCM6362_GROUP(gpio3), -+ BCM6362_GROUP(gpio4), -+ BCM6362_GROUP(gpio5), -+ BCM6362_GROUP(gpio6), -+ BCM6362_GROUP(gpio7), -+ BCM6362_GROUP(gpio8), -+ BCM6362_GROUP(gpio9), -+ BCM6362_GROUP(gpio10), -+ BCM6362_GROUP(gpio11), -+ BCM6362_GROUP(gpio12), -+ BCM6362_GROUP(gpio13), -+ BCM6362_GROUP(gpio14), -+ BCM6362_GROUP(gpio15), -+ BCM6362_GROUP(gpio16), -+ BCM6362_GROUP(gpio17), -+ BCM6362_GROUP(gpio18), -+ BCM6362_GROUP(gpio19), -+ BCM6362_GROUP(gpio20), -+ BCM6362_GROUP(gpio21), -+ BCM6362_GROUP(gpio22), -+ BCM6362_GROUP(gpio23), -+ BCM6362_GROUP(gpio24), -+ BCM6362_GROUP(gpio25), -+ BCM6362_GROUP(gpio26), -+ BCM6362_GROUP(gpio27), -+ BCM6362_GROUP(gpio28), -+ BCM6362_GROUP(gpio29), -+ BCM6362_GROUP(gpio30), -+ BCM6362_GROUP(gpio31), -+ BCM6362_GROUP(gpio32), -+ BCM6362_GROUP(gpio33), -+ BCM6362_GROUP(gpio34), -+ BCM6362_GROUP(gpio35), -+ BCM6362_GROUP(gpio36), -+ BCM6362_GROUP(gpio37), -+ BCM6362_GROUP(gpio38), -+ BCM6362_GROUP(gpio39), -+ BCM6362_GROUP(gpio40), -+ BCM6362_GROUP(gpio41), -+ BCM6362_GROUP(gpio42), -+ BCM6362_GROUP(gpio43), -+ BCM6362_GROUP(gpio44), -+ BCM6362_GROUP(gpio45), -+ BCM6362_GROUP(gpio46), -+ BCM6362_GROUP(gpio47), -+ BCM6362_GROUP(nand_grp), -+}; -+ -+static const char * const led_groups[] = { -+ "gpio0", -+ "gpio1", -+ "gpio2", -+ "gpio3", -+ "gpio4", -+ "gpio5", -+ "gpio6", -+ "gpio7", -+ "gpio8", -+ "gpio9", -+ "gpio10", -+ "gpio11", -+ "gpio12", -+ "gpio13", -+ "gpio14", -+ "gpio15", -+ "gpio16", -+ "gpio17", -+ "gpio18", -+ "gpio19", -+ "gpio20", -+ "gpio21", -+ "gpio22", -+ "gpio23", -+}; -+ -+static const char * const usb_device_led_groups[] = { -+ "gpio0", -+}; -+ -+static const char * const sys_irq_groups[] = { -+ "gpio1", -+}; -+ -+static const char * const serial_led_clk_groups[] = { -+ "gpio2", -+}; -+ -+static const char * const serial_led_data_groups[] = { -+ "gpio3", -+}; -+ -+static const char * const robosw_led_data_groups[] = { -+ "gpio4", -+}; -+ -+static const char * const robosw_led_clk_groups[] = { -+ "gpio5", -+}; -+ -+static const char * const robosw_led0_groups[] = { -+ "gpio6", -+}; -+ -+static const char * const robosw_led1_groups[] = { -+ "gpio7", -+}; -+ -+static const char * const inet_led_groups[] = { -+ "gpio8", -+}; -+ -+static const char * const spi_cs2_groups[] = { -+ "gpio9", -+}; -+ -+static const char * const spi_cs3_groups[] = { -+ "gpio10", -+}; -+ -+static const char * const ntr_pulse_groups[] = { -+ "gpio11", -+}; -+ -+static const char * const uart1_scts_groups[] = { -+ "gpio12", -+}; -+ -+static const char * const uart1_srts_groups[] = { -+ "gpio13", -+}; -+ -+static const char * const uart1_sdin_groups[] = { -+ "gpio14", -+}; -+ -+static const char * const uart1_sdout_groups[] = { -+ "gpio15", -+}; -+ -+static const char * const adsl_spi_miso_groups[] = { -+ "gpio16", -+}; -+ -+static const char * const adsl_spi_mosi_groups[] = { -+ "gpio17", -+}; -+ -+static const char * const adsl_spi_clk_groups[] = { -+ "gpio18", -+}; -+ -+static const char * const adsl_spi_cs_groups[] = { -+ "gpio19", -+}; -+ -+static const char * const ephy0_led_groups[] = { -+ "gpio20", -+}; -+ -+static const char * const ephy1_led_groups[] = { -+ "gpio21", -+}; -+ -+static const char * const ephy2_led_groups[] = { -+ "gpio22", -+}; -+ -+static const char * const ephy3_led_groups[] = { -+ "gpio23", -+}; -+ -+static const char * const ext_irq0_groups[] = { -+ "gpio24", -+}; -+ -+static const char * const ext_irq1_groups[] = { -+ "gpio25", -+}; -+ -+static const char * const ext_irq2_groups[] = { -+ "gpio26", -+}; -+ -+static const char * const ext_irq3_groups[] = { -+ "gpio27", -+}; -+ -+static const char * const wifi_groups[] = { -+ "gpio32", -+ "gpio33", -+ "gpio34", -+ "gpio35", -+ "gpio36", -+ "gpio37", -+ "gpio38", -+ "gpio39", -+ "gpio40", -+ "gpio41", -+ "gpio42", -+ "gpio43", -+ "gpio44", -+ "gpio45", -+ "gpio46", -+ "gpio47", -+}; -+ -+static const char * const nand_groups[] = { -+ "nand_grp", -+}; -+ -+#define BCM6362_LED_FUN(n) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .reg = BCM6362_LEDCTRL, \ -+ } -+ -+#define BCM6362_MODE_FUN(n) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .reg = BCM6362_MODE, \ -+ } -+ -+#define BCM6362_CTRL_FUN(n) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .reg = BCM6362_CTRL, \ -+ } -+ -+#define BCM6362_BASEMODE_FUN(n, mask) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .reg = BCM6362_BASEMODE, \ -+ .basemode_mask = (mask), \ -+ } -+ -+static const struct bcm6362_function bcm6362_funcs[] = { -+ BCM6362_LED_FUN(led), -+ BCM6362_MODE_FUN(usb_device_led), -+ BCM6362_MODE_FUN(sys_irq), -+ BCM6362_MODE_FUN(serial_led_clk), -+ BCM6362_MODE_FUN(serial_led_data), -+ BCM6362_MODE_FUN(robosw_led_data), -+ BCM6362_MODE_FUN(robosw_led_clk), -+ BCM6362_MODE_FUN(robosw_led0), -+ BCM6362_MODE_FUN(robosw_led1), -+ BCM6362_MODE_FUN(inet_led), -+ BCM6362_MODE_FUN(spi_cs2), -+ BCM6362_MODE_FUN(spi_cs3), -+ BCM6362_MODE_FUN(ntr_pulse), -+ BCM6362_MODE_FUN(uart1_scts), -+ BCM6362_MODE_FUN(uart1_srts), -+ BCM6362_MODE_FUN(uart1_sdin), -+ BCM6362_MODE_FUN(uart1_sdout), -+ BCM6362_MODE_FUN(adsl_spi_miso), -+ BCM6362_MODE_FUN(adsl_spi_mosi), -+ BCM6362_MODE_FUN(adsl_spi_clk), -+ BCM6362_MODE_FUN(adsl_spi_cs), -+ BCM6362_MODE_FUN(ephy0_led), -+ BCM6362_MODE_FUN(ephy1_led), -+ BCM6362_MODE_FUN(ephy2_led), -+ BCM6362_MODE_FUN(ephy3_led), -+ BCM6362_MODE_FUN(ext_irq0), -+ BCM6362_MODE_FUN(ext_irq1), -+ BCM6362_MODE_FUN(ext_irq2), -+ BCM6362_MODE_FUN(ext_irq3), -+ BCM6362_CTRL_FUN(wifi), -+ BCM6362_BASEMODE_FUN(nand, BASEMODE_NAND), -+}; -+ -+static int bcm6362_pinctrl_get_group_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6362_groups); -+} -+ -+static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev, -+ unsigned group) -+{ -+ return bcm6362_groups[group].name; -+} -+ -+static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, -+ unsigned group, const unsigned **pins, -+ unsigned *num_pins) -+{ -+ *pins = bcm6362_groups[group].pins; -+ *num_pins = bcm6362_groups[group].num_pins; -+ -+ return 0; -+} -+ -+static int bcm6362_pinctrl_get_func_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6362_funcs); -+} -+ -+static const char *bcm6362_pinctrl_get_func_name(struct pinctrl_dev *pctldev, -+ unsigned selector) -+{ -+ return bcm6362_funcs[selector].name; -+} -+ -+static int bcm6362_pinctrl_get_groups(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ const char * const **groups, -+ unsigned * const num_groups) -+{ -+ *groups = bcm6362_funcs[selector].groups; -+ *num_groups = bcm6362_funcs[selector].num_groups; -+ -+ return 0; -+} -+ -+static void bcm6362_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin) -+{ -+ const struct pinctrl_pin_desc *desc = &bcm6362_pins[pin]; -+ unsigned int mask = bcm63xx_bank_pin(pin); -+ -+ if (desc->drv_data) -+ regmap_update_bits(pc->regs, BCM6362_BASEMODE_REG, -+ (uint32_t) desc->drv_data, 0); -+ -+ if (pin < BCM63XX_BANK_GPIOS) { -+ /* base mode 0 => gpio 1 => mux function */ -+ regmap_update_bits(pc->regs, BCM6362_MODE_REG, mask, 0); -+ -+ /* pins 0-23 might be muxed to led */ -+ if (pin < BCM6362_NUM_LEDS) -+ regmap_update_bits(pc->regs, BCM6362_LED_REG, mask, 0); -+ } else { -+ /* ctrl reg 0 => wifi function 1 => gpio */ -+ regmap_update_bits(pc->regs, BCM6362_CTRL_REG, mask, mask); -+ } -+} -+ -+static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev, -+ unsigned selector, unsigned group) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ const struct bcm6362_pingroup *pg = &bcm6362_groups[group]; -+ const struct bcm6362_function *f = &bcm6362_funcs[selector]; -+ unsigned i; -+ unsigned int reg; -+ unsigned int val, mask; -+ -+ for (i = 0; i < pg->num_pins; i++) -+ bcm6362_set_gpio(pc, pg->pins[i]); -+ -+ switch (f->reg) { -+ case BCM6362_LEDCTRL: -+ reg = BCM6362_LED_REG; -+ mask = BIT(pg->pins[0]); -+ val = BIT(pg->pins[0]); -+ break; -+ case BCM6362_MODE: -+ reg = BCM6362_MODE_REG; -+ mask = BIT(pg->pins[0]); -+ val = BIT(pg->pins[0]); -+ break; -+ case BCM6362_CTRL: -+ reg = BCM6362_CTRL_REG; -+ mask = BIT(pg->pins[0]); -+ val = 0; -+ break; -+ case BCM6362_BASEMODE: -+ reg = BCM6362_BASEMODE_REG; -+ mask = f->basemode_mask; -+ val = f->basemode_mask; -+ break; -+ default: -+ WARN_ON(1); -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(pc->regs, reg, mask, val); -+ -+ return 0; -+} -+ -+static int bcm6362_gpio_request_enable(struct pinctrl_dev *pctldev, -+ struct pinctrl_gpio_range *range, -+ unsigned offset) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ -+ /* disable all functions using this pin */ -+ bcm6362_set_gpio(pc, offset); -+ -+ return 0; -+} -+ -+static struct pinctrl_ops bcm6362_pctl_ops = { -+ .dt_free_map = pinctrl_utils_free_map, -+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, -+ .get_group_name = bcm6362_pinctrl_get_group_name, -+ .get_group_pins = bcm6362_pinctrl_get_group_pins, -+ .get_groups_count = bcm6362_pinctrl_get_group_count, -+}; -+ -+static struct pinmux_ops bcm6362_pmx_ops = { -+ .get_function_groups = bcm6362_pinctrl_get_groups, -+ .get_function_name = bcm6362_pinctrl_get_func_name, -+ .get_functions_count = bcm6362_pinctrl_get_func_count, -+ .gpio_request_enable = bcm6362_gpio_request_enable, -+ .set_mux = bcm6362_pinctrl_set_mux, -+ .strict = true, -+}; -+ -+static const struct bcm63xx_pinctrl_soc bcm6362_soc = { -+ .ngpios = BCM6362_NUM_GPIOS, -+ .npins = ARRAY_SIZE(bcm6362_pins), -+ .pctl_ops = &bcm6362_pctl_ops, -+ .pins = bcm6362_pins, -+ .pmx_ops = &bcm6362_pmx_ops, -+}; -+ -+static int bcm6362_pinctrl_probe(struct platform_device *pdev) -+{ -+ return bcm63xx_pinctrl_probe(pdev, &bcm6362_soc, NULL); -+} -+ -+static const struct of_device_id bcm6362_pinctrl_match[] = { -+ { .compatible = "brcm,bcm6362-pinctrl", }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver bcm6362_pinctrl_driver = { -+ .probe = bcm6362_pinctrl_probe, -+ .driver = { -+ .name = "bcm6362-pinctrl", -+ .of_match_table = bcm6362_pinctrl_match, -+ }, -+}; -+ -+builtin_platform_driver(bcm6362_pinctrl_driver); diff --git a/target/linux/bmips/patches-5.10/065-v5.13-dt-bindings-add-BCM6368-pincontroller-binding-docume.patch b/target/linux/bmips/patches-5.10/065-v5.13-dt-bindings-add-BCM6368-pincontroller-binding-docume.patch deleted file mode 100644 index e4e91e597f..0000000000 --- a/target/linux/bmips/patches-5.10/065-v5.13-dt-bindings-add-BCM6368-pincontroller-binding-docume.patch +++ /dev/null @@ -1,242 +0,0 @@ -From 9fbf8303796c89ecab026eb3dbadae7f98c49922 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:15 +0100 -Subject: [PATCH 14/22] dt-bindings: add BCM6368 pincontroller binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the pincontrol core found in BCM6368 SoCs. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-15-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../pinctrl/brcm,bcm6368-pinctrl.yaml | 217 ++++++++++++++++++ - 1 file changed, 217 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml -@@ -0,0 +1,217 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6368-pinctrl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6368 pin controller -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Bindings for Broadcom's BCM6368 memory-mapped pin controller. -+ -+properties: -+ compatible: -+ const: brcm,bcm6368-pinctrl -+ -+ reg: -+ maxItems: 2 -+ -+patternProperties: -+ '-pins$': -+ type: object -+ $ref: pinmux-node.yaml# -+ -+ properties: -+ function: -+ enum: [ analog_afe_0, analog_afe_1, sys_irq, serial_led_data, -+ serial_led_clk, inet_led, ephy0_led, ephy1_led, ephy2_led, -+ ephy3_led, robosw_led_data, robosw_led_clk, robosw_led0, -+ robosw_led1, usb_device_led, pci_req1, pci_gnt1, pci_intb, -+ pci_req0, pci_gnt0, pcmcia_cd1, pcmcia_cd2, pcmcia_vs1, -+ pcmcia_vs2, ebi_cs2, ebi_cs3, spi_cs2, spi_cs3, spi_cs4, -+ spi_cs5, uart1 ] -+ -+ pins: -+ enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, -+ gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, -+ gpio16, gpio17, gpio18, gpio19, gpio20, gpio22, gpio23, -+ gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, -+ gpio31, uart1_grp ] -+ -+required: -+ - compatible -+ - reg -+ -+additionalProperties: false -+ -+examples: -+ - | -+ pinctrl@18 { -+ compatible = "brcm,bcm6368-pinctrl"; -+ reg = <0x18 0x4>, <0x38 0x4>; -+ -+ pinctrl_analog_afe_0: analog_afe_0-pins { -+ function = "analog_afe_0"; -+ pins = "gpio0"; -+ }; -+ -+ pinctrl_analog_afe_1: analog_afe_1-pins { -+ function = "analog_afe_1"; -+ pins = "gpio1"; -+ }; -+ -+ pinctrl_sys_irq: sys_irq-pins { -+ function = "sys_irq"; -+ pins = "gpio2"; -+ }; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio3"; -+ }; -+ -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio4"; -+ }; -+ }; -+ -+ pinctrl_inet_led: inet_led-pins { -+ function = "inet_led"; -+ pins = "gpio5"; -+ }; -+ -+ pinctrl_ephy0_led: ephy0_led-pins { -+ function = "ephy0_led"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_ephy1_led: ephy1_led-pins { -+ function = "ephy1_led"; -+ pins = "gpio7"; -+ }; -+ -+ pinctrl_ephy2_led: ephy2_led-pins { -+ function = "ephy2_led"; -+ pins = "gpio8"; -+ }; -+ -+ pinctrl_ephy3_led: ephy3_led-pins { -+ function = "ephy3_led"; -+ pins = "gpio9"; -+ }; -+ -+ pinctrl_robosw_led_data: robosw_led_data-pins { -+ function = "robosw_led_data"; -+ pins = "gpio10"; -+ }; -+ -+ pinctrl_robosw_led_clk: robosw_led_clk-pins { -+ function = "robosw_led_clk"; -+ pins = "gpio11"; -+ }; -+ -+ pinctrl_robosw_led0: robosw_led0-pins { -+ function = "robosw_led0"; -+ pins = "gpio12"; -+ }; -+ -+ pinctrl_robosw_led1: robosw_led1-pins { -+ function = "robosw_led1"; -+ pins = "gpio13"; -+ }; -+ -+ pinctrl_usb_device_led: usb_device_led-pins { -+ function = "usb_device_led"; -+ pins = "gpio14"; -+ }; -+ -+ pinctrl_pci: pci-pins { -+ pinctrl_pci_req1: pci_req1-pins { -+ function = "pci_req1"; -+ pins = "gpio16"; -+ }; -+ -+ pinctrl_pci_gnt1: pci_gnt1-pins { -+ function = "pci_gnt1"; -+ pins = "gpio17"; -+ }; -+ -+ pinctrl_pci_intb: pci_intb-pins { -+ function = "pci_intb"; -+ pins = "gpio18"; -+ }; -+ -+ pinctrl_pci_req0: pci_req0-pins { -+ function = "pci_req0"; -+ pins = "gpio19"; -+ }; -+ -+ pinctrl_pci_gnt0: pci_gnt0-pins { -+ function = "pci_gnt0"; -+ pins = "gpio20"; -+ }; -+ }; -+ -+ pinctrl_pcmcia: pcmcia-pins { -+ pinctrl_pcmcia_cd1: pcmcia_cd1-pins { -+ function = "pcmcia_cd1"; -+ pins = "gpio22"; -+ }; -+ -+ pinctrl_pcmcia_cd2: pcmcia_cd2-pins { -+ function = "pcmcia_cd2"; -+ pins = "gpio23"; -+ }; -+ -+ pinctrl_pcmcia_vs1: pcmcia_vs1-pins { -+ function = "pcmcia_vs1"; -+ pins = "gpio24"; -+ }; -+ -+ pinctrl_pcmcia_vs2: pcmcia_vs2-pins { -+ function = "pcmcia_vs2"; -+ pins = "gpio25"; -+ }; -+ }; -+ -+ pinctrl_ebi_cs2: ebi_cs2-pins { -+ function = "ebi_cs2"; -+ pins = "gpio26"; -+ }; -+ -+ pinctrl_ebi_cs3: ebi_cs3-pins { -+ function = "ebi_cs3"; -+ pins = "gpio27"; -+ }; -+ -+ pinctrl_spi_cs2: spi_cs2-pins { -+ function = "spi_cs2"; -+ pins = "gpio28"; -+ }; -+ -+ pinctrl_spi_cs3: spi_cs3-pins { -+ function = "spi_cs3"; -+ pins = "gpio29"; -+ }; -+ -+ pinctrl_spi_cs4: spi_cs4-pins { -+ function = "spi_cs4"; -+ pins = "gpio30"; -+ }; -+ -+ pinctrl_spi_cs5: spi_cs5-pins { -+ function = "spi_cs5"; -+ pins = "gpio31"; -+ }; -+ -+ pinctrl_uart1: uart1-pins { -+ function = "uart1"; -+ group = "uart1_grp"; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/066-v5.13-dt-bindings-add-BCM6368-GPIO-sysctl-binding-document.patch b/target/linux/bmips/patches-5.10/066-v5.13-dt-bindings-add-BCM6368-GPIO-sysctl-binding-document.patch deleted file mode 100644 index d36cff6564..0000000000 --- a/target/linux/bmips/patches-5.10/066-v5.13-dt-bindings-add-BCM6368-GPIO-sysctl-binding-document.patch +++ /dev/null @@ -1,269 +0,0 @@ -From fd22635f222f44dcb4dd6382d97de13144edad2b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:16 +0100 -Subject: [PATCH 15/22] dt-bindings: add BCM6368 GPIO sysctl binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the GPIO sysctl found in BCM6368 SoCs. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-16-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../mfd/brcm,bcm6368-gpio-sysctl.yaml | 246 ++++++++++++++++++ - 1 file changed, 246 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml -@@ -0,0 +1,246 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6368 GPIO System Controller Device Tree Bindings -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Broadcom BCM6368 SoC GPIO system controller which provides a register map -+ for controlling the GPIO and pins of the SoC. -+ -+properties: -+ "#address-cells": true -+ -+ "#size-cells": true -+ -+ compatible: -+ items: -+ - const: brcm,bcm6368-gpio-sysctl -+ - const: syscon -+ - const: simple-mfd -+ -+ ranges: -+ maxItems: 1 -+ -+ reg: -+ maxItems: 1 -+ -+patternProperties: -+ "^gpio@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../gpio/brcm,bcm6345-gpio.yaml" -+ description: -+ GPIO controller for the SoC GPIOs. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. -+ -+ "^pinctrl@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../pinctrl/brcm,bcm6368-pinctrl.yaml" -+ description: -+ Pin controller for the SoC pins. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml. -+ -+required: -+ - "#address-cells" -+ - compatible -+ - ranges -+ - reg -+ - "#size-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ syscon@10000080 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "brcm,bcm6368-gpio-sysctl", "syscon", "simple-mfd"; -+ reg = <0x10000080 0x80>; -+ ranges = <0 0x10000080 0x80>; -+ -+ gpio@0 { -+ compatible = "brcm,bcm6368-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0x0 0x8>, <0x8 0x8>; -+ -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 0 38>; -+ #gpio-cells = <2>; -+ }; -+ -+ pinctrl: pinctrl@18 { -+ compatible = "brcm,bcm6368-pinctrl"; -+ reg = <0x18 0x4>, <0x38 0x4>; -+ -+ pinctrl_analog_afe_0: analog_afe_0-pins { -+ function = "analog_afe_0"; -+ pins = "gpio0"; -+ }; -+ -+ pinctrl_analog_afe_1: analog_afe_1-pins { -+ function = "analog_afe_1"; -+ pins = "gpio1"; -+ }; -+ -+ pinctrl_sys_irq: sys_irq-pins { -+ function = "sys_irq"; -+ pins = "gpio2"; -+ }; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio3"; -+ }; -+ -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio4"; -+ }; -+ }; -+ -+ pinctrl_inet_led: inet_led-pins { -+ function = "inet_led"; -+ pins = "gpio5"; -+ }; -+ -+ pinctrl_ephy0_led: ephy0_led-pins { -+ function = "ephy0_led"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_ephy1_led: ephy1_led-pins { -+ function = "ephy1_led"; -+ pins = "gpio7"; -+ }; -+ -+ pinctrl_ephy2_led: ephy2_led-pins { -+ function = "ephy2_led"; -+ pins = "gpio8"; -+ }; -+ -+ pinctrl_ephy3_led: ephy3_led-pins { -+ function = "ephy3_led"; -+ pins = "gpio9"; -+ }; -+ -+ pinctrl_robosw_led_data: robosw_led_data-pins { -+ function = "robosw_led_data"; -+ pins = "gpio10"; -+ }; -+ -+ pinctrl_robosw_led_clk: robosw_led_clk-pins { -+ function = "robosw_led_clk"; -+ pins = "gpio11"; -+ }; -+ -+ pinctrl_robosw_led0: robosw_led0-pins { -+ function = "robosw_led0"; -+ pins = "gpio12"; -+ }; -+ -+ pinctrl_robosw_led1: robosw_led1-pins { -+ function = "robosw_led1"; -+ pins = "gpio13"; -+ }; -+ -+ pinctrl_usb_device_led: usb_device_led-pins { -+ function = "usb_device_led"; -+ pins = "gpio14"; -+ }; -+ -+ pinctrl_pci: pci-pins { -+ pinctrl_pci_req1: pci_req1-pins { -+ function = "pci_req1"; -+ pins = "gpio16"; -+ }; -+ -+ pinctrl_pci_gnt1: pci_gnt1-pins { -+ function = "pci_gnt1"; -+ pins = "gpio17"; -+ }; -+ -+ pinctrl_pci_intb: pci_intb-pins { -+ function = "pci_intb"; -+ pins = "gpio18"; -+ }; -+ -+ pinctrl_pci_req0: pci_req0-pins { -+ function = "pci_req0"; -+ pins = "gpio19"; -+ }; -+ -+ pinctrl_pci_gnt0: pci_gnt0-pins { -+ function = "pci_gnt0"; -+ pins = "gpio20"; -+ }; -+ }; -+ -+ pinctrl_pcmcia: pcmcia-pins { -+ pinctrl_pcmcia_cd1: pcmcia_cd1-pins { -+ function = "pcmcia_cd1"; -+ pins = "gpio22"; -+ }; -+ -+ pinctrl_pcmcia_cd2: pcmcia_cd2-pins { -+ function = "pcmcia_cd2"; -+ pins = "gpio23"; -+ }; -+ -+ pinctrl_pcmcia_vs1: pcmcia_vs1-pins { -+ function = "pcmcia_vs1"; -+ pins = "gpio24"; -+ }; -+ -+ pinctrl_pcmcia_vs2: pcmcia_vs2-pins { -+ function = "pcmcia_vs2"; -+ pins = "gpio25"; -+ }; -+ }; -+ -+ pinctrl_ebi_cs2: ebi_cs2-pins { -+ function = "ebi_cs2"; -+ pins = "gpio26"; -+ }; -+ -+ pinctrl_ebi_cs3: ebi_cs3-pins { -+ function = "ebi_cs3"; -+ pins = "gpio27"; -+ }; -+ -+ pinctrl_spi_cs2: spi_cs2-pins { -+ function = "spi_cs2"; -+ pins = "gpio28"; -+ }; -+ -+ pinctrl_spi_cs3: spi_cs3-pins { -+ function = "spi_cs3"; -+ pins = "gpio29"; -+ }; -+ -+ pinctrl_spi_cs4: spi_cs4-pins { -+ function = "spi_cs4"; -+ pins = "gpio30"; -+ }; -+ -+ pinctrl_spi_cs5: spi_cs5-pins { -+ function = "spi_cs5"; -+ pins = "gpio31"; -+ }; -+ -+ pinctrl_uart1: uart1-pins { -+ function = "uart1"; -+ group = "uart1_grp"; -+ }; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/067-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6368.patch b/target/linux/bmips/patches-5.10/067-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6368.patch deleted file mode 100644 index 3965762407..0000000000 --- a/target/linux/bmips/patches-5.10/067-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6368.patch +++ /dev/null @@ -1,576 +0,0 @@ -From 50554accf7a79980cd04481e8903073bdb706daf Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:17 +0100 -Subject: [PATCH 16/22] pinctrl: add a pincontrol driver for BCM6368 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32 -GPIOs onto alternative functions. Not all are documented. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210324081923.20379-17-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/bcm/Kconfig | 8 + - drivers/pinctrl/bcm/Makefile | 1 + - drivers/pinctrl/bcm/pinctrl-bcm6368.c | 523 ++++++++++++++++++++++++++ - 3 files changed, 532 insertions(+) - create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6368.c - ---- a/drivers/pinctrl/bcm/Kconfig -+++ b/drivers/pinctrl/bcm/Kconfig -@@ -60,6 +60,14 @@ config PINCTRL_BCM6362 - help - Say Y here to enable the Broadcom BCM6362 GPIO driver. - -+config PINCTRL_BCM6368 -+ bool "Broadcom BCM6368 GPIO driver" -+ depends on (BMIPS_GENERIC || COMPILE_TEST) -+ select PINCTRL_BCM63XX -+ default BMIPS_GENERIC -+ help -+ Say Y here to enable the Broadcom BCM6368 GPIO driver. -+ - config PINCTRL_IPROC_GPIO - bool "Broadcom iProc GPIO (with PINCONF) driver" - depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) ---- a/drivers/pinctrl/bcm/Makefile -+++ b/drivers/pinctrl/bcm/Makefile -@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_BCM63XX) += pinctr - obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o - obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o - obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o -+obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o - obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o - obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o - obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o ---- /dev/null -+++ b/drivers/pinctrl/bcm/pinctrl-bcm6368.c -@@ -0,0 +1,523 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Driver for BCM6368 GPIO unit (pinctrl + GPIO) -+ * -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> -+ */ -+ -+#include <linux/bits.h> -+#include <linux/gpio/driver.h> -+#include <linux/kernel.h> -+#include <linux/of.h> -+#include <linux/pinctrl/pinmux.h> -+#include <linux/platform_device.h> -+#include <linux/regmap.h> -+ -+#include "../pinctrl-utils.h" -+ -+#include "pinctrl-bcm63xx.h" -+ -+#define BCM6368_NUM_GPIOS 38 -+ -+#define BCM6368_MODE_REG 0x18 -+#define BCM6368_BASEMODE_REG 0x38 -+#define BCM6368_BASEMODE_MASK 0x7 -+#define BCM6368_BASEMODE_GPIO 0x0 -+#define BCM6368_BASEMODE_UART1 0x1 -+ -+struct bcm6368_pingroup { -+ const char *name; -+ const unsigned * const pins; -+ const unsigned num_pins; -+}; -+ -+struct bcm6368_function { -+ const char *name; -+ const char * const *groups; -+ const unsigned num_groups; -+ -+ unsigned dir_out:16; -+ unsigned basemode:3; -+}; -+ -+struct bcm6368_priv { -+ struct regmap_field *overlays; -+}; -+ -+#define BCM6368_BASEMODE_PIN(a, b) \ -+ { \ -+ .number = a, \ -+ .name = b, \ -+ .drv_data = (void *)true \ -+ } -+ -+static const struct pinctrl_pin_desc bcm6368_pins[] = { -+ PINCTRL_PIN(0, "gpio0"), -+ PINCTRL_PIN(1, "gpio1"), -+ PINCTRL_PIN(2, "gpio2"), -+ PINCTRL_PIN(3, "gpio3"), -+ PINCTRL_PIN(4, "gpio4"), -+ PINCTRL_PIN(5, "gpio5"), -+ PINCTRL_PIN(6, "gpio6"), -+ PINCTRL_PIN(7, "gpio7"), -+ PINCTRL_PIN(8, "gpio8"), -+ PINCTRL_PIN(9, "gpio9"), -+ PINCTRL_PIN(10, "gpio10"), -+ PINCTRL_PIN(11, "gpio11"), -+ PINCTRL_PIN(12, "gpio12"), -+ PINCTRL_PIN(13, "gpio13"), -+ PINCTRL_PIN(14, "gpio14"), -+ PINCTRL_PIN(15, "gpio15"), -+ PINCTRL_PIN(16, "gpio16"), -+ PINCTRL_PIN(17, "gpio17"), -+ PINCTRL_PIN(18, "gpio18"), -+ PINCTRL_PIN(19, "gpio19"), -+ PINCTRL_PIN(20, "gpio20"), -+ PINCTRL_PIN(21, "gpio21"), -+ PINCTRL_PIN(22, "gpio22"), -+ PINCTRL_PIN(23, "gpio23"), -+ PINCTRL_PIN(24, "gpio24"), -+ PINCTRL_PIN(25, "gpio25"), -+ PINCTRL_PIN(26, "gpio26"), -+ PINCTRL_PIN(27, "gpio27"), -+ PINCTRL_PIN(28, "gpio28"), -+ PINCTRL_PIN(29, "gpio29"), -+ BCM6368_BASEMODE_PIN(30, "gpio30"), -+ BCM6368_BASEMODE_PIN(31, "gpio31"), -+ BCM6368_BASEMODE_PIN(32, "gpio32"), -+ BCM6368_BASEMODE_PIN(33, "gpio33"), -+ PINCTRL_PIN(34, "gpio34"), -+ PINCTRL_PIN(35, "gpio35"), -+ PINCTRL_PIN(36, "gpio36"), -+ PINCTRL_PIN(37, "gpio37"), -+}; -+ -+static unsigned gpio0_pins[] = { 0 }; -+static unsigned gpio1_pins[] = { 1 }; -+static unsigned gpio2_pins[] = { 2 }; -+static unsigned gpio3_pins[] = { 3 }; -+static unsigned gpio4_pins[] = { 4 }; -+static unsigned gpio5_pins[] = { 5 }; -+static unsigned gpio6_pins[] = { 6 }; -+static unsigned gpio7_pins[] = { 7 }; -+static unsigned gpio8_pins[] = { 8 }; -+static unsigned gpio9_pins[] = { 9 }; -+static unsigned gpio10_pins[] = { 10 }; -+static unsigned gpio11_pins[] = { 11 }; -+static unsigned gpio12_pins[] = { 12 }; -+static unsigned gpio13_pins[] = { 13 }; -+static unsigned gpio14_pins[] = { 14 }; -+static unsigned gpio15_pins[] = { 15 }; -+static unsigned gpio16_pins[] = { 16 }; -+static unsigned gpio17_pins[] = { 17 }; -+static unsigned gpio18_pins[] = { 18 }; -+static unsigned gpio19_pins[] = { 19 }; -+static unsigned gpio20_pins[] = { 20 }; -+static unsigned gpio21_pins[] = { 21 }; -+static unsigned gpio22_pins[] = { 22 }; -+static unsigned gpio23_pins[] = { 23 }; -+static unsigned gpio24_pins[] = { 24 }; -+static unsigned gpio25_pins[] = { 25 }; -+static unsigned gpio26_pins[] = { 26 }; -+static unsigned gpio27_pins[] = { 27 }; -+static unsigned gpio28_pins[] = { 28 }; -+static unsigned gpio29_pins[] = { 29 }; -+static unsigned gpio30_pins[] = { 30 }; -+static unsigned gpio31_pins[] = { 31 }; -+static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 }; -+ -+#define BCM6368_GROUP(n) \ -+ { \ -+ .name = #n, \ -+ .pins = n##_pins, \ -+ .num_pins = ARRAY_SIZE(n##_pins), \ -+ } -+ -+static struct bcm6368_pingroup bcm6368_groups[] = { -+ BCM6368_GROUP(gpio0), -+ BCM6368_GROUP(gpio1), -+ BCM6368_GROUP(gpio2), -+ BCM6368_GROUP(gpio3), -+ BCM6368_GROUP(gpio4), -+ BCM6368_GROUP(gpio5), -+ BCM6368_GROUP(gpio6), -+ BCM6368_GROUP(gpio7), -+ BCM6368_GROUP(gpio8), -+ BCM6368_GROUP(gpio9), -+ BCM6368_GROUP(gpio10), -+ BCM6368_GROUP(gpio11), -+ BCM6368_GROUP(gpio12), -+ BCM6368_GROUP(gpio13), -+ BCM6368_GROUP(gpio14), -+ BCM6368_GROUP(gpio15), -+ BCM6368_GROUP(gpio16), -+ BCM6368_GROUP(gpio17), -+ BCM6368_GROUP(gpio18), -+ BCM6368_GROUP(gpio19), -+ BCM6368_GROUP(gpio20), -+ BCM6368_GROUP(gpio21), -+ BCM6368_GROUP(gpio22), -+ BCM6368_GROUP(gpio23), -+ BCM6368_GROUP(gpio24), -+ BCM6368_GROUP(gpio25), -+ BCM6368_GROUP(gpio26), -+ BCM6368_GROUP(gpio27), -+ BCM6368_GROUP(gpio28), -+ BCM6368_GROUP(gpio29), -+ BCM6368_GROUP(gpio30), -+ BCM6368_GROUP(gpio31), -+ BCM6368_GROUP(uart1_grp), -+}; -+ -+static const char * const analog_afe_0_groups[] = { -+ "gpio0", -+}; -+ -+static const char * const analog_afe_1_groups[] = { -+ "gpio1", -+}; -+ -+static const char * const sys_irq_groups[] = { -+ "gpio2", -+}; -+ -+static const char * const serial_led_data_groups[] = { -+ "gpio3", -+}; -+ -+static const char * const serial_led_clk_groups[] = { -+ "gpio4", -+}; -+ -+static const char * const inet_led_groups[] = { -+ "gpio5", -+}; -+ -+static const char * const ephy0_led_groups[] = { -+ "gpio6", -+}; -+ -+static const char * const ephy1_led_groups[] = { -+ "gpio7", -+}; -+ -+static const char * const ephy2_led_groups[] = { -+ "gpio8", -+}; -+ -+static const char * const ephy3_led_groups[] = { -+ "gpio9", -+}; -+ -+static const char * const robosw_led_data_groups[] = { -+ "gpio10", -+}; -+ -+static const char * const robosw_led_clk_groups[] = { -+ "gpio11", -+}; -+ -+static const char * const robosw_led0_groups[] = { -+ "gpio12", -+}; -+ -+static const char * const robosw_led1_groups[] = { -+ "gpio13", -+}; -+ -+static const char * const usb_device_led_groups[] = { -+ "gpio14", -+}; -+ -+static const char * const pci_req1_groups[] = { -+ "gpio16", -+}; -+ -+static const char * const pci_gnt1_groups[] = { -+ "gpio17", -+}; -+ -+static const char * const pci_intb_groups[] = { -+ "gpio18", -+}; -+ -+static const char * const pci_req0_groups[] = { -+ "gpio19", -+}; -+ -+static const char * const pci_gnt0_groups[] = { -+ "gpio20", -+}; -+ -+static const char * const pcmcia_cd1_groups[] = { -+ "gpio22", -+}; -+ -+static const char * const pcmcia_cd2_groups[] = { -+ "gpio23", -+}; -+ -+static const char * const pcmcia_vs1_groups[] = { -+ "gpio24", -+}; -+ -+static const char * const pcmcia_vs2_groups[] = { -+ "gpio25", -+}; -+ -+static const char * const ebi_cs2_groups[] = { -+ "gpio26", -+}; -+ -+static const char * const ebi_cs3_groups[] = { -+ "gpio27", -+}; -+ -+static const char * const spi_cs2_groups[] = { -+ "gpio28", -+}; -+ -+static const char * const spi_cs3_groups[] = { -+ "gpio29", -+}; -+ -+static const char * const spi_cs4_groups[] = { -+ "gpio30", -+}; -+ -+static const char * const spi_cs5_groups[] = { -+ "gpio31", -+}; -+ -+static const char * const uart1_groups[] = { -+ "uart1_grp", -+}; -+ -+#define BCM6368_FUN(n, out) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .dir_out = out, \ -+ } -+ -+#define BCM6368_BASEMODE_FUN(n, val, out) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .basemode = BCM6368_BASEMODE_##val, \ -+ .dir_out = out, \ -+ } -+ -+static const struct bcm6368_function bcm6368_funcs[] = { -+ BCM6368_FUN(analog_afe_0, 1), -+ BCM6368_FUN(analog_afe_1, 1), -+ BCM6368_FUN(sys_irq, 1), -+ BCM6368_FUN(serial_led_data, 1), -+ BCM6368_FUN(serial_led_clk, 1), -+ BCM6368_FUN(inet_led, 1), -+ BCM6368_FUN(ephy0_led, 1), -+ BCM6368_FUN(ephy1_led, 1), -+ BCM6368_FUN(ephy2_led, 1), -+ BCM6368_FUN(ephy3_led, 1), -+ BCM6368_FUN(robosw_led_data, 1), -+ BCM6368_FUN(robosw_led_clk, 1), -+ BCM6368_FUN(robosw_led0, 1), -+ BCM6368_FUN(robosw_led1, 1), -+ BCM6368_FUN(usb_device_led, 1), -+ BCM6368_FUN(pci_req1, 0), -+ BCM6368_FUN(pci_gnt1, 0), -+ BCM6368_FUN(pci_intb, 0), -+ BCM6368_FUN(pci_req0, 0), -+ BCM6368_FUN(pci_gnt0, 0), -+ BCM6368_FUN(pcmcia_cd1, 0), -+ BCM6368_FUN(pcmcia_cd2, 0), -+ BCM6368_FUN(pcmcia_vs1, 0), -+ BCM6368_FUN(pcmcia_vs2, 0), -+ BCM6368_FUN(ebi_cs2, 1), -+ BCM6368_FUN(ebi_cs3, 1), -+ BCM6368_FUN(spi_cs2, 1), -+ BCM6368_FUN(spi_cs3, 1), -+ BCM6368_FUN(spi_cs4, 1), -+ BCM6368_FUN(spi_cs5, 1), -+ BCM6368_BASEMODE_FUN(uart1, UART1, 0x6), -+}; -+ -+static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6368_groups); -+} -+ -+static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev, -+ unsigned group) -+{ -+ return bcm6368_groups[group].name; -+} -+ -+static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, -+ unsigned group, const unsigned **pins, -+ unsigned *num_pins) -+{ -+ *pins = bcm6368_groups[group].pins; -+ *num_pins = bcm6368_groups[group].num_pins; -+ -+ return 0; -+} -+ -+static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6368_funcs); -+} -+ -+static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev, -+ unsigned selector) -+{ -+ return bcm6368_funcs[selector].name; -+} -+ -+static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ const char * const **groups, -+ unsigned * const num_groups) -+{ -+ *groups = bcm6368_funcs[selector].groups; -+ *num_groups = bcm6368_funcs[selector].num_groups; -+ -+ return 0; -+} -+ -+static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev, -+ unsigned selector, unsigned group) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ struct bcm6368_priv *priv = pc->driver_data; -+ const struct bcm6368_pingroup *pg = &bcm6368_groups[group]; -+ const struct bcm6368_function *fun = &bcm6368_funcs[selector]; -+ int i, pin; -+ -+ if (fun->basemode) { -+ unsigned int mask = 0; -+ -+ for (i = 0; i < pg->num_pins; i++) { -+ pin = pg->pins[i]; -+ if (pin < BCM63XX_BANK_GPIOS) -+ mask |= BIT(pin); -+ } -+ -+ regmap_update_bits(pc->regs, BCM6368_MODE_REG, mask, 0); -+ regmap_field_write(priv->overlays, fun->basemode); -+ } else { -+ pin = pg->pins[0]; -+ -+ if (bcm6368_pins[pin].drv_data) -+ regmap_field_write(priv->overlays, -+ BCM6368_BASEMODE_GPIO); -+ -+ regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(pin), -+ BIT(pin)); -+ } -+ -+ for (pin = 0; pin < pg->num_pins; pin++) { -+ struct pinctrl_gpio_range *range; -+ int hw_gpio = bcm6368_pins[pin].number; -+ -+ range = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio); -+ if (range) { -+ struct gpio_chip *gc = range->gc; -+ -+ if (fun->dir_out & BIT(pin)) -+ gc->direction_output(gc, hw_gpio, 0); -+ else -+ gc->direction_input(gc, hw_gpio); -+ } -+ } -+ -+ return 0; -+} -+ -+static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev, -+ struct pinctrl_gpio_range *range, -+ unsigned offset) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ struct bcm6368_priv *priv = pc->driver_data; -+ -+ if (offset >= BCM63XX_BANK_GPIOS && !bcm6368_pins[offset].drv_data) -+ return 0; -+ -+ /* disable all functions using this pin */ -+ if (offset < BCM63XX_BANK_GPIOS) -+ regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(offset), 0); -+ -+ if (bcm6368_pins[offset].drv_data) -+ regmap_field_write(priv->overlays, BCM6368_BASEMODE_GPIO); -+ -+ return 0; -+} -+ -+static struct pinctrl_ops bcm6368_pctl_ops = { -+ .dt_free_map = pinctrl_utils_free_map, -+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, -+ .get_group_name = bcm6368_pinctrl_get_group_name, -+ .get_group_pins = bcm6368_pinctrl_get_group_pins, -+ .get_groups_count = bcm6368_pinctrl_get_group_count, -+}; -+ -+static struct pinmux_ops bcm6368_pmx_ops = { -+ .get_function_groups = bcm6368_pinctrl_get_groups, -+ .get_function_name = bcm6368_pinctrl_get_func_name, -+ .get_functions_count = bcm6368_pinctrl_get_func_count, -+ .gpio_request_enable = bcm6368_gpio_request_enable, -+ .set_mux = bcm6368_pinctrl_set_mux, -+ .strict = true, -+}; -+ -+static const struct bcm63xx_pinctrl_soc bcm6368_soc = { -+ .ngpios = BCM6368_NUM_GPIOS, -+ .npins = ARRAY_SIZE(bcm6368_pins), -+ .pctl_ops = &bcm6368_pctl_ops, -+ .pins = bcm6368_pins, -+ .pmx_ops = &bcm6368_pmx_ops, -+}; -+ -+static int bcm6368_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct reg_field overlays = REG_FIELD(BCM6368_BASEMODE_REG, 0, 15); -+ struct device *dev = &pdev->dev; -+ struct bcm63xx_pinctrl *pc; -+ struct bcm6368_priv *priv; -+ int err; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ err = bcm63xx_pinctrl_probe(pdev, &bcm6368_soc, (void *) priv); -+ if (err) -+ return err; -+ -+ pc = platform_get_drvdata(pdev); -+ -+ priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays); -+ if (IS_ERR(priv->overlays)) -+ return PTR_ERR(priv->overlays); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm6368_pinctrl_match[] = { -+ { .compatible = "brcm,bcm6368-pinctrl", }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver bcm6368_pinctrl_driver = { -+ .probe = bcm6368_pinctrl_probe, -+ .driver = { -+ .name = "bcm6368-pinctrl", -+ .of_match_table = bcm6368_pinctrl_match, -+ }, -+}; -+ -+builtin_platform_driver(bcm6368_pinctrl_driver); diff --git a/target/linux/bmips/patches-5.10/068-v5.13-dt-bindings-add-BCM63268-pincontroller-binding-docum.patch b/target/linux/bmips/patches-5.10/068-v5.13-dt-bindings-add-BCM63268-pincontroller-binding-docum.patch deleted file mode 100644 index bffc1ab02f..0000000000 --- a/target/linux/bmips/patches-5.10/068-v5.13-dt-bindings-add-BCM63268-pincontroller-binding-docum.patch +++ /dev/null @@ -1,190 +0,0 @@ -From 9b3303413379af8bed307cd465fe7aa1bc3569ea Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:18 +0100 -Subject: [PATCH 17/22] dt-bindings: add BCM63268 pincontroller binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the pincontrol core found in the BCM63268 -family SoCs. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-18-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../pinctrl/brcm,bcm63268-pinctrl.yaml | 164 ++++++++++++++++++ - 1 file changed, 164 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml -@@ -0,0 +1,164 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM63268 pin controller -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Bindings for Broadcom's BCM63268 memory-mapped pin controller. -+ -+properties: -+ compatible: -+ const: brcm,bcm63268-pinctrl -+ -+ reg: -+ maxItems: 3 -+ -+patternProperties: -+ '-pins$': -+ type: object -+ $ref: pinmux-node.yaml# -+ -+ properties: -+ function: -+ enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5, -+ hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi, -+ vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data, -+ nand, gpio35_alt, dectpd, vdsl_phy_override_0, -+ vdsl_phy_override_1, vdsl_phy_override_2, -+ vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ] -+ -+ pins: -+ enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19, -+ gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35 -+ dectpd_grp, vdsl_phy_override_0_grp, -+ vdsl_phy_override_1_grp, vdsl_phy_override_2_grp, -+ vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ] -+ -+required: -+ - compatible -+ - reg -+ -+additionalProperties: false -+ -+examples: -+ - | -+ pinctrl@10 { -+ compatible = "brcm,bcm63268-pinctrl"; -+ reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio0"; -+ }; -+ -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio1"; -+ }; -+ }; -+ -+ pinctrl_hsspi_cs4: hsspi_cs4-pins { -+ function = "hsspi_cs4"; -+ pins = "gpio16"; -+ }; -+ -+ pinctrl_hsspi_cs5: hsspi_cs5-pins { -+ function = "hsspi_cs5"; -+ pins = "gpio17"; -+ }; -+ -+ pinctrl_hsspi_cs6: hsspi_cs6-pins { -+ function = "hsspi_cs6"; -+ pins = "gpio8"; -+ }; -+ -+ pinctrl_hsspi_cs7: hsspi_cs7-pins { -+ function = "hsspi_cs7"; -+ pins = "gpio9"; -+ }; -+ -+ pinctrl_adsl_spi: adsl_spi-pins { -+ pinctrl_adsl_spi_miso: adsl_spi_miso-pins { -+ function = "adsl_spi_miso"; -+ pins = "gpio18"; -+ }; -+ -+ pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins { -+ function = "adsl_spi_mosi"; -+ pins = "gpio19"; -+ }; -+ }; -+ -+ pinctrl_vreq_clk: vreq_clk-pins { -+ function = "vreq_clk"; -+ pins = "gpio22"; -+ }; -+ -+ pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins { -+ function = "pcie_clkreq_b"; -+ pins = "gpio23"; -+ }; -+ -+ pinctrl_robosw_led_clk: robosw_led_clk-pins { -+ function = "robosw_led_clk"; -+ pins = "gpio30"; -+ }; -+ -+ pinctrl_robosw_led_data: robosw_led_data-pins { -+ function = "robosw_led_data"; -+ pins = "gpio31"; -+ }; -+ -+ pinctrl_nand: nand-pins { -+ function = "nand"; -+ group = "nand_grp"; -+ }; -+ -+ pinctrl_gpio35_alt: gpio35_alt-pins { -+ function = "gpio35_alt"; -+ pin = "gpio35"; -+ }; -+ -+ pinctrl_dectpd: dectpd-pins { -+ function = "dectpd"; -+ group = "dectpd_grp"; -+ }; -+ -+ pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins { -+ function = "vdsl_phy_override_0"; -+ group = "vdsl_phy_override_0_grp"; -+ }; -+ -+ pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins { -+ function = "vdsl_phy_override_1"; -+ group = "vdsl_phy_override_1_grp"; -+ }; -+ -+ pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins { -+ function = "vdsl_phy_override_2"; -+ group = "vdsl_phy_override_2_grp"; -+ }; -+ -+ pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins { -+ function = "vdsl_phy_override_3"; -+ group = "vdsl_phy_override_3_grp"; -+ }; -+ -+ pinctrl_dsl_gpio8: dsl_gpio8-pins { -+ function = "dsl_gpio8"; -+ group = "dsl_gpio8"; -+ }; -+ -+ pinctrl_dsl_gpio9: dsl_gpio9-pins { -+ function = "dsl_gpio9"; -+ group = "dsl_gpio9"; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/069-v5.13-dt-bindings-add-BCM63268-GPIO-sysctl-binding-documen.patch b/target/linux/bmips/patches-5.10/069-v5.13-dt-bindings-add-BCM63268-GPIO-sysctl-binding-documen.patch deleted file mode 100644 index a130d60d42..0000000000 --- a/target/linux/bmips/patches-5.10/069-v5.13-dt-bindings-add-BCM63268-GPIO-sysctl-binding-documen.patch +++ /dev/null @@ -1,217 +0,0 @@ -From ff8324355d7ae2e4ebbd304de27bb5fa75e20c6a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:19 +0100 -Subject: [PATCH 18/22] dt-bindings: add BCM63268 GPIO sysctl binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the GPIO sysctl found in BCM63268 SoCs. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-19-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../mfd/brcm,bcm63268-gpio-sysctl.yaml | 194 ++++++++++++++++++ - 1 file changed, 194 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml -@@ -0,0 +1,194 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Broadcom BCM63268 SoC GPIO system controller which provides a register map -+ for controlling the GPIO and pins of the SoC. -+ -+properties: -+ "#address-cells": true -+ -+ "#size-cells": true -+ -+ compatible: -+ items: -+ - const: brcm,bcm63268-gpio-sysctl -+ - const: syscon -+ - const: simple-mfd -+ -+ ranges: -+ maxItems: 1 -+ -+ reg: -+ maxItems: 1 -+ -+patternProperties: -+ "^gpio@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../gpio/brcm,bcm6345-gpio.yaml" -+ description: -+ GPIO controller for the SoC GPIOs. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. -+ -+ "^pinctrl@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml" -+ description: -+ Pin controller for the SoC pins. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml. -+ -+required: -+ - "#address-cells" -+ - compatible -+ - ranges -+ - reg -+ - "#size-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ syscon@100000c0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd"; -+ reg = <0x100000c0 0x80>; -+ ranges = <0 0x100000c0 0x80>; -+ -+ gpio@0 { -+ compatible = "brcm,bcm63268-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0x0 0x8>, <0x8 0x8>; -+ -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 0 52>; -+ #gpio-cells = <2>; -+ }; -+ -+ pinctrl: pinctrl@10 { -+ compatible = "brcm,bcm63268-pinctrl"; -+ reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio0"; -+ }; -+ -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio1"; -+ }; -+ }; -+ -+ pinctrl_hsspi_cs4: hsspi_cs4-pins { -+ function = "hsspi_cs4"; -+ pins = "gpio16"; -+ }; -+ -+ pinctrl_hsspi_cs5: hsspi_cs5-pins { -+ function = "hsspi_cs5"; -+ pins = "gpio17"; -+ }; -+ -+ pinctrl_hsspi_cs6: hsspi_cs6-pins { -+ function = "hsspi_cs6"; -+ pins = "gpio8"; -+ }; -+ -+ pinctrl_hsspi_cs7: hsspi_cs7-pins { -+ function = "hsspi_cs7"; -+ pins = "gpio9"; -+ }; -+ -+ pinctrl_adsl_spi: adsl_spi-pins { -+ pinctrl_adsl_spi_miso: adsl_spi_miso-pins { -+ function = "adsl_spi_miso"; -+ pins = "gpio18"; -+ }; -+ -+ pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins { -+ function = "adsl_spi_mosi"; -+ pins = "gpio19"; -+ }; -+ }; -+ -+ pinctrl_vreq_clk: vreq_clk-pins { -+ function = "vreq_clk"; -+ pins = "gpio22"; -+ }; -+ -+ pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins { -+ function = "pcie_clkreq_b"; -+ pins = "gpio23"; -+ }; -+ -+ pinctrl_robosw_led_clk: robosw_led_clk-pins { -+ function = "robosw_led_clk"; -+ pins = "gpio30"; -+ }; -+ -+ pinctrl_robosw_led_data: robosw_led_data-pins { -+ function = "robosw_led_data"; -+ pins = "gpio31"; -+ }; -+ -+ pinctrl_nand: nand-pins { -+ function = "nand"; -+ group = "nand_grp"; -+ }; -+ -+ pinctrl_gpio35_alt: gpio35_alt-pins { -+ function = "gpio35_alt"; -+ pin = "gpio35"; -+ }; -+ -+ pinctrl_dectpd: dectpd-pins { -+ function = "dectpd"; -+ group = "dectpd_grp"; -+ }; -+ -+ pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins { -+ function = "vdsl_phy_override_0"; -+ group = "vdsl_phy_override_0_grp"; -+ }; -+ -+ pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins { -+ function = "vdsl_phy_override_1"; -+ group = "vdsl_phy_override_1_grp"; -+ }; -+ -+ pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins { -+ function = "vdsl_phy_override_2"; -+ group = "vdsl_phy_override_2_grp"; -+ }; -+ -+ pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins { -+ function = "vdsl_phy_override_3"; -+ group = "vdsl_phy_override_3_grp"; -+ }; -+ -+ pinctrl_dsl_gpio8: dsl_gpio8-pins { -+ function = "dsl_gpio8"; -+ group = "dsl_gpio8"; -+ }; -+ -+ pinctrl_dsl_gpio9: dsl_gpio9-pins { -+ function = "dsl_gpio9"; -+ group = "dsl_gpio9"; -+ }; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/070-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM63268.patch b/target/linux/bmips/patches-5.10/070-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM63268.patch deleted file mode 100644 index 933af5fb51..0000000000 --- a/target/linux/bmips/patches-5.10/070-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM63268.patch +++ /dev/null @@ -1,697 +0,0 @@ -From 155cca1b0794a8f541e7eaa45be70df0a49964f3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:20 +0100 -Subject: [PATCH 19/22] pinctrl: add a pincontrol driver for BCM63268 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs -to different functions. Depending on the mux, these are either single -pin configurations or whole pin groups. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210324081923.20379-20-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/bcm/Kconfig | 8 + - drivers/pinctrl/bcm/Makefile | 1 + - drivers/pinctrl/bcm/pinctrl-bcm63268.c | 643 +++++++++++++++++++++++++ - 3 files changed, 652 insertions(+) - create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63268.c - ---- a/drivers/pinctrl/bcm/Kconfig -+++ b/drivers/pinctrl/bcm/Kconfig -@@ -68,6 +68,14 @@ config PINCTRL_BCM6368 - help - Say Y here to enable the Broadcom BCM6368 GPIO driver. - -+config PINCTRL_BCM63268 -+ bool "Broadcom BCM63268 GPIO driver" -+ depends on (BMIPS_GENERIC || COMPILE_TEST) -+ select PINCTRL_BCM63XX -+ default BMIPS_GENERIC -+ help -+ Say Y here to enable the Broadcom BCM63268 GPIO driver. -+ - config PINCTRL_IPROC_GPIO - bool "Broadcom iProc GPIO (with PINCONF) driver" - depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) ---- a/drivers/pinctrl/bcm/Makefile -+++ b/drivers/pinctrl/bcm/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_BCM6328) += pinctr - obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o - obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o - obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o -+obj-$(CONFIG_PINCTRL_BCM63268) += pinctrl-bcm63268.o - obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o - obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o - obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o ---- /dev/null -+++ b/drivers/pinctrl/bcm/pinctrl-bcm63268.c -@@ -0,0 +1,643 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Driver for BCM63268 GPIO unit (pinctrl + GPIO) -+ * -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> -+ */ -+ -+#include <linux/bits.h> -+#include <linux/gpio/driver.h> -+#include <linux/kernel.h> -+#include <linux/of.h> -+#include <linux/pinctrl/pinmux.h> -+#include <linux/platform_device.h> -+#include <linux/regmap.h> -+ -+#include "../pinctrl-utils.h" -+ -+#include "pinctrl-bcm63xx.h" -+ -+#define BCM63268_NUM_GPIOS 52 -+#define BCM63268_NUM_LEDS 24 -+ -+#define BCM63268_LED_REG 0x10 -+#define BCM63268_MODE_REG 0x18 -+#define BCM63268_CTRL_REG 0x1c -+#define BCM63268_BASEMODE_REG 0x38 -+#define BCM63268_BASEMODE_NAND BIT(2) /* GPIOs 2-7, 24-31 */ -+#define BCM63268_BASEMODE_GPIO35 BIT(4) /* GPIO 35 */ -+#define BCM63268_BASEMODE_DECTPD BIT(5) /* GPIOs 8/9 */ -+#define BCM63268_BASEMODE_VDSL_PHY_0 BIT(6) /* GPIOs 10/11 */ -+#define BCM63268_BASEMODE_VDSL_PHY_1 BIT(7) /* GPIOs 12/13 */ -+#define BCM63268_BASEMODE_VDSL_PHY_2 BIT(8) /* GPIOs 24/25 */ -+#define BCM63268_BASEMODE_VDSL_PHY_3 BIT(9) /* GPIOs 26/27 */ -+ -+enum bcm63268_pinctrl_reg { -+ BCM63268_LEDCTRL, -+ BCM63268_MODE, -+ BCM63268_CTRL, -+ BCM63268_BASEMODE, -+}; -+ -+struct bcm63268_pingroup { -+ const char *name; -+ const unsigned * const pins; -+ const unsigned num_pins; -+}; -+ -+struct bcm63268_function { -+ const char *name; -+ const char * const *groups; -+ const unsigned num_groups; -+ -+ enum bcm63268_pinctrl_reg reg; -+ uint32_t mask; -+}; -+ -+#define BCM63268_PIN(a, b, basemode) \ -+ { \ -+ .number = a, \ -+ .name = b, \ -+ .drv_data = (void *)(basemode) \ -+ } -+ -+static const struct pinctrl_pin_desc bcm63268_pins[] = { -+ PINCTRL_PIN(0, "gpio0"), -+ PINCTRL_PIN(1, "gpio1"), -+ BCM63268_PIN(2, "gpio2", BCM63268_BASEMODE_NAND), -+ BCM63268_PIN(3, "gpio3", BCM63268_BASEMODE_NAND), -+ BCM63268_PIN(4, "gpio4", BCM63268_BASEMODE_NAND), -+ BCM63268_PIN(5, "gpio5", BCM63268_BASEMODE_NAND), -+ BCM63268_PIN(6, "gpio6", BCM63268_BASEMODE_NAND), -+ BCM63268_PIN(7, "gpio7", BCM63268_BASEMODE_NAND), -+ BCM63268_PIN(8, "gpio8", BCM63268_BASEMODE_DECTPD), -+ BCM63268_PIN(9, "gpio9", BCM63268_BASEMODE_DECTPD), -+ BCM63268_PIN(10, "gpio10", BCM63268_BASEMODE_VDSL_PHY_0), -+ BCM63268_PIN(11, "gpio11", BCM63268_BASEMODE_VDSL_PHY_0), -+ BCM63268_PIN(12, "gpio12", BCM63268_BASEMODE_VDSL_PHY_1), -+ BCM63268_PIN(13, "gpio13", BCM63268_BASEMODE_VDSL_PHY_1), -+ PINCTRL_PIN(14, "gpio14"), -+ PINCTRL_PIN(15, "gpio15"), -+ PINCTRL_PIN(16, "gpio16"), -+ PINCTRL_PIN(17, "gpio17"), -+ PINCTRL_PIN(18, "gpio18"), -+ PINCTRL_PIN(19, "gpio19"), -+ PINCTRL_PIN(20, "gpio20"), -+ PINCTRL_PIN(21, "gpio21"), -+ PINCTRL_PIN(22, "gpio22"), -+ PINCTRL_PIN(23, "gpio23"), -+ BCM63268_PIN(24, "gpio24", -+ BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2), -+ BCM63268_PIN(25, "gpio25", -+ BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2), -+ BCM63268_PIN(26, "gpio26", -+ BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3), -+ BCM63268_PIN(27, "gpio27", -+ BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3), -+ BCM63268_PIN(28, "gpio28", BCM63268_BASEMODE_NAND), -+ BCM63268_PIN(29, "gpio29", BCM63268_BASEMODE_NAND), -+ BCM63268_PIN(30, "gpio30", BCM63268_BASEMODE_NAND), -+ BCM63268_PIN(31, "gpio31", BCM63268_BASEMODE_NAND), -+ PINCTRL_PIN(32, "gpio32"), -+ PINCTRL_PIN(33, "gpio33"), -+ PINCTRL_PIN(34, "gpio34"), -+ PINCTRL_PIN(35, "gpio35"), -+ PINCTRL_PIN(36, "gpio36"), -+ PINCTRL_PIN(37, "gpio37"), -+ PINCTRL_PIN(38, "gpio38"), -+ PINCTRL_PIN(39, "gpio39"), -+ PINCTRL_PIN(40, "gpio40"), -+ PINCTRL_PIN(41, "gpio41"), -+ PINCTRL_PIN(42, "gpio42"), -+ PINCTRL_PIN(43, "gpio43"), -+ PINCTRL_PIN(44, "gpio44"), -+ PINCTRL_PIN(45, "gpio45"), -+ PINCTRL_PIN(46, "gpio46"), -+ PINCTRL_PIN(47, "gpio47"), -+ PINCTRL_PIN(48, "gpio48"), -+ PINCTRL_PIN(49, "gpio49"), -+ PINCTRL_PIN(50, "gpio50"), -+ PINCTRL_PIN(51, "gpio51"), -+}; -+ -+static unsigned gpio0_pins[] = { 0 }; -+static unsigned gpio1_pins[] = { 1 }; -+static unsigned gpio2_pins[] = { 2 }; -+static unsigned gpio3_pins[] = { 3 }; -+static unsigned gpio4_pins[] = { 4 }; -+static unsigned gpio5_pins[] = { 5 }; -+static unsigned gpio6_pins[] = { 6 }; -+static unsigned gpio7_pins[] = { 7 }; -+static unsigned gpio8_pins[] = { 8 }; -+static unsigned gpio9_pins[] = { 9 }; -+static unsigned gpio10_pins[] = { 10 }; -+static unsigned gpio11_pins[] = { 11 }; -+static unsigned gpio12_pins[] = { 12 }; -+static unsigned gpio13_pins[] = { 13 }; -+static unsigned gpio14_pins[] = { 14 }; -+static unsigned gpio15_pins[] = { 15 }; -+static unsigned gpio16_pins[] = { 16 }; -+static unsigned gpio17_pins[] = { 17 }; -+static unsigned gpio18_pins[] = { 18 }; -+static unsigned gpio19_pins[] = { 19 }; -+static unsigned gpio20_pins[] = { 20 }; -+static unsigned gpio21_pins[] = { 21 }; -+static unsigned gpio22_pins[] = { 22 }; -+static unsigned gpio23_pins[] = { 23 }; -+static unsigned gpio24_pins[] = { 24 }; -+static unsigned gpio25_pins[] = { 25 }; -+static unsigned gpio26_pins[] = { 26 }; -+static unsigned gpio27_pins[] = { 27 }; -+static unsigned gpio28_pins[] = { 28 }; -+static unsigned gpio29_pins[] = { 29 }; -+static unsigned gpio30_pins[] = { 30 }; -+static unsigned gpio31_pins[] = { 31 }; -+static unsigned gpio32_pins[] = { 32 }; -+static unsigned gpio33_pins[] = { 33 }; -+static unsigned gpio34_pins[] = { 34 }; -+static unsigned gpio35_pins[] = { 35 }; -+static unsigned gpio36_pins[] = { 36 }; -+static unsigned gpio37_pins[] = { 37 }; -+static unsigned gpio38_pins[] = { 38 }; -+static unsigned gpio39_pins[] = { 39 }; -+static unsigned gpio40_pins[] = { 40 }; -+static unsigned gpio41_pins[] = { 41 }; -+static unsigned gpio42_pins[] = { 42 }; -+static unsigned gpio43_pins[] = { 43 }; -+static unsigned gpio44_pins[] = { 44 }; -+static unsigned gpio45_pins[] = { 45 }; -+static unsigned gpio46_pins[] = { 46 }; -+static unsigned gpio47_pins[] = { 47 }; -+static unsigned gpio48_pins[] = { 48 }; -+static unsigned gpio49_pins[] = { 49 }; -+static unsigned gpio50_pins[] = { 50 }; -+static unsigned gpio51_pins[] = { 51 }; -+ -+static unsigned nand_grp_pins[] = { -+ 2, 3, 4, 5, 6, 7, 24, -+ 25, 26, 27, 28, 29, 30, 31, -+}; -+ -+static unsigned dectpd_grp_pins[] = { 8, 9 }; -+static unsigned vdsl_phy0_grp_pins[] = { 10, 11 }; -+static unsigned vdsl_phy1_grp_pins[] = { 12, 13 }; -+static unsigned vdsl_phy2_grp_pins[] = { 24, 25 }; -+static unsigned vdsl_phy3_grp_pins[] = { 26, 27 }; -+ -+#define BCM63268_GROUP(n) \ -+ { \ -+ .name = #n, \ -+ .pins = n##_pins, \ -+ .num_pins = ARRAY_SIZE(n##_pins), \ -+ } -+ -+static struct bcm63268_pingroup bcm63268_groups[] = { -+ BCM63268_GROUP(gpio0), -+ BCM63268_GROUP(gpio1), -+ BCM63268_GROUP(gpio2), -+ BCM63268_GROUP(gpio3), -+ BCM63268_GROUP(gpio4), -+ BCM63268_GROUP(gpio5), -+ BCM63268_GROUP(gpio6), -+ BCM63268_GROUP(gpio7), -+ BCM63268_GROUP(gpio8), -+ BCM63268_GROUP(gpio9), -+ BCM63268_GROUP(gpio10), -+ BCM63268_GROUP(gpio11), -+ BCM63268_GROUP(gpio12), -+ BCM63268_GROUP(gpio13), -+ BCM63268_GROUP(gpio14), -+ BCM63268_GROUP(gpio15), -+ BCM63268_GROUP(gpio16), -+ BCM63268_GROUP(gpio17), -+ BCM63268_GROUP(gpio18), -+ BCM63268_GROUP(gpio19), -+ BCM63268_GROUP(gpio20), -+ BCM63268_GROUP(gpio21), -+ BCM63268_GROUP(gpio22), -+ BCM63268_GROUP(gpio23), -+ BCM63268_GROUP(gpio24), -+ BCM63268_GROUP(gpio25), -+ BCM63268_GROUP(gpio26), -+ BCM63268_GROUP(gpio27), -+ BCM63268_GROUP(gpio28), -+ BCM63268_GROUP(gpio29), -+ BCM63268_GROUP(gpio30), -+ BCM63268_GROUP(gpio31), -+ BCM63268_GROUP(gpio32), -+ BCM63268_GROUP(gpio33), -+ BCM63268_GROUP(gpio34), -+ BCM63268_GROUP(gpio35), -+ BCM63268_GROUP(gpio36), -+ BCM63268_GROUP(gpio37), -+ BCM63268_GROUP(gpio38), -+ BCM63268_GROUP(gpio39), -+ BCM63268_GROUP(gpio40), -+ BCM63268_GROUP(gpio41), -+ BCM63268_GROUP(gpio42), -+ BCM63268_GROUP(gpio43), -+ BCM63268_GROUP(gpio44), -+ BCM63268_GROUP(gpio45), -+ BCM63268_GROUP(gpio46), -+ BCM63268_GROUP(gpio47), -+ BCM63268_GROUP(gpio48), -+ BCM63268_GROUP(gpio49), -+ BCM63268_GROUP(gpio50), -+ BCM63268_GROUP(gpio51), -+ -+ /* multi pin groups */ -+ BCM63268_GROUP(nand_grp), -+ BCM63268_GROUP(dectpd_grp), -+ BCM63268_GROUP(vdsl_phy0_grp), -+ BCM63268_GROUP(vdsl_phy1_grp), -+ BCM63268_GROUP(vdsl_phy2_grp), -+ BCM63268_GROUP(vdsl_phy3_grp), -+}; -+ -+static const char * const led_groups[] = { -+ "gpio0", -+ "gpio1", -+ "gpio2", -+ "gpio3", -+ "gpio4", -+ "gpio5", -+ "gpio6", -+ "gpio7", -+ "gpio8", -+ "gpio9", -+ "gpio10", -+ "gpio11", -+ "gpio12", -+ "gpio13", -+ "gpio14", -+ "gpio15", -+ "gpio16", -+ "gpio17", -+ "gpio18", -+ "gpio19", -+ "gpio20", -+ "gpio21", -+ "gpio22", -+ "gpio23", -+}; -+ -+static const char * const serial_led_clk_groups[] = { -+ "gpio0", -+}; -+ -+static const char * const serial_led_data_groups[] = { -+ "gpio1", -+}; -+ -+static const char * const hsspi_cs4_groups[] = { -+ "gpio16", -+}; -+ -+static const char * const hsspi_cs5_groups[] = { -+ "gpio17", -+}; -+ -+static const char * const hsspi_cs6_groups[] = { -+ "gpio8", -+}; -+ -+static const char * const hsspi_cs7_groups[] = { -+ "gpio9", -+}; -+ -+static const char * const uart1_scts_groups[] = { -+ "gpio10", -+ "gpio24", -+}; -+ -+static const char * const uart1_srts_groups[] = { -+ "gpio11", -+ "gpio25", -+}; -+ -+static const char * const uart1_sdin_groups[] = { -+ "gpio12", -+ "gpio26", -+}; -+ -+static const char * const uart1_sdout_groups[] = { -+ "gpio13", -+ "gpio27", -+}; -+ -+static const char * const ntr_pulse_in_groups[] = { -+ "gpio14", -+ "gpio28", -+}; -+ -+static const char * const dsl_ntr_pulse_out_groups[] = { -+ "gpio15", -+ "gpio29", -+}; -+ -+static const char * const adsl_spi_miso_groups[] = { -+ "gpio18", -+}; -+ -+static const char * const adsl_spi_mosi_groups[] = { -+ "gpio19", -+}; -+ -+static const char * const vreg_clk_groups[] = { -+ "gpio22", -+}; -+ -+static const char * const pcie_clkreq_b_groups[] = { -+ "gpio23", -+}; -+ -+static const char * const switch_led_clk_groups[] = { -+ "gpio30", -+}; -+ -+static const char * const switch_led_data_groups[] = { -+ "gpio31", -+}; -+ -+static const char * const wifi_groups[] = { -+ "gpio32", -+ "gpio33", -+ "gpio34", -+ "gpio35", -+ "gpio36", -+ "gpio37", -+ "gpio38", -+ "gpio39", -+ "gpio40", -+ "gpio41", -+ "gpio42", -+ "gpio43", -+ "gpio44", -+ "gpio45", -+ "gpio46", -+ "gpio47", -+ "gpio48", -+ "gpio49", -+ "gpio50", -+ "gpio51", -+}; -+ -+static const char * const nand_groups[] = { -+ "nand_grp", -+}; -+ -+static const char * const dectpd_groups[] = { -+ "dectpd_grp", -+}; -+ -+static const char * const vdsl_phy_override_0_groups[] = { -+ "vdsl_phy_override_0_grp", -+}; -+ -+static const char * const vdsl_phy_override_1_groups[] = { -+ "vdsl_phy_override_1_grp", -+}; -+ -+static const char * const vdsl_phy_override_2_groups[] = { -+ "vdsl_phy_override_2_grp", -+}; -+ -+static const char * const vdsl_phy_override_3_groups[] = { -+ "vdsl_phy_override_3_grp", -+}; -+ -+#define BCM63268_LED_FUN(n) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .reg = BCM63268_LEDCTRL, \ -+ } -+ -+#define BCM63268_MODE_FUN(n) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .reg = BCM63268_MODE, \ -+ } -+ -+#define BCM63268_CTRL_FUN(n) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .reg = BCM63268_CTRL, \ -+ } -+ -+#define BCM63268_BASEMODE_FUN(n, val) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .reg = BCM63268_BASEMODE, \ -+ .mask = val, \ -+ } -+ -+static const struct bcm63268_function bcm63268_funcs[] = { -+ BCM63268_LED_FUN(led), -+ BCM63268_MODE_FUN(serial_led_clk), -+ BCM63268_MODE_FUN(serial_led_data), -+ BCM63268_MODE_FUN(hsspi_cs6), -+ BCM63268_MODE_FUN(hsspi_cs7), -+ BCM63268_MODE_FUN(uart1_scts), -+ BCM63268_MODE_FUN(uart1_srts), -+ BCM63268_MODE_FUN(uart1_sdin), -+ BCM63268_MODE_FUN(uart1_sdout), -+ BCM63268_MODE_FUN(ntr_pulse_in), -+ BCM63268_MODE_FUN(dsl_ntr_pulse_out), -+ BCM63268_MODE_FUN(hsspi_cs4), -+ BCM63268_MODE_FUN(hsspi_cs5), -+ BCM63268_MODE_FUN(adsl_spi_miso), -+ BCM63268_MODE_FUN(adsl_spi_mosi), -+ BCM63268_MODE_FUN(vreg_clk), -+ BCM63268_MODE_FUN(pcie_clkreq_b), -+ BCM63268_MODE_FUN(switch_led_clk), -+ BCM63268_MODE_FUN(switch_led_data), -+ BCM63268_CTRL_FUN(wifi), -+ BCM63268_BASEMODE_FUN(nand, BCM63268_BASEMODE_NAND), -+ BCM63268_BASEMODE_FUN(dectpd, BCM63268_BASEMODE_DECTPD), -+ BCM63268_BASEMODE_FUN(vdsl_phy_override_0, -+ BCM63268_BASEMODE_VDSL_PHY_0), -+ BCM63268_BASEMODE_FUN(vdsl_phy_override_1, -+ BCM63268_BASEMODE_VDSL_PHY_1), -+ BCM63268_BASEMODE_FUN(vdsl_phy_override_2, -+ BCM63268_BASEMODE_VDSL_PHY_2), -+ BCM63268_BASEMODE_FUN(vdsl_phy_override_3, -+ BCM63268_BASEMODE_VDSL_PHY_3), -+}; -+ -+static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm63268_groups); -+} -+ -+static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev, -+ unsigned group) -+{ -+ return bcm63268_groups[group].name; -+} -+ -+static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, -+ unsigned group, -+ const unsigned **pins, -+ unsigned *num_pins) -+{ -+ *pins = bcm63268_groups[group].pins; -+ *num_pins = bcm63268_groups[group].num_pins; -+ -+ return 0; -+} -+ -+static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm63268_funcs); -+} -+ -+static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev, -+ unsigned selector) -+{ -+ return bcm63268_funcs[selector].name; -+} -+ -+static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ const char * const **groups, -+ unsigned * const num_groups) -+{ -+ *groups = bcm63268_funcs[selector].groups; -+ *num_groups = bcm63268_funcs[selector].num_groups; -+ -+ return 0; -+} -+ -+static void bcm63268_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin) -+{ -+ const struct pinctrl_pin_desc *desc = &bcm63268_pins[pin]; -+ unsigned int basemode = (unsigned long) desc->drv_data; -+ unsigned int mask = BIT(bcm63xx_bank_pin(pin)); -+ -+ if (basemode) -+ regmap_update_bits(pc->regs, BCM63268_BASEMODE_REG, basemode, -+ 0); -+ -+ if (pin < BCM63XX_BANK_GPIOS) { -+ /* base mode: 0 => gpio, 1 => mux function */ -+ regmap_update_bits(pc->regs, BCM63268_MODE_REG, mask, 0); -+ -+ /* pins 0-23 might be muxed to led */ -+ if (pin < BCM63268_NUM_LEDS) -+ regmap_update_bits(pc->regs, BCM63268_LED_REG, mask, -+ 0); -+ } else if (pin < BCM63268_NUM_GPIOS) { -+ /* ctrl reg: 0 => wifi function, 1 => gpio */ -+ regmap_update_bits(pc->regs, BCM63268_CTRL_REG, mask, mask); -+ } -+} -+ -+static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev, -+ unsigned selector, unsigned group) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ const struct bcm63268_pingroup *pg = &bcm63268_groups[group]; -+ const struct bcm63268_function *f = &bcm63268_funcs[selector]; -+ unsigned i; -+ unsigned int reg; -+ unsigned int val, mask; -+ -+ for (i = 0; i < pg->num_pins; i++) -+ bcm63268_set_gpio(pc, pg->pins[i]); -+ -+ switch (f->reg) { -+ case BCM63268_LEDCTRL: -+ reg = BCM63268_LED_REG; -+ mask = BIT(pg->pins[0]); -+ val = BIT(pg->pins[0]); -+ break; -+ case BCM63268_MODE: -+ reg = BCM63268_MODE_REG; -+ mask = BIT(pg->pins[0]); -+ val = BIT(pg->pins[0]); -+ break; -+ case BCM63268_CTRL: -+ reg = BCM63268_CTRL_REG; -+ mask = BIT(pg->pins[0]); -+ val = 0; -+ break; -+ case BCM63268_BASEMODE: -+ reg = BCM63268_BASEMODE_REG; -+ mask = f->mask; -+ val = f->mask; -+ break; -+ default: -+ WARN_ON(1); -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(pc->regs, reg, mask, val); -+ -+ return 0; -+} -+ -+static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev, -+ struct pinctrl_gpio_range *range, -+ unsigned offset) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ -+ /* disable all functions using this pin */ -+ bcm63268_set_gpio(pc, offset); -+ -+ return 0; -+} -+ -+static struct pinctrl_ops bcm63268_pctl_ops = { -+ .dt_free_map = pinctrl_utils_free_map, -+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, -+ .get_group_name = bcm63268_pinctrl_get_group_name, -+ .get_group_pins = bcm63268_pinctrl_get_group_pins, -+ .get_groups_count = bcm63268_pinctrl_get_group_count, -+}; -+ -+static struct pinmux_ops bcm63268_pmx_ops = { -+ .get_function_groups = bcm63268_pinctrl_get_groups, -+ .get_function_name = bcm63268_pinctrl_get_func_name, -+ .get_functions_count = bcm63268_pinctrl_get_func_count, -+ .gpio_request_enable = bcm63268_gpio_request_enable, -+ .set_mux = bcm63268_pinctrl_set_mux, -+ .strict = true, -+}; -+ -+static const struct bcm63xx_pinctrl_soc bcm63268_soc = { -+ .ngpios = BCM63268_NUM_GPIOS, -+ .npins = ARRAY_SIZE(bcm63268_pins), -+ .pctl_ops = &bcm63268_pctl_ops, -+ .pins = bcm63268_pins, -+ .pmx_ops = &bcm63268_pmx_ops, -+}; -+ -+static int bcm63268_pinctrl_probe(struct platform_device *pdev) -+{ -+ return bcm63xx_pinctrl_probe(pdev, &bcm63268_soc, NULL); -+} -+ -+static const struct of_device_id bcm63268_pinctrl_match[] = { -+ { .compatible = "brcm,bcm63268-pinctrl", }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver bcm63268_pinctrl_driver = { -+ .probe = bcm63268_pinctrl_probe, -+ .driver = { -+ .name = "bcm63268-pinctrl", -+ .of_match_table = bcm63268_pinctrl_match, -+ }, -+}; -+ -+builtin_platform_driver(bcm63268_pinctrl_driver); diff --git a/target/linux/bmips/patches-5.10/071-v5.13-dt-bindings-add-BCM6318-pincontroller-binding-docume.patch b/target/linux/bmips/patches-5.10/071-v5.13-dt-bindings-add-BCM6318-pincontroller-binding-docume.patch deleted file mode 100644 index 3b490da098..0000000000 --- a/target/linux/bmips/patches-5.10/071-v5.13-dt-bindings-add-BCM6318-pincontroller-binding-docume.patch +++ /dev/null @@ -1,168 +0,0 @@ -From b2f215141b985d5d39ed16fe7e2089d5aa162302 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:21 +0100 -Subject: [PATCH 20/22] dt-bindings: add BCM6318 pincontroller binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the pincontrol core found in BCM6318 SoCs. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-21-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../pinctrl/brcm,bcm6318-pinctrl.yaml | 143 ++++++++++++++++++ - 1 file changed, 143 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml -@@ -0,0 +1,143 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6318-pinctrl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6318 pin controller -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Bindings for Broadcom's BCM6318 memory-mapped pin controller. -+ -+properties: -+ compatible: -+ const: brcm,bcm6318-pinctrl -+ -+ reg: -+ maxItems: 2 -+ -+patternProperties: -+ '-pins$': -+ type: object -+ $ref: pinmux-node.yaml# -+ -+ properties: -+ function: -+ enum: [ ephy0_spd_led, ephy1_spd_led, ephy2_spd_led, ephy3_spd_led, -+ ephy0_act_led, ephy1_act_led, ephy2_act_led, ephy3_act_led, -+ serial_led_data, serial_led_clk, inet_act_led, inet_fail_led, -+ dsl_led, post_fail_led, wlan_wps_led, usb_pwron, -+ usb_device_led, usb_active ] -+ -+ pins: -+ enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, -+ gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio40 ] -+ -+required: -+ - compatible -+ - reg -+ -+additionalProperties: false -+ -+examples: -+ - | -+ pinctrl@18 { -+ compatible = "brcm,bcm6318-pinctrl"; -+ reg = <0x18 0x10>, <0x54 0x18>; -+ -+ pinctrl_ephy0_spd_led: ephy0_spd_led-pins { -+ function = "ephy0_spd_led"; -+ pins = "gpio0"; -+ }; -+ -+ pinctrl_ephy1_spd_led: ephy1_spd_led-pins { -+ function = "ephy1_spd_led"; -+ pins = "gpio1"; -+ }; -+ -+ pinctrl_ephy2_spd_led: ephy2_spd_led-pins { -+ function = "ephy2_spd_led"; -+ pins = "gpio2"; -+ }; -+ -+ pinctrl_ephy3_spd_led: ephy3_spd_led-pins { -+ function = "ephy3_spd_led"; -+ pins = "gpio3"; -+ }; -+ -+ pinctrl_ephy0_act_led: ephy0_act_led-pins { -+ function = "ephy0_act_led"; -+ pins = "gpio4"; -+ }; -+ -+ pinctrl_ephy1_act_led: ephy1_act_led-pins { -+ function = "ephy1_act_led"; -+ pins = "gpio5"; -+ }; -+ -+ pinctrl_ephy2_act_led: ephy2_act_led-pins { -+ function = "ephy2_act_led"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_ephy3_act_led: ephy3_act_led-pins { -+ function = "ephy3_act_led"; -+ pins = "gpio7"; -+ }; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio7"; -+ }; -+ }; -+ -+ pinctrl_inet_act_led: inet_act_led-pins { -+ function = "inet_act_led"; -+ pins = "gpio8"; -+ }; -+ -+ pinctrl_inet_fail_led: inet_fail_led-pins { -+ function = "inet_fail_led"; -+ pins = "gpio9"; -+ }; -+ -+ pinctrl_dsl_led: dsl_led-pins { -+ function = "dsl_led"; -+ pins = "gpio10"; -+ }; -+ -+ pinctrl_post_fail_led: post_fail_led-pins { -+ function = "post_fail_led"; -+ pins = "gpio11"; -+ }; -+ -+ pinctrl_wlan_wps_led: wlan_wps_led-pins { -+ function = "wlan_wps_led"; -+ pins = "gpio12"; -+ }; -+ -+ pinctrl_usb_pwron: usb_pwron-pins { -+ function = "usb_pwron"; -+ pins = "gpio13"; -+ }; -+ -+ pinctrl_usb_device_led: usb_device_led-pins { -+ function = "usb_device_led"; -+ pins = "gpio13"; -+ }; -+ -+ pinctrl_usb_active: usb_active-pins { -+ function = "usb_active"; -+ pins = "gpio40"; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/072-v5.13-dt-bindings-add-BCM6318-GPIO-sysctl-binding-document.patch b/target/linux/bmips/patches-5.10/072-v5.13-dt-bindings-add-BCM6318-GPIO-sysctl-binding-document.patch deleted file mode 100644 index 1ef13407c8..0000000000 --- a/target/linux/bmips/patches-5.10/072-v5.13-dt-bindings-add-BCM6318-GPIO-sysctl-binding-document.patch +++ /dev/null @@ -1,200 +0,0 @@ -From b6d46b9454742a25f9d923be072869e40b2ecebb Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:22 +0100 -Subject: [PATCH 21/22] dt-bindings: add BCM6318 GPIO sysctl binding - documentation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add binding documentation for the GPIO sysctl found in BCM6318 SoCs. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Link: https://lore.kernel.org/r/20210324081923.20379-22-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - .../mfd/brcm,bcm6318-gpio-sysctl.yaml | 177 ++++++++++++++++++ - 1 file changed, 177 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml -@@ -0,0 +1,177 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM6318 GPIO System Controller Device Tree Bindings -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ - Jonas Gorski <jonas.gorski@gmail.com> -+ -+description: -+ Broadcom BCM6318 SoC GPIO system controller which provides a register map -+ for controlling the GPIO and pins of the SoC. -+ -+properties: -+ "#address-cells": true -+ -+ "#size-cells": true -+ -+ compatible: -+ items: -+ - const: brcm,bcm6318-gpio-sysctl -+ - const: syscon -+ - const: simple-mfd -+ -+ ranges: -+ maxItems: 1 -+ -+ reg: -+ maxItems: 1 -+ -+patternProperties: -+ "^gpio@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../gpio/brcm,bcm6345-gpio.yaml" -+ description: -+ GPIO controller for the SoC GPIOs. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml. -+ -+ "^pinctrl@[0-9a-f]+$": -+ # Child node -+ type: object -+ $ref: "../pinctrl/brcm,bcm6318-pinctrl.yaml" -+ description: -+ Pin controller for the SoC pins. This child node definition -+ should follow the bindings specified in -+ Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml. -+ -+required: -+ - "#address-cells" -+ - compatible -+ - ranges -+ - reg -+ - "#size-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ syscon@10000080 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "brcm,bcm6318-gpio-sysctl", "syscon", "simple-mfd"; -+ reg = <0x10000080 0x80>; -+ ranges = <0 0x10000080 0x80>; -+ -+ gpio@0 { -+ compatible = "brcm,bcm6318-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0x0 0x8>, <0x8 0x8>; -+ -+ gpio-controller; -+ gpio-ranges = <&pinctrl 0 0 50>; -+ #gpio-cells = <2>; -+ }; -+ -+ pinctrl: pinctrl@10 { -+ compatible = "brcm,bcm6318-pinctrl"; -+ reg = <0x18 0x10>, <0x54 0x18>; -+ -+ pinctrl_ephy0_spd_led: ephy0_spd_led-pins { -+ function = "ephy0_spd_led"; -+ pins = "gpio0"; -+ }; -+ -+ pinctrl_ephy1_spd_led: ephy1_spd_led-pins { -+ function = "ephy1_spd_led"; -+ pins = "gpio1"; -+ }; -+ -+ pinctrl_ephy2_spd_led: ephy2_spd_led-pins { -+ function = "ephy2_spd_led"; -+ pins = "gpio2"; -+ }; -+ -+ pinctrl_ephy3_spd_led: ephy3_spd_led-pins { -+ function = "ephy3_spd_led"; -+ pins = "gpio3"; -+ }; -+ -+ pinctrl_ephy0_act_led: ephy0_act_led-pins { -+ function = "ephy0_act_led"; -+ pins = "gpio4"; -+ }; -+ -+ pinctrl_ephy1_act_led: ephy1_act_led-pins { -+ function = "ephy1_act_led"; -+ pins = "gpio5"; -+ }; -+ -+ pinctrl_ephy2_act_led: ephy2_act_led-pins { -+ function = "ephy2_act_led"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_ephy3_act_led: ephy3_act_led-pins { -+ function = "ephy3_act_led"; -+ pins = "gpio7"; -+ }; -+ -+ pinctrl_serial_led: serial_led-pins { -+ pinctrl_serial_led_data: serial_led_data-pins { -+ function = "serial_led_data"; -+ pins = "gpio6"; -+ }; -+ -+ pinctrl_serial_led_clk: serial_led_clk-pins { -+ function = "serial_led_clk"; -+ pins = "gpio7"; -+ }; -+ }; -+ -+ pinctrl_inet_act_led: inet_act_led-pins { -+ function = "inet_act_led"; -+ pins = "gpio8"; -+ }; -+ -+ pinctrl_inet_fail_led: inet_fail_led-pins { -+ function = "inet_fail_led"; -+ pins = "gpio9"; -+ }; -+ -+ pinctrl_dsl_led: dsl_led-pins { -+ function = "dsl_led"; -+ pins = "gpio10"; -+ }; -+ -+ pinctrl_post_fail_led: post_fail_led-pins { -+ function = "post_fail_led"; -+ pins = "gpio11"; -+ }; -+ -+ pinctrl_wlan_wps_led: wlan_wps_led-pins { -+ function = "wlan_wps_led"; -+ pins = "gpio12"; -+ }; -+ -+ pinctrl_usb_pwron: usb_pwron-pins { -+ function = "usb_pwron"; -+ pins = "gpio13"; -+ }; -+ -+ pinctrl_usb_device_led: usb_device_led-pins { -+ function = "usb_device_led"; -+ pins = "gpio13"; -+ }; -+ -+ pinctrl_usb_active: usb_active-pins { -+ function = "usb_active"; -+ pins = "gpio40"; -+ }; -+ }; -+ }; diff --git a/target/linux/bmips/patches-5.10/073-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6318.patch b/target/linux/bmips/patches-5.10/073-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6318.patch deleted file mode 100644 index afd8d9e1fa..0000000000 --- a/target/linux/bmips/patches-5.10/073-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6318.patch +++ /dev/null @@ -1,553 +0,0 @@ -From d28039fccf948a407de69106465caa465b1dcf32 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 24 Mar 2021 09:19:23 +0100 -Subject: [PATCH 22/22] pinctrl: add a pincontrol driver for BCM6318 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs -to different functions. BCM6318 is similar to BCM6328 with the addition -of a pad register, and the GPIO meaning of the mux register changes -based on the GPIO number. - -Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210324081923.20379-23-noltari@gmail.com -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/bcm/Kconfig | 8 + - drivers/pinctrl/bcm/Makefile | 1 + - drivers/pinctrl/bcm/pinctrl-bcm6318.c | 498 ++++++++++++++++++++++++++ - 3 files changed, 507 insertions(+) - create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6318.c - ---- a/drivers/pinctrl/bcm/Kconfig -+++ b/drivers/pinctrl/bcm/Kconfig -@@ -36,6 +36,14 @@ config PINCTRL_BCM63XX - select PINCONF - select PINMUX - -+config PINCTRL_BCM6318 -+ bool "Broadcom BCM6318 GPIO driver" -+ depends on (BMIPS_GENERIC || COMPILE_TEST) -+ select PINCTRL_BCM63XX -+ default BMIPS_GENERIC -+ help -+ Say Y here to enable the Broadcom BCM6318 GPIO driver. -+ - config PINCTRL_BCM6328 - bool "Broadcom BCM6328 GPIO driver" - depends on (BMIPS_GENERIC || COMPILE_TEST) ---- a/drivers/pinctrl/bcm/Makefile -+++ b/drivers/pinctrl/bcm/Makefile -@@ -4,6 +4,7 @@ - obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o - obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o - obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o -+obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o - obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o - obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o - obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o ---- /dev/null -+++ b/drivers/pinctrl/bcm/pinctrl-bcm6318.c -@@ -0,0 +1,498 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Driver for BCM6318 GPIO unit (pinctrl + GPIO) -+ * -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> -+ */ -+ -+#include <linux/bits.h> -+#include <linux/gpio/driver.h> -+#include <linux/kernel.h> -+#include <linux/of.h> -+#include <linux/pinctrl/pinmux.h> -+#include <linux/platform_device.h> -+#include <linux/regmap.h> -+ -+#include "../pinctrl-utils.h" -+ -+#include "pinctrl-bcm63xx.h" -+ -+#define BCM6318_NUM_GPIOS 50 -+#define BCM6318_NUM_MUX 48 -+ -+#define BCM6318_MODE_REG 0x18 -+#define BCM6318_MUX_REG 0x1c -+#define BCM6328_MUX_MASK GENMASK(1, 0) -+#define BCM6318_PAD_REG 0x54 -+#define BCM6328_PAD_MASK GENMASK(3, 0) -+ -+struct bcm6318_pingroup { -+ const char *name; -+ const unsigned * const pins; -+ const unsigned num_pins; -+}; -+ -+struct bcm6318_function { -+ const char *name; -+ const char * const *groups; -+ const unsigned num_groups; -+ -+ unsigned mode_val:1; -+ unsigned mux_val:2; -+}; -+ -+static const struct pinctrl_pin_desc bcm6318_pins[] = { -+ PINCTRL_PIN(0, "gpio0"), -+ PINCTRL_PIN(1, "gpio1"), -+ PINCTRL_PIN(2, "gpio2"), -+ PINCTRL_PIN(3, "gpio3"), -+ PINCTRL_PIN(4, "gpio4"), -+ PINCTRL_PIN(5, "gpio5"), -+ PINCTRL_PIN(6, "gpio6"), -+ PINCTRL_PIN(7, "gpio7"), -+ PINCTRL_PIN(8, "gpio8"), -+ PINCTRL_PIN(9, "gpio9"), -+ PINCTRL_PIN(10, "gpio10"), -+ PINCTRL_PIN(11, "gpio11"), -+ PINCTRL_PIN(12, "gpio12"), -+ PINCTRL_PIN(13, "gpio13"), -+ PINCTRL_PIN(14, "gpio14"), -+ PINCTRL_PIN(15, "gpio15"), -+ PINCTRL_PIN(16, "gpio16"), -+ PINCTRL_PIN(17, "gpio17"), -+ PINCTRL_PIN(18, "gpio18"), -+ PINCTRL_PIN(19, "gpio19"), -+ PINCTRL_PIN(20, "gpio20"), -+ PINCTRL_PIN(21, "gpio21"), -+ PINCTRL_PIN(22, "gpio22"), -+ PINCTRL_PIN(23, "gpio23"), -+ PINCTRL_PIN(24, "gpio24"), -+ PINCTRL_PIN(25, "gpio25"), -+ PINCTRL_PIN(26, "gpio26"), -+ PINCTRL_PIN(27, "gpio27"), -+ PINCTRL_PIN(28, "gpio28"), -+ PINCTRL_PIN(29, "gpio29"), -+ PINCTRL_PIN(30, "gpio30"), -+ PINCTRL_PIN(31, "gpio31"), -+ PINCTRL_PIN(32, "gpio32"), -+ PINCTRL_PIN(33, "gpio33"), -+ PINCTRL_PIN(34, "gpio34"), -+ PINCTRL_PIN(35, "gpio35"), -+ PINCTRL_PIN(36, "gpio36"), -+ PINCTRL_PIN(37, "gpio37"), -+ PINCTRL_PIN(38, "gpio38"), -+ PINCTRL_PIN(39, "gpio39"), -+ PINCTRL_PIN(40, "gpio40"), -+ PINCTRL_PIN(41, "gpio41"), -+ PINCTRL_PIN(42, "gpio42"), -+ PINCTRL_PIN(43, "gpio43"), -+ PINCTRL_PIN(44, "gpio44"), -+ PINCTRL_PIN(45, "gpio45"), -+ PINCTRL_PIN(46, "gpio46"), -+ PINCTRL_PIN(47, "gpio47"), -+ PINCTRL_PIN(48, "gpio48"), -+ PINCTRL_PIN(49, "gpio49"), -+}; -+ -+static unsigned gpio0_pins[] = { 0 }; -+static unsigned gpio1_pins[] = { 1 }; -+static unsigned gpio2_pins[] = { 2 }; -+static unsigned gpio3_pins[] = { 3 }; -+static unsigned gpio4_pins[] = { 4 }; -+static unsigned gpio5_pins[] = { 5 }; -+static unsigned gpio6_pins[] = { 6 }; -+static unsigned gpio7_pins[] = { 7 }; -+static unsigned gpio8_pins[] = { 8 }; -+static unsigned gpio9_pins[] = { 9 }; -+static unsigned gpio10_pins[] = { 10 }; -+static unsigned gpio11_pins[] = { 11 }; -+static unsigned gpio12_pins[] = { 12 }; -+static unsigned gpio13_pins[] = { 13 }; -+static unsigned gpio14_pins[] = { 14 }; -+static unsigned gpio15_pins[] = { 15 }; -+static unsigned gpio16_pins[] = { 16 }; -+static unsigned gpio17_pins[] = { 17 }; -+static unsigned gpio18_pins[] = { 18 }; -+static unsigned gpio19_pins[] = { 19 }; -+static unsigned gpio20_pins[] = { 20 }; -+static unsigned gpio21_pins[] = { 21 }; -+static unsigned gpio22_pins[] = { 22 }; -+static unsigned gpio23_pins[] = { 23 }; -+static unsigned gpio24_pins[] = { 24 }; -+static unsigned gpio25_pins[] = { 25 }; -+static unsigned gpio26_pins[] = { 26 }; -+static unsigned gpio27_pins[] = { 27 }; -+static unsigned gpio28_pins[] = { 28 }; -+static unsigned gpio29_pins[] = { 29 }; -+static unsigned gpio30_pins[] = { 30 }; -+static unsigned gpio31_pins[] = { 31 }; -+static unsigned gpio32_pins[] = { 32 }; -+static unsigned gpio33_pins[] = { 33 }; -+static unsigned gpio34_pins[] = { 34 }; -+static unsigned gpio35_pins[] = { 35 }; -+static unsigned gpio36_pins[] = { 36 }; -+static unsigned gpio37_pins[] = { 37 }; -+static unsigned gpio38_pins[] = { 38 }; -+static unsigned gpio39_pins[] = { 39 }; -+static unsigned gpio40_pins[] = { 40 }; -+static unsigned gpio41_pins[] = { 41 }; -+static unsigned gpio42_pins[] = { 42 }; -+static unsigned gpio43_pins[] = { 43 }; -+static unsigned gpio44_pins[] = { 44 }; -+static unsigned gpio45_pins[] = { 45 }; -+static unsigned gpio46_pins[] = { 46 }; -+static unsigned gpio47_pins[] = { 47 }; -+static unsigned gpio48_pins[] = { 48 }; -+static unsigned gpio49_pins[] = { 49 }; -+ -+#define BCM6318_GROUP(n) \ -+ { \ -+ .name = #n, \ -+ .pins = n##_pins, \ -+ .num_pins = ARRAY_SIZE(n##_pins), \ -+ } -+ -+static struct bcm6318_pingroup bcm6318_groups[] = { -+ BCM6318_GROUP(gpio0), -+ BCM6318_GROUP(gpio1), -+ BCM6318_GROUP(gpio2), -+ BCM6318_GROUP(gpio3), -+ BCM6318_GROUP(gpio4), -+ BCM6318_GROUP(gpio5), -+ BCM6318_GROUP(gpio6), -+ BCM6318_GROUP(gpio7), -+ BCM6318_GROUP(gpio8), -+ BCM6318_GROUP(gpio9), -+ BCM6318_GROUP(gpio10), -+ BCM6318_GROUP(gpio11), -+ BCM6318_GROUP(gpio12), -+ BCM6318_GROUP(gpio13), -+ BCM6318_GROUP(gpio14), -+ BCM6318_GROUP(gpio15), -+ BCM6318_GROUP(gpio16), -+ BCM6318_GROUP(gpio17), -+ BCM6318_GROUP(gpio18), -+ BCM6318_GROUP(gpio19), -+ BCM6318_GROUP(gpio20), -+ BCM6318_GROUP(gpio21), -+ BCM6318_GROUP(gpio22), -+ BCM6318_GROUP(gpio23), -+ BCM6318_GROUP(gpio24), -+ BCM6318_GROUP(gpio25), -+ BCM6318_GROUP(gpio26), -+ BCM6318_GROUP(gpio27), -+ BCM6318_GROUP(gpio28), -+ BCM6318_GROUP(gpio29), -+ BCM6318_GROUP(gpio30), -+ BCM6318_GROUP(gpio31), -+ BCM6318_GROUP(gpio32), -+ BCM6318_GROUP(gpio33), -+ BCM6318_GROUP(gpio34), -+ BCM6318_GROUP(gpio35), -+ BCM6318_GROUP(gpio36), -+ BCM6318_GROUP(gpio37), -+ BCM6318_GROUP(gpio38), -+ BCM6318_GROUP(gpio39), -+ BCM6318_GROUP(gpio40), -+ BCM6318_GROUP(gpio41), -+ BCM6318_GROUP(gpio42), -+ BCM6318_GROUP(gpio43), -+ BCM6318_GROUP(gpio44), -+ BCM6318_GROUP(gpio45), -+ BCM6318_GROUP(gpio46), -+ BCM6318_GROUP(gpio47), -+ BCM6318_GROUP(gpio48), -+ BCM6318_GROUP(gpio49), -+}; -+ -+/* GPIO_MODE */ -+static const char * const led_groups[] = { -+ "gpio0", -+ "gpio1", -+ "gpio2", -+ "gpio3", -+ "gpio4", -+ "gpio5", -+ "gpio6", -+ "gpio7", -+ "gpio8", -+ "gpio9", -+ "gpio10", -+ "gpio11", -+ "gpio12", -+ "gpio13", -+ "gpio14", -+ "gpio15", -+ "gpio16", -+ "gpio17", -+ "gpio18", -+ "gpio19", -+ "gpio20", -+ "gpio21", -+ "gpio22", -+ "gpio23", -+}; -+ -+/* PINMUX_SEL */ -+static const char * const ephy0_spd_led_groups[] = { -+ "gpio0", -+}; -+ -+static const char * const ephy1_spd_led_groups[] = { -+ "gpio1", -+}; -+ -+static const char * const ephy2_spd_led_groups[] = { -+ "gpio2", -+}; -+ -+static const char * const ephy3_spd_led_groups[] = { -+ "gpio3", -+}; -+ -+static const char * const ephy0_act_led_groups[] = { -+ "gpio4", -+}; -+ -+static const char * const ephy1_act_led_groups[] = { -+ "gpio5", -+}; -+ -+static const char * const ephy2_act_led_groups[] = { -+ "gpio6", -+}; -+ -+static const char * const ephy3_act_led_groups[] = { -+ "gpio7", -+}; -+ -+static const char * const serial_led_data_groups[] = { -+ "gpio6", -+}; -+ -+static const char * const serial_led_clk_groups[] = { -+ "gpio7", -+}; -+ -+static const char * const inet_act_led_groups[] = { -+ "gpio8", -+}; -+ -+static const char * const inet_fail_led_groups[] = { -+ "gpio9", -+}; -+ -+static const char * const dsl_led_groups[] = { -+ "gpio10", -+}; -+ -+static const char * const post_fail_led_groups[] = { -+ "gpio11", -+}; -+ -+static const char * const wlan_wps_led_groups[] = { -+ "gpio12", -+}; -+ -+static const char * const usb_pwron_groups[] = { -+ "gpio13", -+}; -+ -+static const char * const usb_device_led_groups[] = { -+ "gpio13", -+}; -+ -+static const char * const usb_active_groups[] = { -+ "gpio40", -+}; -+ -+#define BCM6318_MODE_FUN(n) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .mode_val = 1, \ -+ } -+ -+#define BCM6318_MUX_FUN(n, mux) \ -+ { \ -+ .name = #n, \ -+ .groups = n##_groups, \ -+ .num_groups = ARRAY_SIZE(n##_groups), \ -+ .mux_val = mux, \ -+ } -+ -+static const struct bcm6318_function bcm6318_funcs[] = { -+ BCM6318_MODE_FUN(led), -+ BCM6318_MUX_FUN(ephy0_spd_led, 1), -+ BCM6318_MUX_FUN(ephy1_spd_led, 1), -+ BCM6318_MUX_FUN(ephy2_spd_led, 1), -+ BCM6318_MUX_FUN(ephy3_spd_led, 1), -+ BCM6318_MUX_FUN(ephy0_act_led, 1), -+ BCM6318_MUX_FUN(ephy1_act_led, 1), -+ BCM6318_MUX_FUN(ephy2_act_led, 1), -+ BCM6318_MUX_FUN(ephy3_act_led, 1), -+ BCM6318_MUX_FUN(serial_led_data, 3), -+ BCM6318_MUX_FUN(serial_led_clk, 3), -+ BCM6318_MUX_FUN(inet_act_led, 1), -+ BCM6318_MUX_FUN(inet_fail_led, 1), -+ BCM6318_MUX_FUN(dsl_led, 1), -+ BCM6318_MUX_FUN(post_fail_led, 1), -+ BCM6318_MUX_FUN(wlan_wps_led, 1), -+ BCM6318_MUX_FUN(usb_pwron, 1), -+ BCM6318_MUX_FUN(usb_device_led, 2), -+ BCM6318_MUX_FUN(usb_active, 2), -+}; -+ -+static inline unsigned int bcm6318_mux_off(unsigned int pin) -+{ -+ return BCM6318_MUX_REG + (pin / 16) * 4; -+} -+ -+static inline unsigned int bcm6318_pad_off(unsigned int pin) -+{ -+ return BCM6318_PAD_REG + (pin / 8) * 4; -+} -+ -+static int bcm6318_pinctrl_get_group_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6318_groups); -+} -+ -+static const char *bcm6318_pinctrl_get_group_name(struct pinctrl_dev *pctldev, -+ unsigned group) -+{ -+ return bcm6318_groups[group].name; -+} -+ -+static int bcm6318_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, -+ unsigned group, const unsigned **pins, -+ unsigned *num_pins) -+{ -+ *pins = bcm6318_groups[group].pins; -+ *num_pins = bcm6318_groups[group].num_pins; -+ -+ return 0; -+} -+ -+static int bcm6318_pinctrl_get_func_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(bcm6318_funcs); -+} -+ -+static const char *bcm6318_pinctrl_get_func_name(struct pinctrl_dev *pctldev, -+ unsigned selector) -+{ -+ return bcm6318_funcs[selector].name; -+} -+ -+static int bcm6318_pinctrl_get_groups(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ const char * const **groups, -+ unsigned * const num_groups) -+{ -+ *groups = bcm6318_funcs[selector].groups; -+ *num_groups = bcm6318_funcs[selector].num_groups; -+ -+ return 0; -+} -+ -+static inline void bcm6318_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin, -+ unsigned int mode, unsigned int mux) -+{ -+ if (pin < BCM63XX_BANK_GPIOS) -+ regmap_update_bits(pc->regs, BCM6318_MODE_REG, BIT(pin), -+ mode ? BIT(pin) : 0); -+ -+ if (pin < BCM6318_NUM_MUX) -+ regmap_update_bits(pc->regs, -+ bcm6318_mux_off(pin), -+ BCM6328_MUX_MASK << ((pin % 16) * 2), -+ mux << ((pin % 16) * 2)); -+} -+ -+static inline void bcm6318_set_pad(struct bcm63xx_pinctrl *pc, unsigned pin, -+ uint8_t val) -+{ -+ regmap_update_bits(pc->regs, bcm6318_pad_off(pin), -+ BCM6328_PAD_MASK << ((pin % 8) * 4), -+ val << ((pin % 8) * 4)); -+} -+ -+static int bcm6318_pinctrl_set_mux(struct pinctrl_dev *pctldev, -+ unsigned selector, unsigned group) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ const struct bcm6318_pingroup *pg = &bcm6318_groups[group]; -+ const struct bcm6318_function *f = &bcm6318_funcs[selector]; -+ -+ bcm6318_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val); -+ -+ return 0; -+} -+ -+static int bcm6318_gpio_request_enable(struct pinctrl_dev *pctldev, -+ struct pinctrl_gpio_range *range, -+ unsigned offset) -+{ -+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); -+ -+ /* disable all functions using this pin */ -+ if (offset < 13) { -+ /* GPIOs 0-12 use mux 0 as GPIO function */ -+ bcm6318_rmw_mux(pc, offset, 0, 0); -+ } else if (offset < 42) { -+ /* GPIOs 13-41 use mux 3 as GPIO function */ -+ bcm6318_rmw_mux(pc, offset, 0, 3); -+ -+ bcm6318_set_pad(pc, offset, 0); -+ } -+ -+ return 0; -+} -+ -+static struct pinctrl_ops bcm6318_pctl_ops = { -+ .dt_free_map = pinctrl_utils_free_map, -+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, -+ .get_group_name = bcm6318_pinctrl_get_group_name, -+ .get_group_pins = bcm6318_pinctrl_get_group_pins, -+ .get_groups_count = bcm6318_pinctrl_get_group_count, -+}; -+ -+static struct pinmux_ops bcm6318_pmx_ops = { -+ .get_function_groups = bcm6318_pinctrl_get_groups, -+ .get_function_name = bcm6318_pinctrl_get_func_name, -+ .get_functions_count = bcm6318_pinctrl_get_func_count, -+ .gpio_request_enable = bcm6318_gpio_request_enable, -+ .set_mux = bcm6318_pinctrl_set_mux, -+ .strict = true, -+}; -+ -+static const struct bcm63xx_pinctrl_soc bcm6318_soc = { -+ .ngpios = BCM6318_NUM_GPIOS, -+ .npins = ARRAY_SIZE(bcm6318_pins), -+ .pctl_ops = &bcm6318_pctl_ops, -+ .pins = bcm6318_pins, -+ .pmx_ops = &bcm6318_pmx_ops, -+}; -+ -+static int bcm6318_pinctrl_probe(struct platform_device *pdev) -+{ -+ return bcm63xx_pinctrl_probe(pdev, &bcm6318_soc, NULL); -+} -+ -+static const struct of_device_id bcm6318_pinctrl_match[] = { -+ { .compatible = "brcm,bcm6318-pinctrl", }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver bcm6318_pinctrl_driver = { -+ .probe = bcm6318_pinctrl_probe, -+ .driver = { -+ .name = "bcm6318-pinctrl", -+ .of_match_table = bcm6318_pinctrl_match, -+ }, -+}; -+ -+builtin_platform_driver(bcm6318_pinctrl_driver); diff --git a/target/linux/bmips/patches-5.10/074-v5.13-pinctrl-bcm-bcm6362-fix-warning.patch b/target/linux/bmips/patches-5.10/074-v5.13-pinctrl-bcm-bcm6362-fix-warning.patch deleted file mode 100644 index 92da534af9..0000000000 --- a/target/linux/bmips/patches-5.10/074-v5.13-pinctrl-bcm-bcm6362-fix-warning.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 1978d88cdc8eb0986d36cac0e9541220fa71d87d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Tue, 30 Mar 2021 12:32:25 +0200 -Subject: [PATCH] pinctrl: bcm: bcm6362: fix warning -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The current implementation of bcm6362_set_gpio() produces the following -warning on x86_64: -drivers/pinctrl/bcm/pinctrl-bcm6362.c: In function 'bcm6362_set_gpio': -drivers/pinctrl/bcm/pinctrl-bcm6362.c:503:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] - 503 | (uint32_t) desc->drv_data, 0); - | ^ - -Modify the code to make it similar to bcm63268_set_gpio() in order to fix -the warning. - -Fixes: 705791e23ecd ("pinctrl: add a pincontrol driver for BCM6362") -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Link: https://lore.kernel.org/r/20210330103225.3949-1-noltari@gmail.com -Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/bcm/pinctrl-bcm6362.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/pinctrl/bcm/pinctrl-bcm6362.c -+++ b/drivers/pinctrl/bcm/pinctrl-bcm6362.c -@@ -496,11 +496,11 @@ static int bcm6362_pinctrl_get_groups(st - static void bcm6362_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin) - { - const struct pinctrl_pin_desc *desc = &bcm6362_pins[pin]; -+ unsigned int basemode = (uintptr_t)desc->drv_data; - unsigned int mask = bcm63xx_bank_pin(pin); - -- if (desc->drv_data) -- regmap_update_bits(pc->regs, BCM6362_BASEMODE_REG, -- (uint32_t) desc->drv_data, 0); -+ if (basemode) -+ regmap_update_bits(pc->regs, BCM6362_BASEMODE_REG, basemode, 0); - - if (pin < BCM63XX_BANK_GPIOS) { - /* base mode 0 => gpio 1 => mux function */ diff --git a/target/linux/bmips/patches-5.10/075-v5.13-pinctrl-bcm63xx-Fix-dependencies.patch b/target/linux/bmips/patches-5.10/075-v5.13-pinctrl-bcm63xx-Fix-dependencies.patch deleted file mode 100644 index bf27683438..0000000000 --- a/target/linux/bmips/patches-5.10/075-v5.13-pinctrl-bcm63xx-Fix-dependencies.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 26ea7ac92836ba616f75a1ab57e64ffc21da7758 Mon Sep 17 00:00:00 2001 -From: Linus Walleij <linus.walleij@linaro.org> -Date: Wed, 31 Mar 2021 14:45:05 +0200 -Subject: [PATCH] pinctrl: bcm63xx: Fix dependencies -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add depends on OF so we don't get weird build errors on -randconfig. - -Also order selects the same as the other drivers for -pure aestetic reasons. - -Reported-by: Randy Dunlap <rdunlap@infradead.org> -Cc: Álvaro Fernández Rojas <noltari@gmail.com> -Signed-off-by: Linus Walleij <linus.walleij@linaro.org> ---- - drivers/pinctrl/bcm/Kconfig | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/pinctrl/bcm/Kconfig -+++ b/drivers/pinctrl/bcm/Kconfig -@@ -31,10 +31,12 @@ config PINCTRL_BCM2835 - - config PINCTRL_BCM63XX - bool -+ depends on OF -+ select PINMUX -+ select PINCONF - select GENERIC_PINCONF -+ select GPIOLIB - select GPIO_REGMAP -- select PINCONF -- select PINMUX - - config PINCTRL_BCM6318 - bool "Broadcom BCM6318 GPIO driver" diff --git a/target/linux/bmips/patches-5.10/080-v5.14-watchdog-bcm7038_wdt-add-big-endian-support.patch b/target/linux/bmips/patches-5.10/080-v5.14-watchdog-bcm7038_wdt-add-big-endian-support.patch deleted file mode 100644 index 3ddba6c937..0000000000 --- a/target/linux/bmips/patches-5.10/080-v5.14-watchdog-bcm7038_wdt-add-big-endian-support.patch +++ /dev/null @@ -1,86 +0,0 @@ -From e379c2199de4280243e43118dceb4ea5e97059a3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Tue, 23 Feb 2021 09:00:42 +0100 -Subject: [PATCH] watchdog: bcm7038_wdt: add big endian support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -bcm7038_wdt can be used on bmips big endian (bcm63xx) devices too. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Reviewed-by: Guenter Roeck <linux@roeck-us.net> -Link: https://lore.kernel.org/r/20210223080042.29569-1-noltari@gmail.com -Signed-off-by: Guenter Roeck <linux@roeck-us.net> -Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org> ---- - drivers/watchdog/bcm7038_wdt.c | 31 +++++++++++++++++++++++++------ - 1 file changed, 25 insertions(+), 6 deletions(-) - ---- a/drivers/watchdog/bcm7038_wdt.c -+++ b/drivers/watchdog/bcm7038_wdt.c -@@ -34,6 +34,25 @@ struct bcm7038_watchdog { - - static bool nowayout = WATCHDOG_NOWAYOUT; - -+static inline void bcm7038_wdt_write(u32 value, void __iomem *addr) -+{ -+ /* MIPS chips strapped for BE will automagically configure the -+ * peripheral registers for CPU-native byte order. -+ */ -+ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) -+ __raw_writel(value, addr); -+ else -+ writel_relaxed(value, addr); -+} -+ -+static inline u32 bcm7038_wdt_read(void __iomem *addr) -+{ -+ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) -+ return __raw_readl(addr); -+ else -+ return readl_relaxed(addr); -+} -+ - static void bcm7038_wdt_set_timeout_reg(struct watchdog_device *wdog) - { - struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); -@@ -41,15 +60,15 @@ static void bcm7038_wdt_set_timeout_reg( - - timeout = wdt->rate * wdog->timeout; - -- writel(timeout, wdt->base + WDT_TIMEOUT_REG); -+ bcm7038_wdt_write(timeout, wdt->base + WDT_TIMEOUT_REG); - } - - static int bcm7038_wdt_ping(struct watchdog_device *wdog) - { - struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); - -- writel(WDT_START_1, wdt->base + WDT_CMD_REG); -- writel(WDT_START_2, wdt->base + WDT_CMD_REG); -+ bcm7038_wdt_write(WDT_START_1, wdt->base + WDT_CMD_REG); -+ bcm7038_wdt_write(WDT_START_2, wdt->base + WDT_CMD_REG); - - return 0; - } -@@ -66,8 +85,8 @@ static int bcm7038_wdt_stop(struct watch - { - struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); - -- writel(WDT_STOP_1, wdt->base + WDT_CMD_REG); -- writel(WDT_STOP_2, wdt->base + WDT_CMD_REG); -+ bcm7038_wdt_write(WDT_STOP_1, wdt->base + WDT_CMD_REG); -+ bcm7038_wdt_write(WDT_STOP_2, wdt->base + WDT_CMD_REG); - - return 0; - } -@@ -88,7 +107,7 @@ static unsigned int bcm7038_wdt_get_time - struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); - u32 time_left; - -- time_left = readl(wdt->base + WDT_CMD_REG); -+ time_left = bcm7038_wdt_read(wdt->base + WDT_CMD_REG); - - return time_left / wdt->rate; - } diff --git a/target/linux/bmips/patches-5.10/100-irqchip-add-support-for-bcm6345-style-external-inter.patch b/target/linux/bmips/patches-5.10/100-irqchip-add-support-for-bcm6345-style-external-inter.patch deleted file mode 100644 index ebaf89fad0..0000000000 --- a/target/linux/bmips/patches-5.10/100-irqchip-add-support-for-bcm6345-style-external-inter.patch +++ /dev/null @@ -1,392 +0,0 @@ -From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Sun, 30 Nov 2014 14:54:27 +0100 -Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external - interrupt controller - -Signed-off-by: Jonas Gorski <jogo@openwrt.org> ---- - .../interrupt-controller/brcm,bcm6345-ext-intc.txt | 29 ++ - drivers/irqchip/Kconfig | 4 + - drivers/irqchip/Makefile | 1 + - drivers/irqchip/irq-bcm6345-ext.c | 287 ++++++++++++++++++++ - include/linux/irqchip/irq-bcm6345-ext.h | 14 + - 5 files changed, 335 insertions(+) - create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt - create mode 100644 drivers/irqchip/irq-bcm6345-ext.c - create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h - ---- /dev/null -+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt -@@ -0,0 +1,29 @@ -+Broadcom BCM6345-style external interrupt controller -+ -+Required properties: -+ -+- compatible: Should be "brcm,bcm6345-ext-intc" or "brcm,bcm6318-ext-intc". -+- reg: Specifies the base physical addresses and size of the registers. -+- interrupt-controller: identifies the node as an interrupt controller. -+- #interrupt-cells: Specifies the number of cells needed to encode an interrupt -+ source, Should be 2. -+- interrupt-parent: Specifies the phandle to the parent interrupt controller -+ this one is cascaded from. -+- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller -+ node, valid values depend on the type of parent interrupt controller. -+ -+Optional properties: -+ -+- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the -+ register. Defaults to 4. -+ -+Example: -+ -+ext_intc: interrupt-controller@10000018 { -+ compatible = "brcm,bcm6345-ext-intc"; -+ interrupt-parent = <&periph_intc>; -+ #interrupt-cells = <2>; -+ reg = <0x10000018 0x4>; -+ interrupt-controller; -+ interrupts = <24>, <25>, <26>, <27>; -+}; ---- a/drivers/irqchip/Kconfig -+++ b/drivers/irqchip/Kconfig -@@ -113,6 +113,10 @@ config I8259 - bool - select IRQ_DOMAIN - -+config BCM6345_EXT_IRQ -+ bool "BCM6345 External IRQ Controller" -+ select IRQ_DOMAIN -+ - config BCM6345_L1_IRQ - bool - select GENERIC_IRQ_CHIP ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -63,6 +63,7 @@ obj-$(CONFIG_XTENSA_MX) += irq-xtensa- - obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o - obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o - obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o -+obj-$(CONFIG_BCM6345_EXT_IRQ) += irq-bcm6345-ext.o - obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o - obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o - obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o ---- /dev/null -+++ b/drivers/irqchip/irq-bcm6345-ext.c -@@ -0,0 +1,299 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org> -+ */ -+ -+#include <linux/ioport.h> -+#include <linux/irq.h> -+#include <linux/irqchip.h> -+#include <linux/irqchip/chained_irq.h> -+#include <linux/irqchip/irq-bcm6345-ext.h> -+#include <linux/kernel.h> -+#include <linux/of.h> -+#include <linux/of_irq.h> -+#include <linux/of_address.h> -+#include <linux/slab.h> -+#include <linux/spinlock.h> -+ -+#ifdef CONFIG_BCM63XX -+#include <asm/mach-bcm63xx/bcm63xx_irq.h> -+ -+#define VIRQ_BASE IRQ_EXTERNAL_BASE -+#else -+#define VIRQ_BASE 0 -+#endif -+ -+#define MAX_IRQS 4 -+ -+#define EXTIRQ_CFG_SENSE 0 -+#define EXTIRQ_CFG_STAT 1 -+#define EXTIRQ_CFG_CLEAR 2 -+#define EXTIRQ_CFG_MASK 3 -+#define EXTIRQ_CFG_BOTHEDGE 4 -+#define EXTIRQ_CFG_LEVELSENSE 5 -+ -+struct intc_data { -+ struct irq_chip chip; -+ struct irq_domain *domain; -+ raw_spinlock_t lock; -+ -+ int parent_irq[MAX_IRQS]; -+ void __iomem *reg; -+ int shift; -+ unsigned int toggle_clear_on_ack:1; -+}; -+ -+static void bcm6345_ext_intc_irq_handle(struct irq_desc *desc) -+{ -+ struct intc_data *data = irq_desc_get_handler_data(desc); -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ unsigned int irq = irq_desc_get_irq(desc); -+ unsigned int idx; -+ -+ chained_irq_enter(chip, desc); -+ -+ for (idx = 0; idx < MAX_IRQS; idx++) { -+ if (data->parent_irq[idx] != irq) -+ continue; -+ -+ generic_handle_irq(irq_find_mapping(data->domain, idx)); -+ } -+ -+ chained_irq_exit(chip, desc); -+} -+ -+static void bcm6345_ext_intc_irq_ack(struct irq_data *data) -+{ -+ struct intc_data *priv = data->domain->host_data; -+ irq_hw_number_t hwirq = irqd_to_hwirq(data); -+ u32 reg; -+ -+ raw_spin_lock(&priv->lock); -+ reg = __raw_readl(priv->reg); -+ __raw_writel(reg | (1 << (hwirq + EXTIRQ_CFG_CLEAR * priv->shift)), -+ priv->reg); -+ if (priv->toggle_clear_on_ack) -+ __raw_writel(reg, priv->reg); -+ raw_spin_unlock(&priv->lock); -+} -+ -+static void bcm6345_ext_intc_irq_mask(struct irq_data *data) -+{ -+ struct intc_data *priv = data->domain->host_data; -+ irq_hw_number_t hwirq = irqd_to_hwirq(data); -+ u32 reg; -+ -+ raw_spin_lock(&priv->lock); -+ reg = __raw_readl(priv->reg); -+ reg &= ~(1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift)); -+ __raw_writel(reg, priv->reg); -+ raw_spin_unlock(&priv->lock); -+} -+ -+static void bcm6345_ext_intc_irq_unmask(struct irq_data *data) -+{ -+ struct intc_data *priv = data->domain->host_data; -+ irq_hw_number_t hwirq = irqd_to_hwirq(data); -+ u32 reg; -+ -+ raw_spin_lock(&priv->lock); -+ reg = __raw_readl(priv->reg); -+ reg |= 1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift); -+ __raw_writel(reg, priv->reg); -+ raw_spin_unlock(&priv->lock); -+} -+ -+static int bcm6345_ext_intc_set_type(struct irq_data *data, -+ unsigned int flow_type) -+{ -+ struct intc_data *priv = data->domain->host_data; -+ irq_hw_number_t hwirq = irqd_to_hwirq(data); -+ bool levelsense = 0, sense = 0, bothedge = 0; -+ u32 reg; -+ -+ flow_type &= IRQ_TYPE_SENSE_MASK; -+ -+ if (flow_type == IRQ_TYPE_NONE) -+ flow_type = IRQ_TYPE_LEVEL_LOW; -+ -+ switch (flow_type) { -+ case IRQ_TYPE_EDGE_BOTH: -+ bothedge = 1; -+ break; -+ -+ case IRQ_TYPE_EDGE_RISING: -+ sense = 1; -+ break; -+ -+ case IRQ_TYPE_EDGE_FALLING: -+ break; -+ -+ case IRQ_TYPE_LEVEL_HIGH: -+ levelsense = 1; -+ sense = 1; -+ break; -+ -+ case IRQ_TYPE_LEVEL_LOW: -+ levelsense = 1; -+ break; -+ -+ default: -+ pr_err("bogus flow type combination given!\n"); -+ return -EINVAL; -+ } -+ -+ raw_spin_lock(&priv->lock); -+ reg = __raw_readl(priv->reg); -+ -+ if (levelsense) -+ reg |= 1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift); -+ else -+ reg &= ~(1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift)); -+ if (sense) -+ reg |= 1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift); -+ else -+ reg &= ~(1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift)); -+ if (bothedge) -+ reg |= 1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift); -+ else -+ reg &= ~(1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift)); -+ -+ __raw_writel(reg, priv->reg); -+ raw_spin_unlock(&priv->lock); -+ -+ irqd_set_trigger_type(data, flow_type); -+ if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) -+ irq_set_handler_locked(data, handle_level_irq); -+ else -+ irq_set_handler_locked(data, handle_edge_irq); -+ -+ return 0; -+} -+ -+static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq, -+ irq_hw_number_t hw) -+{ -+ struct intc_data *priv = d->host_data; -+ -+ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops bcm6345_ext_domain_ops = { -+ .xlate = irq_domain_xlate_twocell, -+ .map = bcm6345_ext_intc_map, -+}; -+ -+static int __init __bcm6345_ext_intc_init(struct device_node *node, -+ int num_irqs, int *irqs, -+ void __iomem *reg, int shift, -+ bool toggle_clear_on_ack) -+{ -+ struct intc_data *data; -+ unsigned int i; -+ int start = VIRQ_BASE; -+ -+ data = kzalloc(sizeof(*data), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ raw_spin_lock_init(&data->lock); -+ -+ for (i = 0; i < num_irqs; i++) { -+ data->parent_irq[i] = irqs[i]; -+ -+ irq_set_handler_data(irqs[i], data); -+ irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle); -+ } -+ -+ data->reg = reg; -+ data->shift = shift; -+ data->toggle_clear_on_ack = toggle_clear_on_ack; -+ -+ data->chip.name = "bcm6345-ext-intc"; -+ data->chip.irq_ack = bcm6345_ext_intc_irq_ack; -+ data->chip.irq_mask = bcm6345_ext_intc_irq_mask; -+ data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask; -+ data->chip.irq_set_type = bcm6345_ext_intc_set_type; -+ -+ /* -+ * If we have less than 4 irqs, this is the second controller on -+ * bcm63xx. So increase the VIRQ start to not overlap with the first -+ * one, but only do so if we actually use a non-zero start. -+ * -+ * This can be removed when bcm63xx has no legacy users anymore. -+ */ -+ if (start && num_irqs < 4) -+ start += 4; -+ -+ data->domain = irq_domain_add_simple(node, num_irqs, start, -+ &bcm6345_ext_domain_ops, data); -+ if (!data->domain) { -+ kfree(data); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg, -+ int shift) -+{ -+ __bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift, false); -+} -+ -+#ifdef CONFIG_OF -+static int __init bcm6345_ext_intc_of_init(struct device_node *node, -+ struct device_node *parent) -+{ -+ int num_irqs, ret = -EINVAL; -+ unsigned i; -+ void __iomem *base; -+ int irqs[MAX_IRQS] = { 0 }; -+ u32 shift; -+ bool toggle_clear_on_ack = false; -+ -+ num_irqs = of_irq_count(node); -+ -+ if (!num_irqs || num_irqs > MAX_IRQS) -+ return -EINVAL; -+ -+ if (of_property_read_u32(node, "brcm,field-width", &shift)) -+ shift = 4; -+ -+ /* on BCM6318 setting CLEAR seems to continuously mask interrupts */ -+ if (of_device_is_compatible(node, "brcm,bcm6318-ext-intc")) -+ toggle_clear_on_ack = true; -+ -+ for (i = 0; i < num_irqs; i++) { -+ irqs[i] = irq_of_parse_and_map(node, i); -+ if (!irqs[i]) -+ return -ENOMEM; -+ } -+ -+ base = of_iomap(node, 0); -+ if (!base) -+ return -ENXIO; -+ -+ ret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift, -+ toggle_clear_on_ack); -+ if (!ret) -+ return 0; -+ -+ iounmap(base); -+ -+ for (i = 0; i < num_irqs; i++) -+ irq_dispose_mapping(irqs[i]); -+ -+ return ret; -+} -+ -+IRQCHIP_DECLARE(bcm6318_ext_intc, "brcm,bcm6318-ext-intc", -+ bcm6345_ext_intc_of_init); -+IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc", -+ bcm6345_ext_intc_of_init); -+#endif ---- /dev/null -+++ b/include/linux/irqchip/irq-bcm6345-ext.h -@@ -0,0 +1,14 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org> -+ */ -+ -+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H -+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H -+ -+void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift); -+ -+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */ diff --git a/target/linux/bmips/patches-5.10/110-mips-bmips-add-BCM63268-timer-clock-definitions.patch b/target/linux/bmips/patches-5.10/110-mips-bmips-add-BCM63268-timer-clock-definitions.patch deleted file mode 100644 index 0df7db9717..0000000000 --- a/target/linux/bmips/patches-5.10/110-mips-bmips-add-BCM63268-timer-clock-definitions.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 5a079515cb3066aeb658634301a98871b47c2af4 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Thu, 25 Feb 2021 19:44:22 +0100 -Subject: [PATCH 1/4] mips: bmips: add BCM63268 timer clock definitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add missing timer clock definitions for BCM63268. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> ---- - include/dt-bindings/clock/bcm63268-clock.h | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/include/dt-bindings/clock/bcm63268-clock.h -+++ b/include/dt-bindings/clock/bcm63268-clock.h -@@ -27,4 +27,17 @@ - #define BCM63268_CLK_TBUS 27 - #define BCM63268_CLK_ROBOSW250 31 - -+#define BCM63268_TCLK_EPHY1 0 -+#define BCM63268_TCLK_EPHY2 1 -+#define BCM63268_TCLK_EPHY3 2 -+#define BCM63268_TCLK_GPHY1 3 -+#define BCM63268_TCLK_DSL 4 -+#define BCM63268_TCLK_WAKEON_EPHY 6 -+#define BCM63268_TCLK_WAKEON_DSL 7 -+#define BCM63268_TCLK_FAP1 11 -+#define BCM63268_TCLK_FAP2 15 -+#define BCM63268_TCLK_UTO_50 16 -+#define BCM63268_TCLK_UTO_EXTIN 17 -+#define BCM63268_TCLK_USB_REF 18 -+ - #endif /* __DT_BINDINGS_CLOCK_BCM63268_H */ diff --git a/target/linux/bmips/patches-5.10/111-mips-bmips-add-BCM63268-timer-reset-definitions.patch b/target/linux/bmips/patches-5.10/111-mips-bmips-add-BCM63268-timer-reset-definitions.patch deleted file mode 100644 index 7b694d3289..0000000000 --- a/target/linux/bmips/patches-5.10/111-mips-bmips-add-BCM63268-timer-reset-definitions.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 3327df17635dd9d24a855ac6b7247fac381514cf Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Thu, 25 Feb 2021 19:45:04 +0100 -Subject: [PATCH 2/4] mips: bmips: add BCM63268 timer reset definitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add missing timer reset definitions for BCM63268. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> ---- - include/dt-bindings/reset/bcm63268-reset.h | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/include/dt-bindings/reset/bcm63268-reset.h -+++ b/include/dt-bindings/reset/bcm63268-reset.h -@@ -23,4 +23,8 @@ - #define BCM63268_RST_PCIE_HARD 17 - #define BCM63268_RST_GPHY 18 - -+#define BCM63268_TRST_SW 29 -+#define BCM63268_TRST_HW 30 -+#define BCM63268_TRST_POR 31 -+ - #endif /* __DT_BINDINGS_RESET_BCM63268_H */ diff --git a/target/linux/bmips/patches-5.10/112-dt-bindings-clock-Add-BCM63268-timer-binding.patch b/target/linux/bmips/patches-5.10/112-dt-bindings-clock-Add-BCM63268-timer-binding.patch deleted file mode 100644 index 945bdfc3d0..0000000000 --- a/target/linux/bmips/patches-5.10/112-dt-bindings-clock-Add-BCM63268-timer-binding.patch +++ /dev/null @@ -1,59 +0,0 @@ -From c17702bad18a085ae913752b45bcc20c2cea879e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Thu, 25 Feb 2021 19:53:08 +0100 -Subject: [PATCH 3/4] dt-bindings: clock: Add BCM63268 timer binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Document the Broadcom BCM63268 Clock and Reset controller. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> ---- - .../clock/brcm,bcm63268-timer-clocks.yaml | 40 +++++++++++++++++++ - 1 file changed, 40 insertions(+) - create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml -@@ -0,0 +1,40 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM63268 Timer Clock and Reset Device Tree Bindings -+ -+maintainers: -+ - Álvaro Fernández Rojas <noltari@gmail.com> -+ -+properties: -+ compatible: -+ const: brcm,bcm63268-timer-clocks -+ -+ reg: -+ maxItems: 1 -+ -+ "#clock-cells": -+ const: 1 -+ -+ "#reset-cells": -+ const: 1 -+ -+required: -+ - compatible -+ - reg -+ - "#clock-cells" -+ - "#reset-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ timer_clk: clock-controller@100000ac { -+ compatible = "brcm,bcm63268-timer-clocks"; -+ reg = <0x100000ac 0x4>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; diff --git a/target/linux/bmips/patches-5.10/113-clk-bcm-Add-BCM63268-timer-clock-and-reset-driver.patch b/target/linux/bmips/patches-5.10/113-clk-bcm-Add-BCM63268-timer-clock-and-reset-driver.patch deleted file mode 100644 index 484647a6e1..0000000000 --- a/target/linux/bmips/patches-5.10/113-clk-bcm-Add-BCM63268-timer-clock-and-reset-driver.patch +++ /dev/null @@ -1,281 +0,0 @@ -From 3c8dd9d0937a19f3f20f28ba0b0b64f448d50dd4 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Thu, 25 Feb 2021 19:54:04 +0100 -Subject: [PATCH 4/4] clk: bcm: Add BCM63268 timer clock and reset driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add driver for BCM63268 timer clock and reset controller. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> ---- - drivers/clk/bcm/Kconfig | 9 ++ - drivers/clk/bcm/Makefile | 1 + - drivers/clk/bcm/clk-bcm63268-timer.c | 232 +++++++++++++++++++++++++++ - 3 files changed, 242 insertions(+) - create mode 100644 drivers/clk/bcm/clk-bcm63268-timer.c - ---- a/drivers/clk/bcm/Kconfig -+++ b/drivers/clk/bcm/Kconfig -@@ -37,6 +37,15 @@ config CLK_BCM_63XX_GATE - Enable common clock framework support for Broadcom BCM63xx DSL SoCs - based on the MIPS architecture - -+config CLK_BCM63268_TIMER -+ bool "Broadcom BCM63268 timer clock and reset support" -+ depends on BMIPS_GENERIC || COMPILE_TEST -+ default BMIPS_GENERIC -+ select RESET_CONTROLLER -+ help -+ Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs -+ based on the MIPS architecture. -+ - config CLK_BCM_KONA - bool "Broadcom Kona CCU clock support" - depends on ARCH_BCM_MOBILE || COMPILE_TEST ---- a/drivers/clk/bcm/Makefile -+++ b/drivers/clk/bcm/Makefile -@@ -1,6 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o - obj-$(CONFIG_CLK_BCM_63XX_GATE) += clk-bcm63xx-gate.o -+obj-$(CONFIG_CLK_BCM63268_TIMER) += clk-bcm63268-timer.o - obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o - obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o - obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o ---- /dev/null -+++ b/drivers/clk/bcm/clk-bcm63268-timer.c -@@ -0,0 +1,232 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * BCM63268 Timer Clock and Reset Controller Driver -+ * -+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com> -+ */ -+ -+#include <linux/clk-provider.h> -+#include <linux/delay.h> -+#include <linux/init.h> -+#include <linux/of.h> -+#include <linux/of_device.h> -+#include <linux/platform_device.h> -+#include <linux/reset-controller.h> -+ -+#include <dt-bindings/clock/bcm63268-clock.h> -+ -+#define BCM63268_TIMER_RESET_SLEEP_MIN_US 10000 -+#define BCM63268_TIMER_RESET_SLEEP_MAX_US 20000 -+ -+struct bcm63268_tclkrst_hw { -+ void __iomem *regs; -+ spinlock_t lock; -+ -+ struct reset_controller_dev rcdev; -+ struct clk_hw_onecell_data data; -+}; -+ -+struct bcm63268_tclk_table_entry { -+ const char * const name; -+ u8 bit; -+ unsigned long flags; -+}; -+ -+static const struct bcm63268_tclk_table_entry bcm63268_timer_clocks[] = { -+ { -+ .name = "ephy1", -+ .bit = BCM63268_TCLK_EPHY1, -+ }, { -+ .name = "ephy2", -+ .bit = BCM63268_TCLK_EPHY2, -+ }, { -+ .name = "ephy3", -+ .bit = BCM63268_TCLK_EPHY3, -+ }, { -+ .name = "gphy1", -+ .bit = BCM63268_TCLK_GPHY1, -+ }, { -+ .name = "dsl", -+ .bit = BCM63268_TCLK_DSL, -+ }, { -+ .name = "wakeon_ephy", -+ .bit = BCM63268_TCLK_WAKEON_EPHY, -+ }, { -+ .name = "wakeon_dsl", -+ .bit = BCM63268_TCLK_WAKEON_DSL, -+ }, { -+ .name = "fap1_pll", -+ .bit = BCM63268_TCLK_FAP1, -+ }, { -+ .name = "fap2_pll", -+ .bit = BCM63268_TCLK_FAP2, -+ }, { -+ .name = "uto_50", -+ .bit = BCM63268_TCLK_UTO_50, -+ }, { -+ .name = "uto_extin", -+ .bit = BCM63268_TCLK_UTO_EXTIN, -+ }, { -+ .name = "usb_ref", -+ .bit = BCM63268_TCLK_USB_REF, -+ }, { -+ /* sentinel */ -+ } -+}; -+ -+static inline struct bcm63268_tclkrst_hw * -+to_bcm63268_timer_reset(struct reset_controller_dev *rcdev) -+{ -+ return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev); -+} -+ -+static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev, -+ unsigned long id, bool assert) -+{ -+ struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev); -+ unsigned long flags; -+ uint32_t val; -+ -+ spin_lock_irqsave(&reset->lock, flags); -+ val = __raw_readl(reset->regs); -+ if (assert) -+ val &= ~BIT(id); -+ else -+ val |= BIT(id); -+ __raw_writel(val, reset->regs); -+ spin_unlock_irqrestore(&reset->lock, flags); -+ -+ return 0; -+} -+ -+static int bcm63268_timer_reset_assert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return bcm63268_timer_reset_update(rcdev, id, true); -+} -+ -+static int bcm63268_timer_reset_deassert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return bcm63268_timer_reset_update(rcdev, id, false); -+} -+ -+static int bcm63268_timer_reset_reset(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ bcm63268_timer_reset_update(rcdev, id, true); -+ usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US, -+ BCM63268_TIMER_RESET_SLEEP_MAX_US); -+ -+ bcm63268_timer_reset_update(rcdev, id, false); -+ /* -+ * Ensure component is taken out reset state by sleeping also after -+ * deasserting the reset. Otherwise, the component may not be ready -+ * for operation. -+ */ -+ usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US, -+ BCM63268_TIMER_RESET_SLEEP_MAX_US); -+ -+ return 0; -+} -+ -+static int bcm63268_timer_reset_status(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev); -+ -+ return !(__raw_readl(reset->regs) & BIT(id)); -+} -+ -+static struct reset_control_ops bcm63268_timer_reset_ops = { -+ .assert = bcm63268_timer_reset_assert, -+ .deassert = bcm63268_timer_reset_deassert, -+ .reset = bcm63268_timer_reset_reset, -+ .status = bcm63268_timer_reset_status, -+}; -+ -+static int bcm63268_tclk_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ const struct bcm63268_tclk_table_entry *entry, *table; -+ struct bcm63268_tclkrst_hw *hw; -+ u8 maxbit = 0; -+ int i, ret; -+ -+ table = of_device_get_match_data(dev); -+ if (!table) -+ return -EINVAL; -+ -+ for (entry = table; entry->name; entry++) -+ maxbit = max_t(u8, maxbit, entry->bit); -+ maxbit++; -+ -+ hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit), -+ GFP_KERNEL); -+ if (!hw) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, hw); -+ -+ spin_lock_init(&hw->lock); -+ -+ hw->data.num = maxbit; -+ for (i = 0; i < maxbit; i++) -+ hw->data.hws[i] = ERR_PTR(-ENODEV); -+ -+ hw->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(hw->regs)) -+ return PTR_ERR(hw->regs); -+ -+ for (entry = table; entry->name; entry++) { -+ struct clk_hw *clk; -+ -+ clk = clk_hw_register_gate(dev, entry->name, NULL, -+ entry->flags, hw->regs, entry->bit, -+ CLK_GATE_BIG_ENDIAN, &hw->lock); -+ if (IS_ERR(clk)) { -+ ret = PTR_ERR(clk); -+ goto out_err; -+ } -+ -+ hw->data.hws[entry->bit] = clk; -+ } -+ -+ ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, -+ &hw->data); -+ if (!ret) -+ return 0; -+ -+ hw->rcdev.of_node = dev->of_node; -+ hw->rcdev.ops = &bcm63268_timer_reset_ops; -+ -+ ret = devm_reset_controller_register(dev, &hw->rcdev); -+ if (ret) -+ dev_err(dev, "Failed to register reset controller\n"); -+ -+out_err: -+ for (i = 0; i < hw->data.num; i++) { -+ if (!IS_ERR(hw->data.hws[i])) -+ clk_hw_unregister_gate(hw->data.hws[i]); -+ } -+ -+ return ret; -+} -+ -+static const struct of_device_id bcm63268_tclk_dt_ids[] = { -+ { -+ .compatible = "brcm,bcm63268-timer-clocks", -+ .data = &bcm63268_timer_clocks, -+ }, { -+ /* sentinel */ -+ } -+}; -+ -+static struct platform_driver bcm63268_tclk = { -+ .probe = bcm63268_tclk_probe, -+ .driver = { -+ .name = "bcm63268-timer-clock", -+ .of_match_table = bcm63268_tclk_dt_ids, -+ }, -+}; -+builtin_platform_driver(bcm63268_tclk); diff --git a/target/linux/bmips/patches-5.10/200-mips-bmips-automatically-detect-CPU-frequency.patch b/target/linux/bmips/patches-5.10/200-mips-bmips-automatically-detect-CPU-frequency.patch deleted file mode 100644 index 2a3aac217f..0000000000 --- a/target/linux/bmips/patches-5.10/200-mips-bmips-automatically-detect-CPU-frequency.patch +++ /dev/null @@ -1,238 +0,0 @@ -From 0377ad93031d3e51c2afe44231241185f684b6af Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Fri, 5 Mar 2021 15:14:32 +0100 -Subject: [PATCH 1/2] mips: bmips: automatically detect CPU frequency -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Some BCM63xx SoCs support multiple CPU frequencies depending on HW config. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> ---- - arch/mips/bmips/setup.c | 198 ++++++++++++++++++++++++++++++++++++++-- - 1 file changed, 191 insertions(+), 7 deletions(-) - ---- a/arch/mips/bmips/setup.c -+++ b/arch/mips/bmips/setup.c -@@ -31,11 +31,51 @@ - - #define RELO_NORMAL_VEC BIT(18) - -+#define REG_BCM6318_SOB ((void __iomem *)CKSEG1ADDR(0x10000900)) -+#define BCM6318_FREQ_SHIFT 23 -+#define BCM6318_FREQ_MASK (0x3 << BCM6318_FREQ_SHIFT) -+ - #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) - #define BCM6328_TP1_DISABLED BIT(9) -+#define REG_BCM6328_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001a40)) -+#define BCM6328_FCVO_SHIFT 7 -+#define BCM6328_FCVO_MASK (0x1f << BCM6328_FCVO_SHIFT) -+ -+#define REG_BCM6358_DDR_PLLC ((void __iomem *)0xfffe12b8) -+#define BCM6358_PLLC_M1_SHIFT 0 -+#define BCM6358_PLLC_M1_MASK (0xff << BCM6358_PLLC_M1_SHIFT) -+#define BCM6358_PLLC_N1_SHIFT 23 -+#define BCM6358_PLLC_N1_MASK (0x3f << BCM6358_PLLC_N1_SHIFT) -+#define BCM6358_PLLC_N2_SHIFT 29 -+#define BCM6358_PLLC_N2_MASK (0x7 << BCM6358_PLLC_N2_SHIFT) -+ -+#define REG_BCM6362_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001814)) -+#define BCM6362_FCVO_SHIFT 1 -+#define BCM6362_FCVO_MASK (0x1f << BCM6362_FCVO_SHIFT) -+ -+#define REG_BCM6368_DDR_PLLC ((void __iomem *)CKSEG1ADDR(0x100012a0)) -+#define BCM6368_PLLC_P1_SHIFT 0 -+#define BCM6368_PLLC_P1_MASK (0xf << BCM6368_PLLC_P1_SHIFT) -+#define BCM6368_PLLC_P2_SHIFT 4 -+#define BCM6368_PLLC_P2_MASK (0xf << BCM6368_PLLC_P2_SHIFT) -+#define BCM6368_PLLC_NDIV_SHIFT 16 -+#define BCM6368_PLLC_NDIV_MASK (0x1ff << BCM6368_PLLC_NDIV_SHIFT) -+#define REG_BCM6368_DDR_PLLD ((void __iomem *)CKSEG1ADDR(0x100012a4)) -+#define BCM6368_PLLD_MDIV_SHIFT 0 -+#define BCM6368_PLLD_MDIV_MASK (0xff << BCM6368_PLLD_MDIV_SHIFT) -+ -+#define REG_BCM63268_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001814)) -+#define BCM63268_FCVO_SHIFT 21 -+#define BCM63268_FCVO_MASK (0xf << BCM63268_FCVO_SHIFT) -+ - - static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; - -+struct bmips_cpufreq { -+ const char *compatible; -+ u32 (*cpu_freq)(void); -+}; -+ - struct bmips_quirk { - const char *compatible; - void (*quirk_fn)(void); -@@ -138,17 +178,161 @@ const char *get_system_type(void) - return "Generic BMIPS kernel"; - } - -+static u32 bcm6318_cpufreq(void) -+{ -+ u32 val = __raw_readl(REG_BCM6318_SOB); -+ -+ switch ((val & BCM6318_FREQ_MASK) >> BCM6318_FREQ_SHIFT) { -+ case 0: -+ return 166000000; -+ case 2: -+ return 250000000; -+ case 3: -+ return 333000000; -+ case 1: -+ return 400000000; -+ default: -+ return 0; -+ } -+} -+ -+static u32 bcm6328_cpufreq(void) -+{ -+ u32 val = __raw_readl(REG_BCM6328_MISC_SB); -+ -+ switch ((val & BCM6328_FCVO_MASK) >> BCM6328_FCVO_SHIFT) { -+ case 0x12: -+ case 0x14: -+ case 0x19: -+ return 160000000; -+ case 0x1c: -+ return 192000000; -+ case 0x13: -+ case 0x15: -+ return 200000000; -+ case 0x1a: -+ return 384000000; -+ case 0x16: -+ return 400000000; -+ default: -+ return 320000000; -+ } -+} -+ -+static u32 bcm6358_cpufreq(void) -+{ -+ u32 val, n1, n2, m1; -+ -+ val = __raw_readl(REG_BCM6358_DDR_PLLC); -+ n1 = (val & BCM6358_PLLC_N1_MASK) >> BCM6358_PLLC_N1_SHIFT; -+ n2 = (val & BCM6358_PLLC_N2_MASK) >> BCM6358_PLLC_N2_SHIFT; -+ m1 = (val & BCM6358_PLLC_M1_MASK) >> BCM6358_PLLC_M1_SHIFT; -+ -+ return (16 * 1000000 * n1 * n2) / m1; -+} -+ -+static u32 bcm6362_cpufreq(void) -+{ -+ u32 val = __raw_readl(REG_BCM6362_MISC_SB); -+ -+ switch ((val & BCM6362_FCVO_MASK) >> BCM6362_FCVO_SHIFT) { -+ case 0x04: -+ case 0x0c: -+ case 0x14: -+ case 0x1c: -+ return 160000000; -+ case 0x15: -+ case 0x1d: -+ return 200000000; -+ case 0x03: -+ case 0x0b: -+ case 0x13: -+ case 0x1b: -+ return 240000000; -+ case 0x07: -+ case 0x17: -+ return 384000000; -+ case 0x05: -+ case 0x0e: -+ case 0x16: -+ case 0x1e: -+ case 0x1f: -+ return 400000000; -+ case 0x06: -+ return 440000000; -+ default: -+ return 320000000; -+ } -+} -+ -+static u32 bcm6368_cpufreq(void) -+{ -+ u32 val, p1, p2, ndiv, m1; -+ -+ val = __raw_readl(REG_BCM6368_DDR_PLLC); -+ p1 = (val & BCM6368_PLLC_P1_MASK) >> BCM6368_PLLC_P1_SHIFT; -+ p2 = (val & BCM6368_PLLC_P2_MASK) >> BCM6368_PLLC_P2_SHIFT; -+ ndiv = (val & BCM6368_PLLC_NDIV_MASK) >> -+ BCM6368_PLLC_NDIV_SHIFT; -+ -+ val = __raw_readl(REG_BCM6368_DDR_PLLD); -+ m1 = (val & BCM6368_PLLD_MDIV_MASK) >> BCM6368_PLLD_MDIV_SHIFT; -+ -+ return (((64 * 1000000) / p1) * p2 * ndiv) / m1; -+} -+ -+static u32 bcm63268_cpufreq(void) -+{ -+ u32 val = __raw_readl(REG_BCM63268_MISC_SB); -+ -+ switch ((val & BCM63268_FCVO_MASK) >> BCM63268_FCVO_SHIFT) { -+ case 0x3: -+ case 0xe: -+ return 320000000; -+ case 0xa: -+ return 333000000; -+ case 0x2: -+ case 0xb: -+ case 0xf: -+ return 400000000; -+ default: -+ return 0; -+ } -+} -+ -+static const struct bmips_cpufreq bmips_cpufreq_list[] = { -+ { "brcm,bcm6318", &bcm6318_cpufreq }, -+ { "brcm,bcm6328", &bcm6328_cpufreq }, -+ { "brcm,bcm6358", &bcm6358_cpufreq }, -+ { "brcm,bcm6362", &bcm6362_cpufreq }, -+ { "brcm,bcm6368", &bcm6368_cpufreq }, -+ { "brcm,bcm63268", &bcm63268_cpufreq }, -+ { /* sentinel */ } -+}; -+ - void __init plat_time_init(void) - { -+ const struct bmips_cpufreq *cf; - struct device_node *np; -- u32 freq; -+ u32 freq = 0; - -- np = of_find_node_by_name(NULL, "cpus"); -- if (!np) -- panic("missing 'cpus' DT node"); -- if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) -- panic("missing 'mips-hpt-frequency' property"); -- of_node_put(np); -+ for (cf = bmips_cpufreq_list; cf->cpu_freq; cf++) { -+ if (of_flat_dt_is_compatible(of_get_flat_dt_root(), -+ cf->compatible)) { -+ freq = cf->cpu_freq() / 2; -+ printk("%s detected @ %u MHz\n", cf->compatible, freq / 500000); -+ break; -+ } -+ } -+ -+ if (!freq) { -+ np = of_find_node_by_name(NULL, "cpus"); -+ if (!np) -+ panic("missing 'cpus' DT node"); -+ if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) -+ panic("missing 'mips-hpt-frequency' property"); -+ of_node_put(np); -+ } - - mips_hpt_frequency = freq; - } diff --git a/target/linux/bmips/patches-5.10/201-mips-bmips-automatically-detect-RAM-size.patch b/target/linux/bmips/patches-5.10/201-mips-bmips-automatically-detect-RAM-size.patch deleted file mode 100644 index 11459ad58f..0000000000 --- a/target/linux/bmips/patches-5.10/201-mips-bmips-automatically-detect-RAM-size.patch +++ /dev/null @@ -1,196 +0,0 @@ -From f9ee3f28ecb979c77423be965ef9dd313bdb9e9b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Mon, 8 Mar 2021 16:58:34 +0100 -Subject: [PATCH 2/2] mips: bmips: automatically detect RAM size -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Some devices have different amounts of RAM installed depending on HW revision. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> ---- - arch/mips/bmips/setup.c | 118 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 118 insertions(+) - ---- a/arch/mips/bmips/setup.c -+++ b/arch/mips/bmips/setup.c -@@ -19,6 +19,7 @@ - #include <linux/of_platform.h> - #include <linux/libfdt.h> - #include <linux/smp.h> -+#include <linux/types.h> - #include <asm/addrspace.h> - #include <asm/bmips.h> - #include <asm/bootinfo.h> -@@ -34,13 +35,16 @@ - #define REG_BCM6318_SOB ((void __iomem *)CKSEG1ADDR(0x10000900)) - #define BCM6318_FREQ_SHIFT 23 - #define BCM6318_FREQ_MASK (0x3 << BCM6318_FREQ_SHIFT) -+#define BCM6318_SDRAM_ADDR ((void __iomem *)CKSEG1ADDR(0x10004000)) - - #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) - #define BCM6328_TP1_DISABLED BIT(9) - #define REG_BCM6328_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001a40)) - #define BCM6328_FCVO_SHIFT 7 - #define BCM6328_FCVO_MASK (0x1f << BCM6328_FCVO_SHIFT) -+#define BCM6328_MEMC_ADDR ((void __iomem *)CKSEG1ADDR(0x10003000)) - -+#define BCM6358_MEMC_ADDR ((void __iomem *)0xfffe1200) - #define REG_BCM6358_DDR_PLLC ((void __iomem *)0xfffe12b8) - #define BCM6358_PLLC_M1_SHIFT 0 - #define BCM6358_PLLC_M1_MASK (0xff << BCM6358_PLLC_M1_SHIFT) -@@ -52,7 +56,9 @@ - #define REG_BCM6362_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001814)) - #define BCM6362_FCVO_SHIFT 1 - #define BCM6362_FCVO_MASK (0x1f << BCM6362_FCVO_SHIFT) -+#define BCM6362_MEMC_ADDR ((void __iomem *)CKSEG1ADDR(0x10003000)) - -+#define BCM6368_MEMC_ADDR ((void __iomem *)CKSEG1ADDR(0x10001200)) - #define REG_BCM6368_DDR_PLLC ((void __iomem *)CKSEG1ADDR(0x100012a0)) - #define BCM6368_PLLC_P1_SHIFT 0 - #define BCM6368_PLLC_P1_MASK (0xf << BCM6368_PLLC_P1_SHIFT) -@@ -67,7 +73,21 @@ - #define REG_BCM63268_MISC_SB ((void __iomem *)CKSEG1ADDR(0x10001814)) - #define BCM63268_FCVO_SHIFT 21 - #define BCM63268_FCVO_MASK (0xf << BCM63268_FCVO_SHIFT) -+#define BCM63268_MEMC_ADDR ((void __iomem *)CKSEG1ADDR(0x10003000)) - -+#define SDRAM_CFG_REG 0x0 -+#define SDRAM_SPACE_SHIFT 4 -+#define SDRAM_SPACE_MASK (0xf << SDRAM_SPACE_SHIFT) -+ -+#define MEMC_CFG_REG 0x4 -+#define MEMC_CFG_32B_SHIFT 1 -+#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) -+#define MEMC_CFG_COL_SHIFT 3 -+#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) -+#define MEMC_CFG_ROW_SHIFT 6 -+#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) -+ -+#define DDR_CSEND_REG 0x8 - - static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; - -@@ -76,6 +96,11 @@ struct bmips_cpufreq { - u32 (*cpu_freq)(void); - }; - -+struct bmips_memsize { -+ const char *compatible; -+ phys_addr_t (*mem_size)(void); -+}; -+ - struct bmips_quirk { - const char *compatible; - void (*quirk_fn)(void); -@@ -337,9 +362,90 @@ void __init plat_time_init(void) - mips_hpt_frequency = freq; - } - -+static inline phys_addr_t bmips_dram_size(unsigned int cols, -+ unsigned int rows, -+ unsigned int is_32b, -+ unsigned int banks) -+{ -+ rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */ -+ cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */ -+ is_32b += 1; -+ -+ return 1 << (cols + rows + is_32b + banks); -+} -+ -+static phys_addr_t _bcm6318_memsize(void __iomem *addr) -+{ -+ u32 val; -+ -+ val = __raw_readl(addr + SDRAM_CFG_REG); -+ val = (val & SDRAM_SPACE_MASK) >> SDRAM_SPACE_SHIFT; -+ -+ return (1 << (val + 20)); -+} -+ -+static phys_addr_t _bcm6328_memsize(void __iomem *addr) -+{ -+ return __raw_readl(addr + DDR_CSEND_REG) << 24; -+} -+ -+static phys_addr_t _bcm6358_memsize(void __iomem *addr) -+{ -+ unsigned int cols, rows, is_32b; -+ u32 val; -+ -+ val = __raw_readl(addr + MEMC_CFG_REG); -+ rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; -+ cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; -+ is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1; -+ -+ return bmips_dram_size(cols, rows, is_32b, 2); -+} -+ -+static phys_addr_t bcm6318_memsize(void) -+{ -+ return _bcm6318_memsize(BCM6318_SDRAM_ADDR); -+} -+ -+static phys_addr_t bcm6328_memsize(void) -+{ -+ return _bcm6328_memsize(BCM6328_MEMC_ADDR); -+} -+ -+static phys_addr_t bcm6358_memsize(void) -+{ -+ return _bcm6358_memsize(BCM6358_MEMC_ADDR); -+} -+ -+static phys_addr_t bcm6362_memsize(void) -+{ -+ return _bcm6328_memsize(BCM6362_MEMC_ADDR); -+} -+ -+static phys_addr_t bcm6368_memsize(void) -+{ -+ return _bcm6358_memsize(BCM6368_MEMC_ADDR); -+} -+ -+static phys_addr_t bcm63268_memsize(void) -+{ -+ return _bcm6328_memsize(BCM63268_MEMC_ADDR); -+} -+ -+static const struct bmips_memsize bmips_memsize_list[] = { -+ { "brcm,bcm6318", &bcm6318_memsize }, -+ { "brcm,bcm6328", &bcm6328_memsize }, -+ { "brcm,bcm6358", &bcm6358_memsize }, -+ { "brcm,bcm6362", &bcm6362_memsize }, -+ { "brcm,bcm6368", &bcm6368_memsize }, -+ { "brcm,bcm63268", &bcm63268_memsize }, -+ { /* sentinel */ } -+}; -+ - void __init plat_mem_setup(void) - { - void *dtb; -+ const struct bmips_memsize *ms; - const struct bmips_quirk *q; - - set_io_port_base(0); -@@ -358,6 +464,18 @@ void __init plat_mem_setup(void) - - __dt_setup_arch(dtb); - -+ for (ms = bmips_memsize_list; ms->mem_size; ms++) { -+ if (of_flat_dt_is_compatible(of_get_flat_dt_root(), -+ ms->compatible)) { -+ phys_addr_t mem = ms->mem_size(); -+ if (mem) { -+ memblock_add(0, mem); -+ printk("%uMB of RAM installed\n", mem >> 20); -+ break; -+ } -+ } -+ } -+ - for (q = bmips_quirk_list; q->quirk_fn; q++) { - if (of_flat_dt_is_compatible(of_get_flat_dt_root(), - q->compatible)) { diff --git a/target/linux/bmips/patches-5.10/202-mips-bmips-disable-ARCH_HAS_SYNC_DMA_FOR_CPU_ALL.patch b/target/linux/bmips/patches-5.10/202-mips-bmips-disable-ARCH_HAS_SYNC_DMA_FOR_CPU_ALL.patch deleted file mode 100644 index ba7cf5c6c4..0000000000 --- a/target/linux/bmips/patches-5.10/202-mips-bmips-disable-ARCH_HAS_SYNC_DMA_FOR_CPU_ALL.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 84c06b4a1dfa3e021fdbcafaff8cebfdec462402 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Tue, 23 Feb 2021 10:39:48 +0100 -Subject: [PATCH] mips: bmips: disable ARCH_HAS_SYNC_DMA_FOR_CPU_ALL -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enabling this option causes kernel panics on BCM6358 with EHCI/OHCI: -[ 3.881739] usb 1-1: new high-speed USB device number 2 using ehci-platform -[ 3.895011] Reserved instruction in kernel code[#1]: -[ 3.900113] CPU: 0 PID: 1 Comm: init Not tainted 5.10.16 #0 -[ 3.905829] $ 0 : 00000000 10008700 00000000 77d94060 -[ 3.911238] $ 4 : 7fd1f088 00000000 81431cac 81431ca0 -[ 3.916641] $ 8 : 00000000 ffffefff 8075cd34 00000000 -[ 3.922043] $12 : 806f8d40 f3e812b7 00000000 000d9aaa -[ 3.927446] $16 : 7fd1f068 7fd1f080 7ff559b8 81428470 -[ 3.932848] $20 : 00000000 00000000 55590000 77d70000 -[ 3.938251] $24 : 00000018 00000010 -[ 3.943655] $28 : 81430000 81431e60 81431f28 800157fc -[ 3.949058] Hi : 00000000 -[ 3.952013] Lo : 00000000 -[ 3.955019] epc : 80015808 setup_sigcontext+0x54/0x24c -[ 3.960464] ra : 800157fc setup_sigcontext+0x48/0x24c -[ 3.965913] Status: 10008703 KERNEL EXL IE -[ 3.970216] Cause : 00800028 (ExcCode 0a) -[ 3.974340] PrId : 0002a010 (Broadcom BMIPS4350) -[ 3.979170] Modules linked in: ohci_platform ohci_hcd fsl_mph_dr_of ehci_platform ehci_fsl ehci_hcd gpio_button_hotplug usbcore nls_base usb_common -[ 3.992907] Process init (pid: 1, threadinfo=(ptrval), task=(ptrval), tls=77e22ec8) -[ 4.000776] Stack : 81431ef4 7fd1f080 81431f28 81428470 7fd1f068 81431edc 7ff559b8 81428470 -[ 4.009467] 81431f28 7fd1f080 55590000 77d70000 77d5498c 80015c70 806f0000 8063ae74 -[ 4.018149] 08100002 81431f28 0000000a 08100002 81431f28 0000000a 77d6b418 00000003 -[ 4.026831] ffffffff 80016414 80080734 81431ecc 81431ecc 00000001 00000000 04000000 -[ 4.035512] 77d54874 00000000 00000000 00000000 00000000 00000012 00000002 00000000 -[ 4.044196] ... -[ 4.046706] Call Trace: -[ 4.049238] [<80015808>] setup_sigcontext+0x54/0x24c -[ 4.054356] [<80015c70>] setup_frame+0xdc/0x124 -[ 4.059015] [<80016414>] do_notify_resume+0x1dc/0x288 -[ 4.064207] [<80011b50>] work_notifysig+0x10/0x18 -[ 4.069036] -[ 4.070538] Code: 8fc300b4 00001025 26240008 <ac820000> ac830004 3c048063 0c0228aa 24846a00 26240010 -[ 4.080686] -[ 4.082517] ---[ end trace 22a8edb41f5f983b ]--- -[ 4.087374] Kernel panic - not syncing: Fatal exception -[ 4.092753] Rebooting in 1 seconds.. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> ---- - arch/mips/Kconfig | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -253,7 +253,6 @@ config ATH79 - config BMIPS_GENERIC - bool "Broadcom Generic BMIPS kernel" - select ARCH_HAS_RESET_CONTROLLER -- select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL - select ARCH_HAS_PHYS_TO_DMA - select BOOT_RAW - select NO_EXCEPT_FILL diff --git a/target/linux/bmips/patches-5.10/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch b/target/linux/bmips/patches-5.10/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch deleted file mode 100644 index c2c2e968e9..0000000000 --- a/target/linux/bmips/patches-5.10/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 590b60fb08cb1e70fe02d3f407c6b3dbe9ad06ff Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Mon, 1 Mar 2021 07:34:39 +0100 -Subject: [PATCH 3/4] net: broadcom: add BCM6368 enetsw controller driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This controller is present on BCM6318, BCM6328, BCM6362, BCM6368 and BCM63268 -SoCs. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> ---- - drivers/net/ethernet/broadcom/Kconfig | 8 + - drivers/net/ethernet/broadcom/Makefile | 1 + - .../net/ethernet/broadcom/bcm6368-enetsw.c | 1111 +++++++++++++++++ - 3 files changed, 1120 insertions(+) - create mode 100644 drivers/net/ethernet/broadcom/bcm6368-enetsw.c - ---- a/drivers/net/ethernet/broadcom/Kconfig -+++ b/drivers/net/ethernet/broadcom/Kconfig -@@ -60,6 +60,14 @@ config BCM63XX_ENET - This driver supports the ethernet MACs in the Broadcom 63xx - MIPS chipset family (BCM63XX). - -+config BCM6368_ENETSW -+ tristate "Broadcom BCM6368 internal mac support" -+ depends on BMIPS_GENERIC || COMPILE_TEST -+ default y -+ help -+ This driver supports Ethernet controller integrated into Broadcom -+ BCM6368 family SoCs. -+ - config BCMGENET - tristate "Broadcom GENET internal MAC support" - depends on HAS_IOMEM ---- a/drivers/net/ethernet/broadcom/Makefile -+++ b/drivers/net/ethernet/broadcom/Makefile -@@ -5,6 +5,7 @@ - - obj-$(CONFIG_B44) += b44.o - obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o -+obj-$(CONFIG_BCM6368_ENETSW) += bcm6368-enetsw.o - obj-$(CONFIG_BCMGENET) += genet/ - obj-$(CONFIG_BNX2) += bnx2.o - obj-$(CONFIG_CNIC) += cnic.o diff --git a/target/linux/bmips/patches-5.10/510-net-dsa-b53-add-support-for-BCM63xx-RGMIIs.patch b/target/linux/bmips/patches-5.10/510-net-dsa-b53-add-support-for-BCM63xx-RGMIIs.patch deleted file mode 100644 index c636e3a907..0000000000 --- a/target/linux/bmips/patches-5.10/510-net-dsa-b53-add-support-for-BCM63xx-RGMIIs.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 32cf73d8c6485b7b97aca7e377a68436d09b7022 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Sun, 14 Mar 2021 20:03:44 +0100 -Subject: [PATCH] net: dsa: b53: add support for BCM63xx RGMIIs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> ---- - drivers/net/dsa/b53/b53_common.c | 37 ++++++++++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -1174,6 +1174,36 @@ static void b53_force_port_config(struct - b53_write8(dev, B53_CTRL_PAGE, off, reg); - } - -+static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port, -+ phy_interface_t interface) -+{ -+ struct b53_device *dev = ds->priv; -+ u8 rgmii_ctrl = 0, off; -+ -+ if (port == 8) -+ off = B53_RGMII_CTRL_IMP; -+ else -+ off = B53_RGMII_CTRL_P(port); -+ -+ b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl); -+ -+ rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); -+ if (interface == PHY_INTERFACE_MODE_RGMII_ID) -+ rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC); -+ else if (interface == PHY_INTERFACE_MODE_RGMII_RXID) -+ rgmii_ctrl |= RGMII_CTRL_DLL_RXC; -+ else if (interface == PHY_INTERFACE_MODE_RGMII_TXID) -+ rgmii_ctrl |= RGMII_CTRL_DLL_TXC; -+ -+ if (port != B53_CPU_PORT) -+ rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII; -+ -+ b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl); -+ -+ dev_info(ds->dev, "Configured port %d for %s\n", port, -+ phy_modes(interface)); -+} -+ - static void b53_adjust_link(struct dsa_switch *ds, int port, - struct phy_device *phydev) - { -@@ -1200,6 +1230,9 @@ static void b53_adjust_link(struct dsa_s - tx_pause, rx_pause); - b53_force_link(dev, port, phydev->link); - -+ if (is63xx(dev)) -+ b53_adjust_63xx_rgmii(ds, port, phydev->interface); -+ - if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { - if (port == dev->imp_port) - off = B53_RGMII_CTRL_IMP; -@@ -1386,6 +1419,9 @@ void b53_phylink_mac_link_up(struct dsa_ - { - struct b53_device *dev = ds->priv; - -+ if (is63xx(dev) && port >= 4) -+ b53_adjust_63xx_rgmii(ds, port, interface); -+ - if (mode == MLO_AN_PHY) - return; - diff --git a/target/linux/bmips/patches-5.10/600-mips-bmips-add-pci-support.patch b/target/linux/bmips/patches-5.10/600-mips-bmips-add-pci-support.patch deleted file mode 100644 index f74a14f256..0000000000 --- a/target/linux/bmips/patches-5.10/600-mips-bmips-add-pci-support.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -265,6 +265,7 @@ config BMIPS_GENERIC - select BCM7038_L1_IRQ - select BCM7120_L2_IRQ - select BRCMSTB_L2_IRQ -+ select HAVE_PCI - select IRQ_MIPS_CPU - select DMA_NONCOHERENT - select SYS_SUPPORTS_32BIT_KERNEL ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -28,6 +28,7 @@ obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xt - # These are still pretty much in the old state, watch, go blind. - # - obj-$(CONFIG_ATH79) += fixup-ath79.o -+obj-$(CONFIG_BMIPS_GENERIC) += fixup-bmips.o - obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o - obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o - obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o diff --git a/target/linux/bmips/patches-5.10/601-pci-controllers-add-bcm6328-pcie-support.patch b/target/linux/bmips/patches-5.10/601-pci-controllers-add-bcm6328-pcie-support.patch deleted file mode 100644 index d7e2fe113e..0000000000 --- a/target/linux/bmips/patches-5.10/601-pci-controllers-add-bcm6328-pcie-support.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/drivers/pci/controller/Kconfig -+++ b/drivers/pci/controller/Kconfig -@@ -3,6 +3,11 @@ - menu "PCI controller drivers" - depends on PCI - -+config PCIE_BCM6328 -+ bool "BCM6328 PCIe controller" -+ depends on BMIPS_GENERIC || COMPILE_TEST -+ depends on OF -+ - config PCI_MVEBU - bool "Marvell EBU PCIe controller" - depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST ---- a/drivers/pci/controller/Makefile -+++ b/drivers/pci/controller/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_PCIE_BCM6328) += pcie-bcm6328.o - obj-$(CONFIG_PCIE_CADENCE) += cadence/ - obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o - obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o diff --git a/target/linux/bmips/patches-5.10/602-pci-controllers-add-bcm6318-pcie-support.patch b/target/linux/bmips/patches-5.10/602-pci-controllers-add-bcm6318-pcie-support.patch deleted file mode 100644 index 3674028aec..0000000000 --- a/target/linux/bmips/patches-5.10/602-pci-controllers-add-bcm6318-pcie-support.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/drivers/pci/controller/Kconfig -+++ b/drivers/pci/controller/Kconfig -@@ -3,6 +3,11 @@ - menu "PCI controller drivers" - depends on PCI - -+config PCIE_BCM6318 -+ bool "BCM6318 PCIe controller" -+ depends on BMIPS_GENERIC || COMPILE_TEST -+ depends on OF -+ - config PCIE_BCM6328 - bool "BCM6328 PCIe controller" - depends on BMIPS_GENERIC || COMPILE_TEST ---- a/drivers/pci/controller/Makefile -+++ b/drivers/pci/controller/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_PCIE_BCM6318) += pcie-bcm6318.o - obj-$(CONFIG_PCIE_BCM6328) += pcie-bcm6328.o - obj-$(CONFIG_PCIE_CADENCE) += cadence/ - obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o diff --git a/target/linux/bmips/patches-5.10/603-pci-controllers-add-bcm6348-pci-support.patch b/target/linux/bmips/patches-5.10/603-pci-controllers-add-bcm6348-pci-support.patch deleted file mode 100644 index c0572604ee..0000000000 --- a/target/linux/bmips/patches-5.10/603-pci-controllers-add-bcm6348-pci-support.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/drivers/pci/controller/Kconfig -+++ b/drivers/pci/controller/Kconfig -@@ -3,6 +3,11 @@ - menu "PCI controller drivers" - depends on PCI - -+config PCI_BCM6348 -+ bool "BCM6348 PCI controller" -+ depends on BMIPS_GENERIC || COMPILE_TEST -+ depends on OF -+ - config PCIE_BCM6318 - bool "BCM6318 PCIe controller" - depends on BMIPS_GENERIC || COMPILE_TEST ---- a/drivers/pci/controller/Makefile -+++ b/drivers/pci/controller/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_PCI_BCM6348) += pci-bcm6348.o - obj-$(CONFIG_PCIE_BCM6318) += pcie-bcm6318.o - obj-$(CONFIG_PCIE_BCM6328) += pcie-bcm6328.o - obj-$(CONFIG_PCIE_CADENCE) += cadence/ diff --git a/target/linux/bmips/patches-5.10/610-mips-bmips-add-pci-fixups.patch b/target/linux/bmips/patches-5.10/610-mips-bmips-add-pci-fixups.patch deleted file mode 100644 index 5f68308986..0000000000 --- a/target/linux/bmips/patches-5.10/610-mips-bmips-add-pci-fixups.patch +++ /dev/null @@ -1,6 +0,0 @@ ---- a/arch/mips/bmips/Makefile -+++ b/arch/mips/bmips/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-y += setup.o irq.o dma.o -+obj-y += ath9k-fixup.o b43-sprom.o diff --git a/target/linux/bmips/patches-5.10/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch b/target/linux/bmips/patches-5.10/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch deleted file mode 100644 index d98d27c6b4..0000000000 --- a/target/linux/bmips/patches-5.10/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch +++ /dev/null @@ -1,26 +0,0 @@ -From ff3409ab17d56450943364ba49a16960e3cdda9b Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Sun, 6 Apr 2014 22:33:16 +0200 -Subject: [RFC] jffs2: work around unaligned accesses failing on bcm63xx/smp - -Unligned memcpy_fromio randomly fails with an unaligned dst. Work around -it by ensuring we are always doing aligned copies. - -Should fix filename corruption in jffs2 with SMP. - -Signed-off-by: Jonas Gorski <jogo@openwrt.org> ---- - fs/jffs2/nodelist.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/fs/jffs2/nodelist.h -+++ b/fs/jffs2/nodelist.h -@@ -259,7 +259,7 @@ struct jffs2_full_dirent - uint32_t ino; /* == zero for unlink */ - unsigned int nhash; - unsigned char type; -- unsigned char name[]; -+ unsigned char name[] __attribute__((aligned((sizeof(long))))); - }; - - /* |