bmips: rewrite pin controllers

This is needed in order to upstream them.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

1 files changed, 220 insertions, 0 deletions

diff --git a/target/linux/bmips/patches-5.10/408-Documentation-add-BCM63268-pincontroller-binding-doc.patch b/target/linux/bmips/patches-5.10/408-Documentation-add-BCM63268-pincontroller-binding-doc.patch
new file mode 100644
index 0000000000..d51af84328
--- /dev/null
+++ b/target/linux/bmips/patches-5.10/408-Documentation-add-BCM63268-pincontroller-binding-doc.patch
@@ -0,0 +1,220 @@
+From 826266914f8397c996d2d4d821b315d614bfc325 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
+Date: Wed, 27 Jul 2016 11:37:08 +0200
+Subject: [PATCH 09/12] Documentation: add BCM63268 pincontroller binding
+ documentation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add binding documentation for the pincontrol core found in the BCM63268
+family SoCs.
+
+Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ .../pinctrl/brcm,bcm63268-pinctrl.yaml        | 198 ++++++++++++++++++
+ 1 file changed, 198 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml
+@@ -0,0 +1,198 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Broadcom BCM63268 pin controller
++
++maintainers:
++  - Álvaro Fernández Rojas <noltari@gmail.com>
++  - Jonas Gorski <jonas.gorski@gmail.com>
++
++description: |+
++  The pin controller node should be the child of a syscon node.
++
++  Refer to the the bindings described in
++  Documentation/devicetree/bindings/mfd/syscon.yaml
++
++properties:
++  compatible:
++    const: brcm,bcm63268-pinctrl
++
++  gpio-controller: true
++
++  '#gpio-cells':
++    description:
++      Specifies the pin number and flags, as defined in
++      include/dt-bindings/gpio/gpio.h
++    const: 2
++
++  interrupts-extended:
++    description:
++      One interrupt per each of the 4 GPIO ports supported by the controller,
++      sorted by port number ascending order.
++    minItems: 4
++    maxItems: 4
++
++patternProperties:
++  '^.*$':
++    if:
++      type: object
++    then:
++      properties:
++        function:
++          $ref: "/schemas/types.yaml#/definitions/string"
++          enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5,
++                  hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi,
++                  vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data,
++                  nand, gpio35_alt, dectpd, vdsl_phy_override_0,
++                  vdsl_phy_override_1, vdsl_phy_override_2,
++                  vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ]
++
++        pins:
++          $ref: "/schemas/types.yaml#/definitions/string"
++          enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19,
++                  gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35
++                  dectpd_grp, vdsl_phy_override_0_grp,
++                  vdsl_phy_override_1_grp, vdsl_phy_override_2_grp,
++                  vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ]
++
++required:
++  - compatible
++  - gpio-controller
++  - '#gpio-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    gpio@100000c0 {
++      compatible = "syscon", "simple-mfd";
++      reg = <0x100000c0 0x80>;
++
++      pinctrl: pinctrl {
++        compatible = "brcm,bcm63268-pinctrl";
++
++        gpio-controller;
++        #gpio-cells = <2>;
++
++        interrupts-extended = <&ext_intc 0 0>,
++                              <&ext_intc 1 0>,
++                              <&ext_intc 2 0>,
++                              <&ext_intc 3 0>;
++        interrupt-names = "gpio32",
++                          "gpio33",
++                          "gpio34",
++                          "gpio35";
++
++        pinctrl_serial_led: serial_led {
++          pinctrl_serial_led_clk: serial_led_clk {
++            function = "serial_led_clk";
++            pins = "gpio0";
++          };
++
++          pinctrl_serial_led_data: serial_led_data {
++            function = "serial_led_data";
++            pins = "gpio1";
++          };
++        };
++
++        pinctrl_hsspi_cs4: hsspi_cs4 {
++          function = "hsspi_cs4";
++          pins = "gpio16";
++        };
++
++        pinctrl_hsspi_cs5: hsspi_cs5 {
++          function = "hsspi_cs5";
++          pins = "gpio17";
++        };
++
++        pinctrl_hsspi_cs6: hsspi_cs6 {
++          function = "hsspi_cs6";
++          pins = "gpio8";
++        };
++
++        pinctrl_hsspi_cs7: hsspi_cs7 {
++          function = "hsspi_cs7";
++          pins = "gpio9";
++        };
++
++        pinctrl_adsl_spi: adsl_spi {
++          pinctrl_adsl_spi_miso: adsl_spi_miso {
++            function = "adsl_spi_miso";
++            pins = "gpio18";
++          };
++
++          pinctrl_adsl_spi_mosi: adsl_spi_mosi {
++            function = "adsl_spi_mosi";
++            pins = "gpio19";
++          };
++        };
++
++        pinctrl_vreq_clk: vreq_clk {
++          function = "vreq_clk";
++          pins = "gpio22";
++        };
++
++        pinctrl_pcie_clkreq_b: pcie_clkreq_b {
++          function = "pcie_clkreq_b";
++          pins = "gpio23";
++        };
++
++        pinctrl_robosw_led_clk: robosw_led_clk {
++          function = "robosw_led_clk";
++          pins = "gpio30";
++        };
++
++        pinctrl_robosw_led_data: robosw_led_data {
++          function = "robosw_led_data";
++          pins = "gpio31";
++        };
++
++        pinctrl_nand: nand {
++          function = "nand";
++          group = "nand_grp";
++        };
++
++        pinctrl_gpio35_alt: gpio35_alt {
++          function = "gpio35_alt";
++          pin = "gpio35";
++        };
++
++        pinctrl_dectpd: dectpd {
++          function = "dectpd";
++          group = "dectpd_grp";
++        };
++
++        pinctrl_vdsl_phy_override_0: vdsl_phy_override_0 {
++          function = "vdsl_phy_override_0";
++          group = "vdsl_phy_override_0_grp";
++        };
++
++        pinctrl_vdsl_phy_override_1: vdsl_phy_override_1 {
++          function = "vdsl_phy_override_1";
++          group = "vdsl_phy_override_1_grp";
++        };
++
++        pinctrl_vdsl_phy_override_2: vdsl_phy_override_2 {
++          function = "vdsl_phy_override_2";
++          group = "vdsl_phy_override_2_grp";
++        };
++
++        pinctrl_vdsl_phy_override_3: vdsl_phy_override_3 {
++          function = "vdsl_phy_override_3";
++          group = "vdsl_phy_override_3_grp";
++        };
++
++        pinctrl_dsl_gpio8: dsl_gpio8 {
++          function = "dsl_gpio8";
++          group = "dsl_gpio8";
++        };
++
++        pinctrl_dsl_gpio9: dsl_gpio9 {
++          function = "dsl_gpio9";
++          group = "dsl_gpio9";
++        };
++      };
++    };