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| author | Daniel González Cabanelas <dgcbueu@gmail.com> | 2020-06-07 10:55:46 +0200 |
|---|---|---|
| committer | Álvaro Fernández Rojas <noltari@gmail.com> | 2020-06-07 20:26:17 +0200 |
| commit | 598ba5b169acbd92c95ebbb2584b9ecb482e900f (patch) | |
| tree | 2243f9db2837b13f64e6200c50a72ad608a25e81 /target/linux/bcm63xx/patches-5.4/431-MIPS-BCM63XX-add-nand-rset.patch | |
| parent | 66f70621608d7f7855607a0436a064e20a34d09c (diff) | |
| download | upstream-598ba5b169acbd92c95ebbb2584b9ecb482e900f.tar.gz upstream-598ba5b169acbd92c95ebbb2584b9ecb482e900f.tar.bz2 upstream-598ba5b169acbd92c95ebbb2584b9ecb482e900f.zip | |
bcm63xx: kernel: add BCM63167 cpuid variant
The BCM63167 is a BCM63268 SoC with a different physical packaging.
Add the CPU ID to allow supporting routers with this SoC (i.e Sercomm
H500-s)
Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
Diffstat (limited to 'target/linux/bcm63xx/patches-5.4/431-MIPS-BCM63XX-add-nand-rset.patch')
| -rw-r--r-- | target/linux/bcm63xx/patches-5.4/431-MIPS-BCM63XX-add-nand-rset.patch | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/target/linux/bcm63xx/patches-5.4/431-MIPS-BCM63XX-add-nand-rset.patch b/target/linux/bcm63xx/patches-5.4/431-MIPS-BCM63XX-add-nand-rset.patch index 1172b23197..090ffeb43c 100644 --- a/target/linux/bcm63xx/patches-5.4/431-MIPS-BCM63XX-add-nand-rset.patch +++ b/target/linux/bcm63xx/patches-5.4/431-MIPS-BCM63XX-add-nand-rset.patch @@ -1,6 +1,6 @@ --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h -@@ -181,7 +181,8 @@ enum bcm63xx_regs_set { +@@ -184,7 +184,8 @@ enum bcm63xx_regs_set { RSET_PCMDMAC, RSET_PCMDMAS, RSET_RNG, @@ -10,7 +10,7 @@ }; #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) -@@ -259,6 +260,7 @@ enum bcm63xx_regs_set { +@@ -262,6 +263,7 @@ enum bcm63xx_regs_set { #define BCM_3368_PCMDMAS_BASE (0xdeadbeef) #define BCM_3368_RNG_BASE (0xdeadbeef) #define BCM_3368_MISC_BASE (0xdeadbeef) @@ -18,7 +18,7 @@ /* * 6318 register sets base address -@@ -306,6 +308,7 @@ enum bcm63xx_regs_set { +@@ -309,6 +311,7 @@ enum bcm63xx_regs_set { #define BCM_6318_PCMDMAS_BASE (0xdeadbeef) #define BCM_6318_RNG_BASE (0xdeadbeef) #define BCM_6318_MISC_BASE (0xb0000280) @@ -26,7 +26,7 @@ #define BCM_6318_OTP_BASE (0xdeadbeef) #define BCM_6318_STRAP_BASE (0xb0000900) -@@ -356,6 +359,7 @@ enum bcm63xx_regs_set { +@@ -359,6 +362,7 @@ enum bcm63xx_regs_set { #define BCM_6328_PCMDMAS_BASE (0xdeadbeef) #define BCM_6328_RNG_BASE (0xdeadbeef) #define BCM_6328_MISC_BASE (0xb0001800) @@ -34,7 +34,7 @@ #define BCM_6328_OTP_BASE (0xb0000600) /* -@@ -405,6 +409,7 @@ enum bcm63xx_regs_set { +@@ -408,6 +412,7 @@ enum bcm63xx_regs_set { #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) #define BCM_6338_RNG_BASE (0xdeadbeef) #define BCM_6338_MISC_BASE (0xdeadbeef) @@ -42,7 +42,7 @@ /* * 6345 register sets base address -@@ -453,6 +458,7 @@ enum bcm63xx_regs_set { +@@ -456,6 +461,7 @@ enum bcm63xx_regs_set { #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) #define BCM_6345_RNG_BASE (0xdeadbeef) #define BCM_6345_MISC_BASE (0xdeadbeef) @@ -50,7 +50,7 @@ /* * 6348 register sets base address -@@ -499,6 +505,7 @@ enum bcm63xx_regs_set { +@@ -502,6 +508,7 @@ enum bcm63xx_regs_set { #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) #define BCM_6348_RNG_BASE (0xdeadbeef) #define BCM_6348_MISC_BASE (0xdeadbeef) @@ -58,7 +58,7 @@ /* * 6358 register sets base address -@@ -545,7 +552,7 @@ enum bcm63xx_regs_set { +@@ -548,7 +555,7 @@ enum bcm63xx_regs_set { #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) #define BCM_6358_RNG_BASE (0xdeadbeef) #define BCM_6358_MISC_BASE (0xdeadbeef) @@ -67,7 +67,7 @@ /* * 6362 register sets base address -@@ -593,6 +600,7 @@ enum bcm63xx_regs_set { +@@ -596,6 +603,7 @@ enum bcm63xx_regs_set { #define BCM_6362_PCMDMAS_BASE (0xdeadbeef) #define BCM_6362_RNG_BASE (0xdeadbeef) #define BCM_6362_MISC_BASE (0xb0001800) @@ -75,7 +75,7 @@ #define BCM_6362_NAND_REG_BASE (0xb0000200) #define BCM_6362_NAND_CACHE_BASE (0xb0000600) -@@ -648,6 +656,7 @@ enum bcm63xx_regs_set { +@@ -651,6 +659,7 @@ enum bcm63xx_regs_set { #define BCM_6368_PCMDMAS_BASE (0xb0005c00) #define BCM_6368_RNG_BASE (0xb0004180) #define BCM_6368_MISC_BASE (0xdeadbeef) @@ -83,7 +83,7 @@ /* * 63268 register sets base address -@@ -695,6 +704,7 @@ enum bcm63xx_regs_set { +@@ -698,6 +707,7 @@ enum bcm63xx_regs_set { #define BCM_63268_PCMDMAS_BASE (0xdeadbeef) #define BCM_63268_RNG_BASE (0xdeadbeef) #define BCM_63268_MISC_BASE (0xb0001800) @@ -91,7 +91,7 @@ extern const unsigned long *bcm63xx_regs_base; -@@ -740,6 +750,7 @@ extern const unsigned long *bcm63xx_regs +@@ -743,6 +753,7 @@ extern const unsigned long *bcm63xx_regs [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \ |