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author | Daniel Golle <daniel@makrotopia.org> | 2022-03-21 01:16:48 +0000 |
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committer | Daniel Golle <daniel@makrotopia.org> | 2022-03-21 13:11:56 +0000 |
commit | 786bf7fdaca4c75e7eba6e9aa3a8b5775fd21186 (patch) | |
tree | 926fecb2b1f6ce1e42ba7ef4c7aab8e68dfd214c /target/linux/bcm63xx/patches-5.4/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch | |
parent | 9470160c350d15f765c33d6c1db15d6c4709a64c (diff) | |
download | upstream-786bf7fdaca4c75e7eba6e9aa3a8b5775fd21186.tar.gz upstream-786bf7fdaca4c75e7eba6e9aa3a8b5775fd21186.tar.bz2 upstream-786bf7fdaca4c75e7eba6e9aa3a8b5775fd21186.zip |
kernel: delete Linux 5.4 config and patches
As the upcoming release will be based on Linux 5.10 only, remove all
kernel configuration as well as patches for Linux 5.4.
There were no targets still actively using Linux 5.4.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 3a14580411adfb75f9a44eded9f41245b9e44606)
Diffstat (limited to 'target/linux/bcm63xx/patches-5.4/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch')
-rw-r--r-- | target/linux/bcm63xx/patches-5.4/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch | 77 |
1 files changed, 0 insertions, 77 deletions
diff --git a/target/linux/bcm63xx/patches-5.4/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch b/target/linux/bcm63xx/patches-5.4/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch deleted file mode 100644 index 07d3f9dbc8..0000000000 --- a/target/linux/bcm63xx/patches-5.4/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch +++ /dev/null @@ -1,77 +0,0 @@ -From c50acd37b425a8a907a6f7f93aa2e658256e79ce Mon Sep 17 00:00:00 2001 -From: Jonas Gorski <jogo@openwrt.org> -Date: Sat, 7 Dec 2013 14:08:36 +0100 -Subject: [PATCH 40/53] MIPS: BCM63XX: add a new cpu variant helper - ---- - arch/mips/bcm63xx/cpu.c | 10 ++++++++++ - arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++ - 2 files changed, 28 insertions(+) - ---- a/arch/mips/bcm63xx/cpu.c -+++ b/arch/mips/bcm63xx/cpu.c -@@ -27,6 +27,8 @@ EXPORT_SYMBOL(bcm63xx_irqs); - u16 bcm63xx_cpu_id __read_mostly; - EXPORT_SYMBOL(bcm63xx_cpu_id); - -+static u32 bcm63xx_cpu_variant __read_mostly; -+ - static u8 bcm63xx_cpu_rev; - static unsigned int bcm63xx_cpu_freq; - static unsigned int bcm63xx_memory_size; -@@ -99,6 +101,13 @@ static const int bcm6368_irqs[] = { - - }; - -+u32 bcm63xx_get_cpu_variant(void) -+{ -+ return bcm63xx_cpu_variant; -+} -+ -+EXPORT_SYMBOL(bcm63xx_get_cpu_variant); -+ - u8 bcm63xx_get_cpu_rev(void) - { - return bcm63xx_cpu_rev; -@@ -333,6 +342,7 @@ void __init bcm63xx_cpu_init(void) - /* read out CPU type */ - tmp = bcm_readl(chipid_reg); - bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; -+ bcm63xx_cpu_variant = bcm63xx_cpu_id; - bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; - - switch (bcm63xx_cpu_id) { ---- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h -+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h -@@ -20,6 +20,7 @@ - #define BCM6368_CPU_ID 0x6368 - - void __init bcm63xx_cpu_init(void); -+u32 bcm63xx_get_cpu_variant(void); - u8 bcm63xx_get_cpu_rev(void); - unsigned int bcm63xx_get_cpu_freq(void); - -@@ -83,6 +84,23 @@ static inline u16 __pure bcm63xx_get_cpu - #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) - #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) - -+#define BCMCPU_VARIANT_IS_3368() \ -+ (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) -+#define BCMCPU_VARIANT_IS_6328() \ -+ (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID) -+#define BCMCPU_VARIANT_IS_6338() \ -+ (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID) -+#define BCMCPU_VARIANT_IS_6345() \ -+ (bcm63xx_get_cpu_variant() == BCM6345_CPU_ID) -+#define BCMCPU_VARIANT_IS_6348() \ -+ (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID) -+#define BCMCPU_VARIANT_IS_6358() \ -+ (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID) -+#define BCMCPU_VARIANT_IS_6362() \ -+ (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) -+#define BCMCPU_VARIANT_IS_6368() \ -+ (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) -+ - /* - * While registers sets are (mostly) the same across 63xx CPU, base - * address of these sets do change. |