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author | Rafał Miłecki <rafal@milecki.pl> | 2022-03-30 23:21:32 +0200 |
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committer | Rafał Miłecki <rafal@milecki.pl> | 2022-03-30 23:22:46 +0200 |
commit | 9ac80a47ea03361993386c100deba2aa164991ad (patch) | |
tree | 96c82b237e4779a87326f34ecd1e9cd9dc72ed20 /target/linux/bcm53xx/patches-5.15/030-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch | |
parent | c41da167d21612916376c9125e8c75ed6fe706fe (diff) | |
download | upstream-9ac80a47ea03361993386c100deba2aa164991ad.tar.gz upstream-9ac80a47ea03361993386c100deba2aa164991ad.tar.bz2 upstream-9ac80a47ea03361993386c100deba2aa164991ad.zip |
bcm53xx: prepare kernel 5.15 support
Tested on Luxul XWR-3150 (boot, NAND, PCIe, switch, Ethernet).
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Diffstat (limited to 'target/linux/bcm53xx/patches-5.15/030-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch')
-rw-r--r-- | target/linux/bcm53xx/patches-5.15/030-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/target/linux/bcm53xx/patches-5.15/030-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch b/target/linux/bcm53xx/patches-5.15/030-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch new file mode 100644 index 0000000000..39a69bd9a8 --- /dev/null +++ b/target/linux/bcm53xx/patches-5.15/030-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch @@ -0,0 +1,90 @@ +From 2addf9266a1d0f4ba59c9868b3effcd50de441a4 Mon Sep 17 00:00:00 2001 +From: Matthew Hagan <mnhagan88@gmail.com> +Date: Fri, 6 Aug 2021 21:44:33 +0100 +Subject: [PATCH] ARM: dts: NSP: Add Ax stepping modifications + +While uncommon, some Ax NSP SoCs exist in the wild. This stepping +requires a modified secondary CPU boot-reg and removal of DMA coherency +properties. Without these modifications, the secondary CPU will be +inactive and many peripherals will exhibit undefined behaviour. + +Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> +Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> +--- + arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 +++++++++++++++++++++++++++++++ + 1 file changed, 70 insertions(+) + create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi + +--- /dev/null ++++ b/arch/arm/boot/dts/bcm-nsp-ax.dtsi +@@ -0,0 +1,70 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT ++/* ++ * Broadcom Northstar Plus Ax stepping-specific bindings. ++ * Notable differences from B0+ are the secondary-boot-reg and ++ * lack of DMA coherency. ++ */ ++ ++&cpu1 { ++ secondary-boot-reg = <0xffff042c>; ++}; ++ ++&dma { ++ /delete-property/ dma-coherent; ++}; ++ ++&sdio { ++ /delete-property/ dma-coherent; ++}; ++ ++&amac0 { ++ /delete-property/ dma-coherent; ++}; ++ ++&amac1 { ++ /delete-property/ dma-coherent; ++}; ++ ++&amac2 { ++ /delete-property/ dma-coherent; ++}; ++ ++&ehci0 { ++ /delete-property/ dma-coherent; ++}; ++ ++&mailbox { ++ /delete-property/ dma-coherent; ++}; ++ ++&xhci { ++ /delete-property/ dma-coherent; ++}; ++ ++&ehci0 { ++ /delete-property/ dma-coherent; ++}; ++ ++&ohci0 { ++ /delete-property/ dma-coherent; ++}; ++ ++&i2c0 { ++ /delete-property/ dma-coherent; ++}; ++ ++&sata { ++ /delete-property/ dma-coherent; ++}; ++ ++&pcie0 { ++ /delete-property/ dma-coherent; ++}; ++ ++&pcie1 { ++ /delete-property/ dma-coherent; ++}; ++ ++&pcie2 { ++ /delete-property/ dma-coherent; ++}; |