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| author | Rafał Miłecki <rafal@milecki.pl> | 2020-03-10 15:46:49 +0100 |
|---|---|---|
| committer | Rafał Miłecki <rafal@milecki.pl> | 2020-03-10 15:50:55 +0100 |
| commit | d369d92fc7ed2970540235b27441f75a81ef171b (patch) | |
| tree | 248c5980fda5e8631c4c7b58a2bf55756e475b1d /target/linux/bcm47xx/patches-5.4/976-ssb_increase_pci_delay.patch | |
| parent | 5c98041d5a054bfe68070bbfa6fdeab63e6586fc (diff) | |
| download | upstream-d369d92fc7ed2970540235b27441f75a81ef171b.tar.gz upstream-d369d92fc7ed2970540235b27441f75a81ef171b.tar.bz2 upstream-d369d92fc7ed2970540235b27441f75a81ef171b.zip | |
bcm47xx: add support for kernel 5.4
Ethernet, switch, LEDs, buttons, USB, sysupgrade & LuCI were
successfully tested on BCM4706.
WARNING: Hack for BCM4710 adding BCM4710_PROTECTED_FILL_TLB() to the
local_r4k_flush_cache_sigtramp() could not be ported. That function has
been dropped in:
commit adcc81f148d7 ("MIPS: math-emu: Write-protect delay slot emulation pages")
commit 3315b6b336c8 ("MIPS: Delete unused flush_cache_sigtramp()")
it's unsure if that chipset will still work reliably.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Diffstat (limited to 'target/linux/bcm47xx/patches-5.4/976-ssb_increase_pci_delay.patch')
| -rw-r--r-- | target/linux/bcm47xx/patches-5.4/976-ssb_increase_pci_delay.patch | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/linux/bcm47xx/patches-5.4/976-ssb_increase_pci_delay.patch b/target/linux/bcm47xx/patches-5.4/976-ssb_increase_pci_delay.patch new file mode 100644 index 0000000000..99aa188374 --- /dev/null +++ b/target/linux/bcm47xx/patches-5.4/976-ssb_increase_pci_delay.patch @@ -0,0 +1,11 @@ +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -390,7 +390,7 @@ static void ssb_pcicore_init_hostmode(st + set_io_port_base(ssb_pcicore_controller.io_map_base); + /* Give some time to the PCI controller to configure itself with the new + * values. Not waiting at this point causes crashes of the machine. */ +- mdelay(10); ++ mdelay(300); + register_pci_controller(&ssb_pcicore_controller); + } + |