bcm27xx: import latest patches from the RPi foundation

bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

1 files changed, 89 insertions, 0 deletions

diff --git a/target/linux/bcm27xx/patches-5.4/950-0707-vc4_hdmi-Adjust-CEC-ref-clock-based-on-its-input-clo.patch b/target/linux/bcm27xx/patches-5.4/950-0707-vc4_hdmi-Adjust-CEC-ref-clock-based-on-its-input-clo.patch
new file mode 100644
index 0000000000..f6145e4ff5
--- /dev/null
+++ b/target/linux/bcm27xx/patches-5.4/950-0707-vc4_hdmi-Adjust-CEC-ref-clock-based-on-its-input-clo.patch
@@ -0,0 +1,89 @@
+From 32e84f4f525e2a0d7dc021b5795df34407096b0e Mon Sep 17 00:00:00 2001
+From: Dom Cobley <popcornmix@gmail.com>
+Date: Thu, 7 May 2020 18:16:08 +0100
+Subject: [PATCH] vc4_hdmi: Adjust CEC ref clock based on its input
+ clock
+
+2711 uses a fixed 27MHz input, earlier models use the HSM clock
+
+Signed-off-by: Dom Cobley <popcornmix@gmail.com>
+---
+ drivers/gpu/drm/vc4/vc4_hdmi.c | 11 ++++++++---
+ drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++
+ 2 files changed, 11 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
++++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
+@@ -79,6 +79,7 @@
+ # define VC4_HD_M_ENABLE			BIT(0)
+ 
+ #define CEC_CLOCK_FREQ 40000
++#define VC4_HSM_CLOCK 163682864
+ 
+ static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
+ {
+@@ -755,8 +756,7 @@ static u32 vc4_hdmi_calc_hsm_clock(struc
+ 	 * needs to be a bit higher than the pixel clock rate
+ 	 * (generally 148.5Mhz).
+ 	 */
+-
+-	return 163682864;
++	return VC4_HSM_CLOCK;
+ }
+ 
+ static u32 vc5_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
+@@ -1400,6 +1400,7 @@ static int vc4_hdmi_cec_init(struct vc4_
+ 	struct cec_connector_info conn_info;
+ 	struct platform_device *pdev = vc4_hdmi->pdev;
+ 	u32 value;
++	u32 clk_cnt;
+ 	int ret;
+ 
+ 	if (!vc4_hdmi->variant->cec_available)
+@@ -1424,8 +1425,9 @@ static int vc4_hdmi_cec_init(struct vc4_
+ 	 * divider: the hsm_clock rate and this divider setting will
+ 	 * give a 40 kHz CEC clock.
+ 	 */
++	clk_cnt = vc4_hdmi->variant->cec_input_clock / CEC_CLOCK_FREQ;
+ 	value |= VC4_HDMI_CEC_ADDR_MASK |
+-		 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
++		 ((clk_cnt-1) << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
+ 	HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
+ 	ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
+ 					vc4_cec_irq_handler,
+@@ -1770,6 +1772,7 @@ static int vc4_hdmi_dev_remove(struct pl
+ 
+ static const struct vc4_hdmi_variant bcm2835_variant = {
+ 	.max_pixel_clock	= 162000000,
++	.cec_input_clock	= VC4_HSM_CLOCK,
+ 	.audio_available	= true,
+ 	.cec_available		= true,
+ 	.registers		= vc4_hdmi_fields,
+@@ -1794,6 +1797,7 @@ static const struct vc4_hdmi_variant bcm
+ 	.id			= 0,
+ 	.audio_available	= true,
+ 	.max_pixel_clock	= 297000000,
++	.cec_input_clock	= 27000000,
+ 	.registers		= vc5_hdmi_hdmi0_fields,
+ 	.num_registers		= ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
+ 	.phy_lane_mapping	= {
+@@ -1821,6 +1825,7 @@ static const struct vc4_hdmi_variant bcm
+ 	.id			= 1,
+ 	.audio_available	= true,
+ 	.max_pixel_clock	= 297000000,
++	.cec_input_clock	= 27000000,
+ 	.registers		= vc5_hdmi_hdmi1_fields,
+ 	.num_registers		= ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
+ 	.phy_lane_mapping	= {
+--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
++++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
+@@ -48,6 +48,9 @@ struct vc4_hdmi_variant {
+ 	/* Maximum pixel clock supported by the controller (in Hz) */
+ 	unsigned long long max_pixel_clock;
+ 
++	/* Input clock frequency of CEC block (in Hz) */
++	unsigned long cec_input_clock;
++
+ 	/* List of the registers available on that variant */
+ 	const struct vc4_hdmi_register *registers;
+