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authorÁlvaro Fernández Rojas <noltari@gmail.com>2020-05-28 19:08:55 +0200
committerÁlvaro Fernández Rojas <noltari@gmail.com>2020-05-28 19:12:43 +0200
commit77e97abf129c5028385dd72587eabab68db0d954 (patch)
treefc52a8c2ba346da77281f00538a1eb6de49deb5d /target/linux/bcm27xx/patches-5.4/950-0557-drm-vc4-crtc-Move-the-cob-allocation-outside-of-bind.patch
parent5d3a0c6b26144eb5d62515b99613b5ad8dbdc717 (diff)
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bcm27xx: update to latest patches from RPi foundation
Also removes random module and switches to new bcm2711 thermal driver. Boot tested on RPi 4B v1.1 4G. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Diffstat (limited to 'target/linux/bcm27xx/patches-5.4/950-0557-drm-vc4-crtc-Move-the-cob-allocation-outside-of-bind.patch')
-rw-r--r--target/linux/bcm27xx/patches-5.4/950-0557-drm-vc4-crtc-Move-the-cob-allocation-outside-of-bind.patch110
1 files changed, 110 insertions, 0 deletions
diff --git a/target/linux/bcm27xx/patches-5.4/950-0557-drm-vc4-crtc-Move-the-cob-allocation-outside-of-bind.patch b/target/linux/bcm27xx/patches-5.4/950-0557-drm-vc4-crtc-Move-the-cob-allocation-outside-of-bind.patch
new file mode 100644
index 0000000000..83c49132a3
--- /dev/null
+++ b/target/linux/bcm27xx/patches-5.4/950-0557-drm-vc4-crtc-Move-the-cob-allocation-outside-of-bind.patch
@@ -0,0 +1,110 @@
+From e93fc4ed811c7dcc6b0c93716f760431fc645ba2 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime@cerno.tech>
+Date: Thu, 26 Dec 2019 15:48:09 +0100
+Subject: [PATCH] drm/vc4: crtc: Move the cob allocation outside of
+ bind
+
+The COB allocation depends on the HVS channel used for a given
+pixelvalve.
+
+While the channel allocation was entirely static in vc4, vc5 changes
+that and at bind time, a pixelvalve can be assigned to multiple
+HVS channels.
+
+Let's prepare that rework by allocating the COB when it's actually
+needed.
+
+Signed-off-by: Maxime Ripard <maxime@cerno.tech>
+---
+ drivers/gpu/drm/vc4/vc4_crtc.c | 39 +++++++++++++++++-----------------
+ drivers/gpu/drm/vc4/vc4_drv.h | 2 --
+ 2 files changed, 20 insertions(+), 21 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_crtc.c
++++ b/drivers/gpu/drm/vc4/vc4_crtc.c
+@@ -65,6 +65,23 @@ static const struct debugfs_reg32 crtc_r
+ VC4_REG32(PV_HACT_ACT),
+ };
+
++static unsigned int
++vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc, unsigned int channel)
++{
++ struct drm_device *drm = vc4_crtc->base.dev;
++ struct vc4_dev *vc4 = to_vc4_dev(drm);
++
++ u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
++ /* Top/base are supposed to be 4-pixel aligned, but the
++ * Raspberry Pi firmware fills the low bits (which are
++ * presumably ignored).
++ */
++ u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
++ u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
++
++ return top - base + 4;
++}
++
+ bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
+ bool in_vblank_irq, int *vpos, int *hpos,
+ ktime_t *stime, ktime_t *etime,
+@@ -73,6 +90,7 @@ bool vc4_crtc_get_scanoutpos(struct drm_
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
++ unsigned int cob_size;
+ u32 val;
+ int fifo_lines;
+ int vblank_lines;
+@@ -108,8 +126,9 @@ bool vc4_crtc_get_scanoutpos(struct drm_
+ *hpos += mode->crtc_htotal / 2;
+ }
+
++ cob_size = vc4_crtc_get_cob_allocation(vc4_crtc, vc4_crtc->channel);
+ /* This is the offset we need for translating hvs -> pv scanout pos. */
+- fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
++ fifo_lines = cob_size / mode->crtc_hdisplay;
+
+ if (fifo_lines > 0)
+ ret = true;
+@@ -1104,22 +1123,6 @@ static void vc4_set_crtc_possible_masks(
+ }
+ }
+
+-static void
+-vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
+-{
+- struct drm_device *drm = vc4_crtc->base.dev;
+- struct vc4_dev *vc4 = to_vc4_dev(drm);
+- u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
+- /* Top/base are supposed to be 4-pixel aligned, but the
+- * Raspberry Pi firmware fills the low bits (which are
+- * presumably ignored).
+- */
+- u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
+- u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
+-
+- vc4_crtc->cob_size = top - base + 4;
+-}
+-
+ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
+ {
+ struct platform_device *pdev = to_platform_device(dev);
+@@ -1174,8 +1177,6 @@ static int vc4_crtc_bind(struct device *
+ */
+ drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
+
+- vc4_crtc_get_cob_allocation(vc4_crtc);
+-
+ CRTC_WRITE(PV_INTEN, 0);
+ CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
+ ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
+--- a/drivers/gpu/drm/vc4/vc4_drv.h
++++ b/drivers/gpu/drm/vc4/vc4_drv.h
+@@ -477,8 +477,6 @@ struct vc4_crtc {
+ u8 lut_r[256];
+ u8 lut_g[256];
+ u8 lut_b[256];
+- /* Size in pixels of the COB memory allocated to this CRTC. */
+- u32 cob_size;
+
+ struct drm_pending_vblank_event *event;
+